HI1-0539-5_技术文档

HI-539

Data Sheet

July 1999

File Number 3149.2

Precision, 4-Channel, Low-Level,

Differential Multiplexer

Features

• Differential Performance, Typical:

o

The Intersil HI-539 is a monolithic, 4-Channel, differential

multiplexer. Two digital inputs are provided for channel

selection, plus an Enable input to disconnect all channels.

- Low ∆r , 125 C . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5Ω

ON

o

- Low ∆I

D(ON)

- Low ∆ Charge Injection . . . . . . . . . . . . . . . . . . . . 0.1pC

, 125 C. . . . . . . . . . . . . . . . . . . . . . . 0.6nA

- Low Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . -124dB

Performance is guaranteed for each channel over the

voltage range ±10V, but is optimized for low level differential

signals. Leakage current, for example, which varies slightly

with input voltage, has its distribution centered at zero input

volts.

• Settling Time, ±0.01% . . . . . . . . . . . . . . . . . . . . . . . 900ns

• Wide Supply Range . . . . . . . . . . . . . . . . . . . ±5V to ±18V

• Break-Before-Make Switching

In most monolithic multiplexers, the net differential offset due

to thermal effects becomes signiﬁcant for low level signals.

This problem is minimized in the HI-539 by symmetrical

placement of critical circuitry with respect to the few heat

producing devices.

• No Latch-Up

Applications

• Low Level Data Acquisition

• Precision Instrumentation

• Test Systems

Supply voltages are ±15V and power consumption is only

2.5mW.

Ordering Information

TRUTH TABLE

TEMP.

PKG.

NO.

ON CHANNEL TO

o

PART NUMBER RANGE ( C)

PACKAGE

EN

L

A

OUT A

None

1A

OUT B

None

1B

1

0

HI1-0539-5

HI1-0539-8

HI3-0539-5

HI4P0539-5

0 to 75

16 Ld CERDIP

F16.3

X

-55 to 125 16 Ld CERDIP

F16.3

E16.3

N20.35

H

L

H

L

0 to 75

16 Ld PDIP

20 Ld PLCC

H

2A

2B

H

3A

3B

H

4A

4B

Pinouts

HI-539

(CERDIP, PDIP)

HI-539

(PLCC)

TOP VIEW

A

1

2

3

4

5

6

7

8

16 A

1

0

3

2

1

20 19

EN

V-

15 GND

14 V+

4

5

6

7

8

18 V+

V-

IN 1A

NC

IN 1A

IN 2A

IN 3A

IN 4A

OUT A

13 IN 1B

12 IN 2B

11 IN 3B

10 IN 4B

17

16

15

IN 1B

NC

IN 2A

IN 3A

IN 2B

14 IN 3B

9

OUT B

9

10 11 12 13

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

HI-539

Absolute Maximum Ratings

Thermal Information

o

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V

V+ or V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V

Thermal Resistance (Typical, Note 1)

θ

( C/W)

θ

( C/W)

JA

JC

CERDIP Package. . . . . . . . . . . . . . . . .

PDIP Package . . . . . . . . . . . . . . . . . . .

PLCC Package. . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature

85

90

80

32

N/A

Analog Signal (V , V

). . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+

IN OUT

Digital Input Voltage (V , V ) . . . . . . . . . . . . . . . . . . . . . . V- to V+

EN

A

Analog Current (IN or OUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

o

Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C

Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

o

Operating Conditions

o

Temperature Range

HI-539-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C

HI-539-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C

o

(PLCC - Lead Tips Only)

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

JA

Electrical Speciﬁcations Supplies = ±15V, V = 4V, V (Logic Level High) = 4V, V (Logic Level Low) = 0.8V,

EN

AH

AL

Unless Otherwise Speciﬁed

-8

-5

TEST

CONDITIONS

TEMP

( C)

o

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

DYNAMIC CHARACTERISTICS

Access Time, t

25

Full

25

-

250

-

750

-

250

-

750

ns

µs

pC

dB

pF

A

1,000

Break-Before-Make Delay, t

30

-

85

-

30

-

85

-

OPEN

Full

25

-

Enable Delay (ON), t

250

-

750

250

-

750

ON(EN)

Full

25

-

1,000

-

1,000

Enable Delay (OFF), t

-

160

-

650

-

160

-

650

OFF(EN)

Full

25

-

900

-

900

Settling Time

To 0.01%

-

0.9

3

-

0.9

3

-

Charge Injection (Output)

∆ Charge Injection (Output)

Charge Injection (Input)

Differential Crosstalk

Full

25

-

0.1

10

-124

-100

5

-

0.1

10

-124

-100

5

-

Note 4

-

Single Ended Crosstalk

Channel Input Capacitance,

25

-

Full

-

C

S(OFF)

Channel Output Capacitance,

Full

-

7

17

0.08

3

-

7

17

0.08

3

-

pF

C

D(OFF)

Channel On Output Capacitance,

C

D(ON)

Input to Output Capacitance,

Note 5

C

DS(OFF)

Digital Input Capacitance, C

A

DIGITAL INPUT CHARACTERISTICS

Input Low Threshold, V

Full

-

4.0

-

0.8

-

4.0

-

0.8

-

V

AL

Input High Threshold, V

AH

Input Leakage Current (High), I

1

µA

AH

AL

Input Leakage Current (Low), I

-

1

-

1

2

HI-539

Electrical Speciﬁcations Supplies = ±15V, V = 4V, V (Logic Level High) = 4V, V (Logic Level Low) = 0.8V,

EN

AH

AL

Unless Otherwise Speciﬁed (Continued)

-8

-5

TEST

CONDITIONS

TEMP

( C)

o

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

ANALOG CHANNEL CHARACTERISTICS

Analog Signal Range, V

Full

25

-10

-

650

950

700

1.1K

4.0

4.75

4.5

5.5

30

+10

-10

-

+10

850

1K

900

1.1K

24

27

-

V

IN

On Resistance, r

V

= 0V

850

650

800

700

900

4.0

4.5

30

Ω

ON

IN

lN

IN

lN

Full

25

1.3K

Ω

= ±10V

= 0V

900

1.4K

24

28

27

33

-

Ω

Full

25

Ω

∆r

ON,

(Side A-Side B)

Ω

Full

25

Ω

= ±10V

Ω

Full

25

Ω

Off Input Leakage Current, I

Condition 0V

(Note 2)

pA

nA

pA

nA

pA

nA

pA

nA

pA

nA

pA

nA

pA

nA

pA

nA

pA

nA

pA

nA

pA

nA

pA

nA

µV

S(OFF)

Full

25

2

10

-

0.2

100

0.5

3

1

Condition ±10V

(Note 2)

100

5

-

Full

25

-

2.5

-

∆I

S(OFF),

(Side A-Side B)

Condition 0V

3

Full

25

0.2

10

2

0.02

10

0.2

-

Condition ±10V

-

Full

25

0.5

30

5

0.05

30

0.5

-

Off Output Leakage Current,

Condition 0V

(Note 2)

-

I

D(OFF)

Full

25

2

10

-

0.2

100

0.5

3

1

Condition ±10V

(Note 2)

100

5

-

Full

25

-

2.5

-

∆I

D(OFF),

(Side A-Side B)

Condition 0V

3

Full

25

0.2

10

2

0.02

10

0.2

-

Condition ±10V

-

Full

25

0.5

50

5

0.05

50

0.5

-

On Channel Leakage Current, I

Condition 0V

(Note 2)

-

D(ON)

Full

25

5

25

-

0.5

150

0.8

10

2.5

-

Condition ±10V

(Note 2)

150

6

Full

25

40

-

4.0

-

∆I

D(ON),

(Side A-Side B)

Condition 0V

Condition ±10V

Note 3

10

Full

25

0.5

30

5

0.05

30

0.5

-

Full

25

0.6

0.02

0.70

6

0.08

0.02

0.08

0.8

-

Differential Offset Voltage, ∆V

OS

-

Full

-

POWER SUPPLY CHARACTERISTICS

Power Dissipation, P

25

Full

25

-

2.3

-

45

-

2.3

-

45

-

mW

mA

D

-

0.150

-

0.150

-

Current, l+

Full

2.0

3

HI-539

Electrical Speciﬁcations Supplies = ±15V, V = 4V, V (Logic Level High) = 4V, V (Logic Level Low) = 0.8V,

EN

AH

AL

Unless Otherwise Speciﬁed (Continued)

-8

TYP

0.001

-

-5

TYP

0.001

-

TEST

CONDITIONS

TEMP

( C)

o

PARAMETER

MIN

MAX

MIN

MAX

-

UNITS

mA

Current, l-

25

-

Full

1.0

±18

1.0

±18

mA

Supply Voltage Range

NOTES:

±5

±15

±5

±15

V

2. See Figures 2B, 2C, 2D. The condition ±10V means:

and I

l

:

D(OFF)

S(OFF)

(V = +10V, V = -10V), then

S

D

(V = -10V, V = +10V)

S

D

I

: (+10V, then -10V)

D(ON)

3. ∆V

(Exclusive of thermocouple effects) = r

∆I

ON D(ON)

+ I

∆r . See Applications section for discussion of additional V

D(ON) ON

error.

OS

4. V = 1kHz, 15V

on all but the selected channel. See Figure 7.

5. Calculated from typical Single-Ended Crosstalk performance.

lN P-P

o

Test Circuits and Waveforms Unless Otherwise Specified T = 25 C, V+ = +15V, V- = -15V, V = 4V and V = 0.8V

A

AH

AL

V

= 0V

IN

100µA

800

700

600

500

V

2

IN

OUT

r

V

2

HI-539

V

=

IN

ON

100µA

-50

-25

0

25

50

75

100

125

o

TEMPERATURE ( C)

FIGURE 1A. TEST CIRCUIT

FIGURE 1B. ON RESISTANCE vs TEMPERATURE

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

900

800

700

600

500

400

o

125 C

V

= 0V

IN

o

25 C

o

-55 C

-12 -10 -8 -6 -4

-2

0

2

4

6

8

10 12

5

7

9

11

13

15

17

ANALOG INPUT (V)

SUPPLY VOLTAGE (±V)

FIGURE 1C. ON RESISTANCE vs ANALOG INPUT VOLTAGE

FIGURE 1D. ON RESISTANCE vs SUPPLY VOLTAGE

FIGURE 1. ON RESISTANCE

4

HI-539

o

Test Circuits and Waveforms Unless Otherwise Specified T = 25 C, V+ = +15V, V- = -15V, V = 4V and V = 0.8V (Continued)

A

AH

AL

10

HI-539†

0.8V

EN

I

OUT A

A

D(ON)

1

I

D(OFF)

±

I

= I

S(OFF)

±10V

10V

D(OFF)

A

1

0

25

50

75

100

125

† Similar Connection For Side “B”

o

TEMPERATURE ( C)

FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE

FIGURE 2B. I TEST CIRCUIT (NOTE 6)

D(OFF)

HI-539†

^HI-539†

OUT A

I

A

I

S(OFF)

0.8V

D(ON)

EN

A

1

EN

0

±

±10V

10V

±

±10V

10V

A

1

4V

0

†Similar Connection For Side “B”

FIGURE 2C. I

TEST CIRCUIT (NOTE 6)

FIGURE 2D. I

D(ON)

TEST CIRCUIT (NOTE 6)

S(OFF)

NOTE:

±

6. Three measurements = ±10V, 10V, and 0V.

FIGURE 2. LEAKAGE CURRENT

+15V/+10V

+I

14

SUPPLY

A

FUNCTIONAL LIMIT

12

10

V+

+10V/+5V

^HI-539†^{IN 1A}

A

1

V

= ±15V

IN 2A

0

SUPPLY

8

6

4

2

V

50Ω

V

= ±10V

A

SUPPLY

IN 3A

IN 4A

-10V/-5V

5V

EN

OUT A

V-

GND

10MΩ

14pF

HIGH = 4.0V

LOW = 0V

50% DUTY CYCLE

V

A

-I

A

SUPPLY

0

-15V/-10V

100Hz

1kHz

10kHz

100kHz

1MHz 3MHz 10MHz

TOGGLE FREQUENCY

†Similar Connection For Side “B”

FIGURE 3A. SUPPLY CURRENT vs TOGGLE FREQUENCY

FIGURE 3. DYNAMIC SUPPLY CURRENT

FIGURE 3B. TEST CIRCUIT

5

HI-539

o

Test Circuits and Waveforms Unless Otherwise Specified T = 25 C, V+ = +15V, V- = -15V, V = 4V and V = 0.8V (Continued)

A

AH

AL

+15V

320

300

280

260

240

220

200

V+

IN 1A

±10V

A

1

IN 2A,

IN 3A

0

V

50Ω

A

HI-539

±

10V

IN 4A

EN

OUT A

V-

5V

GND

50

pF

10

kΩ

-15V

3

4

5

6

7

8

9

10 11 12

13 14 15

LOGIC LEVEL (HIGH) (V)

FIGURE 4A. ACCESS TIME vs LOGIC LEVEL (HIGH)

FIGURE 4B. TEST CIRCUIT

V

= 4V

AH

ADDRESS

DRIVE (V )

V

INPUT

A

2V/DIV.

50%

0V

S

ON

1

+10V

OUTPUT

-10V

OUTPUT

5V/DIV.

10%

t

A

S

ON

4

200ns/DIV.

FIGURE 4C. MEASUREMENT POINTS

FIGURE 4D. WAVEFORMS

FIGURE 4. ACCESS TIME

+15V

V+

V

= 4V

AH

+5V

HI-539†

IN 1A

ADDRESS

DRIVE (V )

IN 2, IN 3A

A

0V

A

1

IN 4A

OUTPUT

0

V

OUT

EN

OUT A

V-

50%

5V

GND

700

Ω

V

50Ω

A

12.5pF

t

OPEN

-15V

†Similar connection for side “B”

FIGURE 5B. TEST CIRCUIT

FIGURE 5A. MEASUREMENT POINTS

6

HI-539

o

Test Circuits and Waveforms Unless Otherwise Specified T = 25 C, V+ = +15V, V- = -15V, V = 4V and V = 0.8V (Continued)

A

AH

AL

V

INPUT

A

2V/DIV.

S

ON

S

ON

1

4

OUTPUT

1V/DIV.

100ns/DIV.

FIGURE 5C. WAVEFORMS

FIGURE 5. BREAK-BEFORE-MAKE DELAY

+15V

V+

^HI-539†

V

= 4V

+10V

AH

IN 1A

50% ENABLE DRIVE (V )

50%

A

IN 2A THRU

IN 4A

A

1

0V

0

V

OUT

90%

EN

OUT A

OUTPUT

10%

50

Ω

GND

V-

700

Ω

V

A

12.5pF

0V

t

ON(EN)

-15V

t

OFF(EN)

†^{Similar connection for side “B”}

FIGURE 6A. MEASUREMENT POINTS

FIGURE 6B. TEST CIRCUIT

ENABLE

DRIVE

2V/DIV.

ENABLED

(S ON)

DISABLED

1

OUTPUT

2V/DIV.

100ns/DIV.

FIGURE 6C. WAVEFORMS

FIGURE 6. ENABLE DELAYS

7

HI-539

o

Test Circuits and Waveforms Unless Otherwise Specified T = 25 C, V+ = +15V, V- = -15V, V = 4V and V = 0.8V (Continued)

A

AH

AL

HI-539

INSTRUMENTATION

^AMPLIFIER†

G = 1000

+

G = 1000

+

-

350Ω

-

1kHz,

15V

P-P

350Ω

1kHz,

15V

P-P

†AD606 or BB3630, for Example

†AD606 or BB3630, for example

FIGURE 7B. DIFFERENTIAL CROSSTALK TEST CIRCUIT

FIGURE 7A. SINGLE-ENDED CROSSTALK TEST CIRCUIT

FIGURE 7. CROSSTALK

Coaxial cable is not suitable for low level signals because the

Application Information

two conductors (center and shield) are unbalanced. Also,

ground loops are produced if the shield is grounded at both

ends by standard BNC connectors. If coax must be used, carry

the signal on the center conductors of two equal-length cables

whose shields are terminated only at the transducer end. As a

general rule, terminate (ground) the shield at one end only,

preferably at the end with greatest noise interference. This is

usually the transducer end for both high and low level signals.

General

The Hl-539 accepts inputs in the range -15V to +15V, with

performance guaranteed over the ±10V range. At these

higher levels of analog input voltage it is comparable to the Hl-

509, and is plug-in compatible with that device (as well as the

Hl-509A). However, as mentioned earlier, the Hl-539 was

designed to introduce minimum error when switching low level

inputs.

Watch Small ∆V Errors

Special care is required in working with these low level

signals. The main concern with signals below 100mV is that

noise, offset voltage, and other aberrations can represent a

large percentage error. A shielded differential signal path is

Printed circuit traces and short lengths of wire can add

substantial error to a signal even after it has traveled

hundreds of feet and arrived on a circuit board. Here, the

small voltage drops due to current ﬂow through connections

of a few milliohms must be considered, especially to meet an

accuracy requirement of 12 bits or more.

essential to maintain a noise level below 50µV

.

RMS

Low Level Signal Transmission

The transmission cable carrying the transducer signal is critical

in a low level system. It should be as short as practical and

rigidly supported. Signal conductors should be tightly twisted

for minimum enclosed area to guard against pickup of

electromagnetic interference, and the twisted pair should be

shielded against capacitively coupled (electrostatic)

Table 1 is a useful collection of data for calculating the effect

of these short connections. (Proximity to a ground plane will

lower the values of inductance.)

As an example, suppose the Hl-539 is feeding a 12-bit

1

converter system with an allowable error of ± / LSB

2

(±1.22mV). lf the interface logic draws 100mA from the 5V

supply, this current will produce 1.28mV across 6 inches of

#24 wire; more than the error budget. Obviously, this digital

current must not be routed through any portion of the analog

ground return network.

interference. A braided wire shield may be satisfactory, but a

1

lapped foil shield is better since it allows only / as much

10

leakage capacitance to ground per foot. A key requirement for

the transmission cable is that it presents a balanced line to

sources of noise interference. This means an equal series

impedance in each conductor plus an equally distributed

impedance from each conductor to ground. The result should

be signals equal in magnitude but opposite in phase at any

transverse plane. Noise will be coupled in phase to both

conductors, and may be rejected as common-mode voltage by

a differential amplifier connected to the multiplexer output.

8

HI-539

TABLE 1.

EQUIVALENT WIDTH OF

P.C. CONDUCTOR

(2 oz. Cu)

IMPEDANCE PER FOOT

60Hz

DC RESISTANCE

PER FOOT

INDUCTANCE PER

WIRE GAGE

FOOT

0.36µH

0.37µH

0.40µH

0.42µH

0.45µH

0.49µH

0.53µH

10kHz

0.0235Ω

0.0254Ω

0.0288Ω

0.0345Ω

0.0488Ω

0.0718Ω

0.110Ω

18

20

22

24

26

28

30

32

0.47”

0.30”

0.0064Ω

0.0102Ω

0.0161Ω

0.0257Ω

0.041Ω

0.066Ω

0.105Ω

0.168Ω

0.0064Ω

0.0102Ω

0.0161Ω

0.0257Ω

0.041Ω

0.066Ω

0.105Ω

0.168Ω

0.19”

0.12”

0.075”

0.047”

0.029”

0.018”

0.171Ω

Provide Path For I

Differential Offset, ∆V

OS

BIAS

The input bias current for any DC-coupled ampliﬁer must

have an external path back to the ampliﬁer’s power supply.

No such path exists in Figure 8A, and consequently the

ampliﬁer output will remain in saturation.

There are two major sources of ∆V . That part due to the

OS

∆r ) becomes signiﬁcant

expression (r

∆l

+ l

ON D(ON) D(ON) ON

with increasing temperature, as shown in the Electrical

Speciﬁcations tables. The other source of offset is the

thermocouple effects due to dissimilar materials in the signal

path. These include silicon, aluminum, tin, nickel-iron and

(often) gold, just to exit the package.

A single large resistor (1MΩ to 10MΩ) from either signal line

to power supply common will provide the required path, but a

resistor on each line is necessary to preserve accuracy. A

single pair of these bias current resistors on the HI-539

output may be used if their loading effect can be tolerated

For the thermocouple effects in the package alone, the

constraint on ∆V

may be stated in terms of a limit on the

OS

(each forms a voltage divider with r ). Otherwise, a resistor

pair on each input channel of the multiplexer is required.

difference in temperature for package pins leading to any

channel of the Hl-539. For example, a difference of 0.13 C

ON

o

produces a 5µV offset. Obviously, this ∆T effect can

The use of bias current resistors is acceptable only if one is

conﬁdent that the sum of signal plus common-mode voltage

will remain within the input range of the multiplexer/ampliﬁer

combination.

dominate the ∆V

parameter at any temperature unless

OS

care is taken in mounting the Hl-539 package.

Temperature gradients across the Hl-539 package should be

held to a minimum in critical applications. Locate the Hl-539

far from heat producing components, with any air currents

ﬂowing lengthwise across the package.

Another solution is to simply run a third wire from the low

side of the signal source, as in Figure 8B. This wire assures

a low common-mode voltage as well as providing the path

for bias currents. Making the connection near the multiplexer

will save wire, but it will also unbalance the line and reduce

the ampliﬁer's common-mode rejection.

9

HI-539

V+

V-

r

ON

+

“FLOATING”

SOURCE

ON

-

FIGURE 8A.

HI-539

V+

r

ON

+

ON

-

V-

1M TO 10M

POWER SUPPLY

COMMON

POWER SUPPLY

COMMON

NOTE: The ampliﬁer in Figure 8A is unusable because its bias currents cannot return to the power supply. Figure 8B shows two alternative paths

for these bias currents: either a pair of resistors, or (better) a third wire from the low side of the signal source.

FIGURE 8B.

10

HI-539

Die Characteristics

DIE DIMENSIONS:

PASSIVATION:

92 mils x 100 mils

Type: Nitride Over Silox

Nitride Thickness: 3.5kÅ ±1kÅ

Silox Thickness: 12kÅ ±2.0kÅ

METALLIZATION:

Type: AlCu

Thickness: 16kÅ ±2kÅ

WORST CASE CURRENT DENSITY:

5

2

2.54 x 10 A/cm at 20mA

SUBSTRATE POTENTIAL (NOTE):

TRANSISTOR COUNT:

-V

SUPPLY

236

PROCESS:

CMOS-DI

NOTE: The substrate appears resistive to the -V

SUPPLY

terminal, therefore it may be left ﬂoating (Insulating Die Mount) or it may be mounted on a

conductor at -V

potential.

SUPPLY

Metallization Mask Layout

HI-539

V-

EN

A

GND

V+

0

1

IN1B

IN2B

IN1A

IN2A

IN3A

IN4A

OUTA

OUTB

IN4B

IN3B

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

11


型号：	HI1-0539-5
厂家：	Intersil
描述：	Precision, 4-Channel, Low-Level, Differential Multiplexer 精密， 4通道，低层次的，差分多路复用器复用器
文件：	总11页 (文件大小：192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HI1-0539-5 [INTERSIL]

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