HA-5101883 [INTERSIL]
Low Noise, High Performance Operational Amplifier; 低噪声，高性能运算放大器
| 型号： | HA-5101883 |
| 厂家： | 
Intersil |
| 描述： | Low Noise, High Performance Operational Amplifier |
| 文件： | 总16页 (文件大小：1176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-5101/883
®
Data Sheet
August 17, 2005
FN3931.1
Low Noise, High Performance Operational
Amplifier
The HA-5101/883 is a dielectrically isolated operational
amplifier featuring low noise and high performance. This
amplifier has an excellent noise voltage density of
4.5nV/√Hz (max) at 1kHz. The unity gain stable
HA-5101/883 yields a 10MHz unity gain bandwidth and a
6V/µs slew rate.
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Noise Voltage @ 1kHz . . . . . . . . . . . 4.5nV/√Hz Max
• Low Noise Current @ 1kHz . . . . . . . . . . . . . 3pA/√Hz Max
• Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . 10MHz Min
DC characteristics of the HA-5101/883 assure accurate
performance. The 3mV (max) offset voltage is externally
adjustable and offset voltage drift is just 3µV/°C. Low bias
currents (200nA max) reduce input current errors and the
high open loop voltage gain of 100kV/V, over temperature,
increases the loop gain for low distortion amplification.
• High Gain (Full Temp) . . . . . . . . . . . . . . . . . .100kV/V Min
(Room Temp) . . . . . . . . . . . . . . . . . 1MV/V Typ
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V/µs Min
• High CMRR/PSRR (Full Temp) . . . . . . . . . . . . . 80dB Min
• High Output Drive Capability (Full Temp). . . . . . . . . 25mA
The HA-5101/883 is ideal for audio applications, especially
low-level signal amplifiers such as microphone, tape head
and preamplifiers. Additionally, it is well suited for low
distortion oscillators, low noise function generators and high
Q filters.
Applications
• High Quality Audio Preamplifiers
• High Q Active Filters
• Low Noise Function Generators
• Low Distortion Oscillators
• Low Noise Comparators
Ordering Information
TEMP.
PKG.
PART NUMBER RANGE (°C)
PACKAGE
DWG. #
HA7-5101/883
-55 to 125 8 Ld CerDIP
F8.3A
5962-89636012A
-55 to 125 20 Ld Ceramic LCC J20.A
Pinouts
HA7-5101/883 (CERDIP)
5962-896360 (CLCC)
TOP VIEW
TOP VIEW
3
2
1
20 19
BAL
-IN
1
2
3
4
8
7
6
5
NC
NC
V+
18
17
NC
-IN
4
5
6
7
8
V+
-
+
-
16 NC
NC
+IN
NC
OUT
+IN
V-
+
15 OUT
BAL
NC
14
9
10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1994, 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HA-5101/883
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 40V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . V+ to V-
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite
Thermal Resistance
Ceramic DIP Package . . . . . . . . . . . . .
Ceramic LCC Package. . . . . . . . . . . . .
Package Power Dissipation Limit at +75°C for T ≤ +175°C
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.22W
Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.35W
Package Power Dissipation Derating Factor Above +75°C
θ
(°C/W)
120
86
θ
(°C/W)
30
26
JA
JC
J
Junction Temperature (T ). . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
J
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+300°C
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . .12.2mW/°C
Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . .13.5mW/°C
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . -55°C to +125°C
Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . ±5V to ±15V
V
R
≤ 1/2 (V+ - V-)
INcm
≥ 500Ω
L
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V = ±15V, R = 100Ω, R = 500kΩ, V
= 0V, Unless Otherwise Specified
S
S
L
OUT
LIMITS
GROUP A
PARAMETER
Input Offset Voltage
SYMBOL
TEST CONDITIONS
SUBGROUP TEMP (°C)
MIN
MAX
3
UNITS
mV
V
V
V
= 0V
1
+25
-3
-4
IO
CM
CM
2, 3
1
+125, -55
+25
4
mV
Input Bias Current
+I
= 0V
-200
-325
200
325
nA
B
+R = 100kΩ
S
2, 3
+125, -55
nA
-RS = 100Ω
-I
V
= 0V
1
+25
-200
-325
200
325
nA
nA
B
CM
S
+R = 100Ω
2, 3
+125, -55
-RS = 100kΩ
Input Offset Current
I
V
= 0V
CM
S
1
+25
-75
75
nA
nA
IO
+R = 100kΩ
2, 3
+125, -55
-125
125
-RS = 100kΩ
Common Mode Range
+CMR
-CMR
V+ = 3V
1
2, 3
1
+25
+125, -55
+25
12
12
-
-
V
V
V- = -27V
-
V+ = 27V
V- = -3V
-12
V
2, 3
4
+125, -55
+25
-
-12
V
Large Signal Voltage Gain
+A
VOL
V
R
= 0V and +10V
100
100
100
100
80
80
-
-
-
-
-
-
kV/V
kV/V
kV/V
kV/V
dB
OUT
L
= 2kΩ
5, 6
4
+125, -55
+25
-A
VOL
V
R
= 0V and −10V
OUT
L
= 2kΩ
5, 6
1
+125, -55
+25
Common Mode Rejection Ratio
+CMRR
-CMRR
∆V
= +10V
CM
V+ =+5V
V- = -25V
2, 3
+125, -55
dB
V
= -10V
OUT
∆V
= -10V
1
+25
80
80
-
-
dB
dB
CM
V+ = +25V
V- = -5V
2, 3
+125, -55
V
= +10V
OUT
FN3931.1
2
August 17, 2005
HA-5101/883
TABLE 1. D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: V = ±15V, R = 100Ω, R = 500kΩ, V
= 0V, Unless Otherwise Specified
S
S
L
OUT
LIMITS
GROUP A
PARAMETER
SYMBOL
TEST CONDITIONS
= 2kΩ
SUBGROUP TEMP (°C)
MIN
MAX
UNITS
V
Output Voltage Swing
+V
R
R
1
2, 3
1
+25
+125, -55
+25
12
12
-
-
OUT1
L
L
-
-12
-12
-
V
-V
= 2kΩ
V
OUT1
2, 3
1
+125, -55
+25
-
V
+V
V
= ±18V
= 600Ω
15
15
-
V
OUT2
S
R
L
2, 3
1
+125, -55
+25
-
V
-V
V
= ±18V
= 600Ω
-15
-15
-
V
OUT2
S
R
L
2, 3
1
+125, -55
+25
-
V
Output Current
+I
V
V
= -15V
= +15V
= 0V
25
25
-
mA
mA
mA
mA
mA
mA
mA
mA
dB
dB
OUT
OUT
= ±18V
S
2, 3
1
+125, -55
+25
-
-I
V
V
-25
-25
6
OUT
OUT
= ±18V
S
2, 3
1
+125, -55
+25
-
Quiescent Power Supply Current
Power Supply Rejection Ratio
+I
V
I
-
CC
OUT
OUT
= 0mA
2, 3
1
+125, -55
+25
-
6
-I
V
I
= 0V
-6
-6
80
80
-
CC
OUT
= 0mA
OUT
2, 3
1
+125, -55
+25
-
+PSRR
-PSRR
∆V = 10V
-
S
V+ = +10V, V- = -15V
V+ = +20V, V- = -15V
2, 3
+125, -55
-
∆V = 10V
1
+25
80
80
-
-
dB
dB
S
V+ = +15V, V- = -10V
V+ = +15V, V- = -20V
2, 3
+125, -55
Offset Voltage Adjustment
+V Adj
IO
Note 4
1
+25
V
V
-1
-
-
-
-
mV
mV
mV
mV
IO
R
= 2kΩ, C = 50pF
L
L
2, 3
1
+125, -55
+25
-1
IO
A
= +1V/V
V
-V Adj
IO
V
V
+1
+1
IO
IO
2, 3
+125, -55
TABLE 2. A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V = ±15V, R = 50Ω, R = 2kΩ, C = 50pF, A
= +1V/V, Unless Otherwise Specified
S
S
L
L
VCL
LIMITS
GROUP A
PARAMETER
SYMBOL
+SR
TEST CONDITIONS
= -3V to +3V
SUBGROUP TEMP (°C)
MIN
MAX
-
UNITS
V/µs
V/µs
ns
Slew Rate
V
V
V
4
4
+25
+25
6
6
-
OUT
OUT
OUT
-SR
= +3V to -3V
-
Rise and Fall Time
Overshoot
t
= 0V to +200mV
4
+25
200
400
200
400
35
R
10% ≤ t ≤ 90%
R
5, 6
4
+125, -55
+25
-
ns
t
V
= 0V to -200mV
-
ns
F
OUT
10% ≤ t ≤ 90%
F
5, 6
4
+125, -55
+25
-
ns
+OS
-OS
V
V
= 0V to +200mV
-
%
OUT
OUT
5, 6
4
+125, -55
+25
-
35
%
= 0V to -200mV
-
35
%
5, 6
+125, -55
-
35
%
FN3931.1
3
August 17, 2005
HA-5101/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: V = ±15V, R = 2kΩ, C = 50pF, A = +1, Unless Otherwise Specified
S
L
L
V
LIMITS
PARAMETER
Differential Input Resistance
Low Frequency Peak-to-Peak Noise
Input Noise Voltage Density
Input Noise Current Density
Unity Gain Bandwidth
SYMBOL
TEST CONDITIONS
NOTES
TEMP (°C)
+25
MIN
MAX
UNITS
R
V
= 0V
CM
1
1
250
-
0.2
4.5
3
kΩ
IN
E
0.1Hz to 10Hz
+25
-
-
µV
P-P
nP-P
E
R
R
V
= 20Ω, f = 1000Hz
1
+25
nV/√Hz
pA/√Hz
MHz
kHz
n
S
o
I
= 2MΩ, f = 1000Hz
1
+25
-
n
S
o
UGBW
FPBW
CLSG
= 100mV
= 10V
1
+25
10
95
+1
-
-
O
Full Power Bandwidth
V
1, 2
1
+25
-
PEAK
Minimum Closed Loop Stable Gain
Output Resistance
-55 to +125
+25
-
V/V
R
Open Loop
= 0V, I
1
150
180
Ω
OUT
PC
Quiescent Power Consumption
NOTES:
V
= 0mA
OUT
1, 3
-55 to +125
-
mW
OUT
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters
are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon
data from multiple production runs which reflect lot to lot and within lot variation.
2. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2πV
).
PEAK
3. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.)
4. Offset adjustment range is [V ±1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V.
IO (Measured)
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLES 1 & 2)
Interim Electrical Parameters (Pre Burn-in)
Final Electrical Test Parameters
Group A Test Requirements
1
1*, 2, 3, 4, 5, 6
1, 2, 3, 4, 5, 6
1
Groups C & D Endpoints
*PDA applies to Subgroup 1 only.
FN3931.1
4
August 17, 2005
HA-5101/883
t
t
F
R
t
t
F
R
FN3931.1
5
August 17, 2005
HA-5101/883
Burn-in Circuits
CERAMIC MINI-DIP
1
2
3
4
8
V+
7
-
+
D
1
6
C
C
3
1
V-
5
D
C
R
1
2
2
CERAMIC LCC
NOTES:
R
C
C
D
= 1MΩ, ±5%, 1/4W (Min)
1
1
3
1
= C = 0.01µF/Socket (Min) or 0.1µF/Row, (Min)
2
= 0.01µF/Socket, 10%
= D = 1N4002 or Equivalent/Board
2
(V+) - (V-) = 30V
FN3931.1
6
August 17, 2005
HA-5101/883
Schematic
-IN
+IN
D
D
2
1
V+
R
R
R
Q
R
R
25
23
R
60
26
28
24
Q
Q
26
47
23
Q
Q
Q
28
24
Q
Q
16
25
Q
Q
Q
L2
L1
L41
R
R
34
35
Q
Q
14
15
Q
45
R
R
37
36
Q
43
8
R
15
Q
Q
37
36
Q
Q
Q
Q
1B
2A
2B
30
OUTPUT
Q
Q
Q
46
44
29
R
22
Q
38
Q
1A
Q
35
8
Q
R
41
13
17A
Q
Q
33
32
Q
42
Q
31
Q
Q
22
Q
21
17
Q
19B
R
20
C
1
Q
Q
Q
5
6
20
Q
10
Q
19A
Q
Q
7
Q
4
C
Q
2
Q
Q
3
11
27
Q
9
Q
12
R
Q
58
34
Q
Q
18
8
R
3A
3.65K
R
4A
Q
Q
49
50
3.65K
Q
Q
39
48
51
R
R
R
4B
18
V-
38
830
R
R
R
R
12
19A
R
27
11
10
830
R
19B
BAL
BAL
FN3931.1
August 17, 2005
7
HA-5101/883
Die Characteris tics
DIE DIMENSIONS
70 X 70 X 19 mils ±1mil
1790 x 1780 x 483µm ±25.4µm
METALLIZATION
Type: AI, 1% Cu
Thickness: 16kÅ ±2kÅ
GLASSIVATION
Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.)
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
WORST CASE CURRENT DENSITY:
5
2
1.38 x 10 A/cm
SUBSTRATE POTENTIAL (Powered Up): V-
TRANSISTOR COUNT: 54
PROCESS: Bipolar Dielectric Isolation
Metallization Mas k Layout
HA-5101/883
BAL
NC
-IN
V+
OUT
BAL
+IN
V-
FN3931.1
8
August 17, 2005
HA-5101/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES MILLIMETERS
MIN
-
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.405
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
10.29
7.87
NOTES
b1
A
b
-
M
M
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
(b)
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
Q
PLANE
A
2
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
C A - B
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
aaa
D
S
M
S
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be
located adjacent to pin one and shall be located within the
Q
0.015
0.005
0.38
0.13
6
shaded area shown. The manufacturer’s identification shall not
be used as a pin one identification mark.
S1
7
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
-
M applies to lead plating and finish thickness.
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
8
8
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
FN3931.1
9
August 17, 2005
HA-5101/883
Ceramic Leadles s Chip Carrier Packages (CLCC)
J20.A MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
0.010 S E H S
D
INCHES MILLIMETERS
D3
SYMBOL
A
MIN
MAX
0.100
0.088
-
MIN
1.52
1.27
-
MAX
2.54
2.23
-
NOTES
o
j x 45
0.060
0.050
-
6, 7
-
-
A1
B
B1
B2
B3
D
0.022
0.028
0.56
0.71
2, 4
-
0.072 REF
1.83 REF
E3
E
B
0.006
0.022
0.15
0.56
-
0.342
0.358
8.69
9.09
-
D1
D2
D3
E
0.200 BSC
0.100 BSC
5.08 BSC
2.54 BSC
-
-
o
h x 45
-
0.358
-
9.09
2
-
0.010 S E F S
A1
0.342
0.358
8.69
9.09
E1
E2
E3
e
0.200 BSC
0.100 BSC
0.358
0.050 BSC
0.015
5.08 BSC
2.54 BSC
9.09
1.27 BSC
0.38
1.02 REF
0.51 REF
-
A
-
2
-
PLANE 2
PLANE 1
-
-
-E-
e1
h
j
-
-
2
5
5
-
0.040 REF
0.020 REF
0.007 M E F S H S
L
0.045
0.055
0.055
0.095
0.015
1.14
1.14
1.91
0.08
1.40
1.40
2.41
0.38
L1
L2
L3
ND
NE
N
0.045
0.075
0.003
-
-
B1
e
L3
L
-H-
-
5
5
5
5
3
3
3
20
20
Rev. 0 5/18/94
-F-
NOTES:
B3
L1
E1
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
L2
E2
B2
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
D2
D1
e1
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The
maximum “A” dimension is package height before being solder
dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
FN3931.1
10
August 17, 2005
HA-5101
®
Data Sheet
August 17, 2005
FN3931.1
DESIGN INFORMATION
The information contained on the following pages has been developed through characterization by Intersil Semiconductor and is
for use as application and design information only. No guarantee is implied.
Typical Performance Curves Unless Otherwise Specified: V = ±15V, T = +25°C
S
A
8
7
1500
1000
6
5
VOLTAGE
CURRENT
4
3
2
500
0
1
0
10
100
1K
FREQUENCY (Hz)
10K
100K
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
FIGURE 1. NOISE SPECTRUM
FIGURE 2. OFFSET VOLTAGE vs TEMPERATURE
A
= 25,000, V = ±15V (12.89mV
RTO or 0.52µV RTI)
P-P
V
S
P-P
A
= 25,000, V = ±15V (0.09nV
RTI)
P-P
V
S
PEAK-TO-PEAK TOTAL NOISE 0.1Hz TO 1MHz
PEAK-TO-PEAK NOISE 0.1Hz TO 10Hz
11
HA-5101
Typical Performance Curves Unless Otherwise Specified: V = ±15V, T = +25°C (Continued)
S
A
20
250
200
150
100
50
0
-20
-40
-60
0
-55
-25
0
25
50
75
100
125
-55
-25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 3. INPUT OFFSET CURRENT vs TEMPERATURE
30
20
5
MAXIMUM
4
MINIMUM
10
0
3
TYPICAL
2
1
0
-10
-20
-30
0
50 100 150 200 250 300 350 400 450 500
TIME (s)
0
2
4
6
8
10
12
14
16
18
20
SUPPLY VOLTAGE (±V)
FIGURE 5. INPUT OFFSET WARMUP DRIFT vs TIME
(NORMALIZED TO ZERO FINAL VALUE)
(SIX REPRESENTATIVE UNITS)
FIGURE 6. SUPPLY CURRENT vs SUPPLY VOLTAGE
1.1
1.1
60
D
RISE TIME
50
1.0
1.0
0.9
0.8
B
SLEW RATE
40
C
0.9
0.8
0.7
30
20
10
0
A
V
V
OUT
IN
A
B
C
D
+15mV
-15mV
+15mV
-15mV
±15V
±15V
0V
0.7
0.6
R
= 2K, C = 50pF
L
L
0V
0.6
-60 -40 -20
0
20
40
60
80
100
120
140
160
0
20
40
60
80 100 120
TIME (s)
TEMPERATURE (°C)
FIGURE 7. SLEW RATE/RISE TIME vs TEMPERATURE
FIGURE 8. SHORT CIRCUIT CURRENT vs TIME
FN3931.1
12
August 17, 2005
HA-5101
Typical Performance Curves Unless Otherwise Specified: V = ±15V, T = +25°C (Continued)
S
A
10M
(140)
V
ERROR
1M
(120)
1mV
100K
(100)
2.65µs
10K
(80)
5
10
15
18
TIME (1.5µs/DIV)
SUPPLY VOLTAGE (±V)
FIGURE 9. DC OPEN-LOOP VOLTAGE GAIN vs SUPPLY
VOLTAGE
FIGURE 10. SETTLING WAVEFORM
6
3
40
30
20
10
0
A
= 100
-55°C
V
GAIN
0
125°C
A
= 10
= 1
V
-3
-6
GAIN
-9
A
0
V
-55°C
PHASE
-12
-45
-90
125°C
-10
-20
PHASE
-135
-180
-225
A
R
= 1V/V
V
L
R
= 2K, C = 50pF
= 2K, C = 50pF
L
L
L
10K
100K
1M
FREQUENCY (Hz)
10M
100M
10K
100K
1M
FREQUENCY (Hz)
10M
100M
FIGURE 11. CLOSED LOOP GAIN AND PHASE AT HIGH AND
LOW TEMPERATURES
FIGURE 12. CLOSED-LOOP VOLTAGE GAIN vs FREQUENCY
AT DIFFERENT CLOSED LOOP GAINS
FN3931.1
August 17, 2005
13
HA-5101
Typical Performance Curves Unless Otherwise Specified: V = ±15V, T = +25°C (Continued)
S
A
-40
-60
140
120
100
-PSRR/CMRR
+PSRR
80
60
40
GAIN
-80
0
45
90
20
0
-100
-120
PHASE
100
135
180
10
1K
10K
100K
1M
10M
100M
100
1K
10K
FREQUENCY (Hz)
100K
1M
FREQUENCY (Hz)
FIGURE 13. OPEN-LOOP GAIN/PHASE vs FREQUENCY
FIGURE 14. REJECTION RATIOS vs FREQUENCY
Rise Time and Overshoot
IN
Timescale = 20ns/Div.
V
= V = ±3V, A = +1, R = 2kΩ, C = 50pF
OUT V L L
IN
V
= V
= 0V to +200mV, A = +1, R = 2K, C = 50pF
OUT V L L
Timescale = 500ns/Div., Scale: Input = 5V/Div, Output = 2V/Div
FIGURE 15. SLEW RATE WAVEFORM
FIGURE 16. SMALL SIGNAL WAVEFORM
FN3931.1
14
August 17, 2005
HA-5101
Offs et Adjus tment
The following is the recommended V adjust configuration:
IO
Applications Information
Operation At ±5V Supply
+15V
The HA-5101 performs well at V = ±5V exhibiting typical
S
characteristics as listed below:
7
(NOTE)
6
3
2
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5mV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56nA
CC
+
V
I
IO
-
BIAS
5
1
R
A
(V = ±3V) . . . . . . . . . . . . . . . . . . 106kV/V
VOL
O
4
P
V
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7V
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13mA
OUT
(NOTE)
R
= 100kΩ
P
CMRR (∆V
= ±2.5V) . . . . . . . . . . . . . 90dB
= 0.5V). . . . . . . . . . . . . . . 90dB
CM
-15V
PSRR (∆V
CC
Unity Gain Bandwidth . . . . . . . . . . . . . . 10MHz
Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . 7V/µs
NOTE: Proper decoupling is always recommended, 0.1µF high quality
capacitor should be at or very near the device’s supply pins.
Input Protection
The HA-5101 has built-in back-to-back protection diodes
which will limit the differential input voltage to approximately
7V. If the HA-5101 will be used in conditions where that volt-
age may be exceeded, then current limiting resistors must
be used. No more than 25mA should be allowed to flow in
the HA-5101’s input.
Comparator Circuit
V+
R
LIM
2
7
-
6
∆V
IN
R
LIM
+
3
Output Saturation
When an op amp is overdriven, output devices can saturate
and sometimes take a long time to recover. Saturation can
be avoided (sometimes) by using circuits such as:
4
V-
(∆V MAX – 7V)
IN
----------------------------------------------
V+
Choose R
Such That:
≤ 2R
LIM
LIM
25mA
R
1
2
R
+
-
R
R
3
4
IN
V
SOURCE
V-
If saturation cannot be avoided the HA-5101 recovers from a
25% overdrive in about 6.5µs (see photo).
OUT
Top: Input
Bottom: Output, 5V/Div., 2µs/Div.
Output is overdriven negative and recovers in 6µs.
FN3931.1
August 17, 2005
15
HA-5101
TABLE 1. TYPICAL PERFORMANCE CHARACTERISTICS
Device Characterized At: V = ±15V, R = 2kΩ, C = 50pF, A = +1V/V, Unless Otherwise Specified
VCL
S
L
L
PARAMETER
Offset Voltage
TEST CONDITIONS
TEMP (°C)
+25
TYP
0.8
3
DESIGN LIMITS
Table 1
7
UNITS
mV
V
= 0V
CM
Offset Voltage Average Drift
Offset Current Average Drift
Input Bias Current
Versus Temperature
Versus Temperature
-55 to +125
-55 to +125
+25
µV/°C
pA/°C
nA
100
65
250
V
V
V
= 0V
= 0V
= 0V
Table 1
Table 1
Table 3
9
CM
CM
CM
Input Offset Current
+25
35
nA
Differential Input Resistance
Input Noise Voltage Density
+25
500
5.4
3.4
3.2
6
kΩ
f
= 10Hz
= 100Hz
= 1kHz
= 10Hz
= 100Hz
= 1kHz
+25
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
V/V
o
f
+25
5.5
o
f
+25
Table 3
20
o
Input Noise Current Density
Large Signal Voltage Gain
f
+25
o
f
+25
1.5
0.52
400K
1M
1M
10
5
o
f
+25
Table 3
Table 1
Table 1
Table 1
5.4
o
V
= ±10V
-55
OUT
+25
V/V
+125
V/V
Slew Rate
V
V
V
V
= ±3V
-55 to +125
-55 to +125
-55 to +125
-55 to +125
+25
V/µs
kHz
OUT
Full Power Bandwidth
Rise and Fall Times
Overshoot
= 10V, (Note 2)
159
50
85
PEAK
= ±200mV
= ±200mV
Table 2
35
ns
OUT
OUT
20
%
Settling Time
To 0.1% for 10V Step
To 0.01% for 10V Step
4.5
6
6
µs
+25
10
µs
Output Short Circuit Current
Output Resistance
t < 10s, V
= ±15V
+25
±35
110
4.3
±4
±50
mA
OUT
Open Loop
+25
Table 3
Table 1
±5
Ω
Supply Current
No Load
+25
mA
Minimum Supply Voltage
Functional Operation Only,
Other Parameters Will Vary
+25
V
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3931.1
16
August 17, 2005
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