HA-5102_04 [INTERSIL]
Dual and Quad, 8MHz, Low Noise Operational Amplifiers; 双路和四路，为8MHz ，低噪声运算放大器
| 型号： | HA-5102_04 |
| 厂家： | 
Intersil |
| 描述： | Dual and Quad, 8MHz, Low Noise Operational Amplifiers |
| 文件： | 总13页 (文件大小：524K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-5102, HA-5104
®
Data Sheet
October 26, 2004
FN2925.9
Dual and Quad, 8MHz, Low Noise
Operational Amplifiers
Features
• Low Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3nV/√Hz
• Bandwidth . . . . . . . . . . . . . . . . . . . 8MHz (Compensated)
• Slew Rate. . . . . . . . . . . . . . . . . . . . 3V/µs (Compensated)
• Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 0.5mV
• Available in Duals or Quads
Low noise and high performance are key words describing
HA-5102 and HA-5104. These general purpose amplifiers
offer an array of dynamic specifications including a 3V/µs
slew rate and 8MHz bandwidth. Complementing these
outstanding parameters is a very low noise specification of
4.3nV/√Hz at 1kHz.
Applications
Fabricated using the Intersil high frequency DI process,
these operational amplifiers also offer excellent input
specifications such as a 0.5mV offset voltage and 30nA
offset current. Complementing these specifications are
108dB open loop gain and 60dB channel separation.
Consuming a very modest amount of power (90mW/
package for duals and 150mW/package for quads),
HA-5102/04 also provide 15mA of output current.
• High Q, Active Filters
• Audio Amplifiers
• Instrumentation Amplifiers
• Integrators
• Signal Generators
• For Further Design Ideas, See Application Note AN554
Pinouts
This impressive combination of features make this series of
amplifiers ideally suited for designs ranging from audio
amplifiers and active filters to the most demanding signal
conditioning and instrumentation circuits.
HA-5102 (CERDIP)
TOP VIEW
OUT1
1
2
3
4
8
7
6
5
V+
OUT2
-IN2
-IN1
+IN1
V-
These operational amplifiers are available in dual or quad
form with industry standard pinouts allowing for immediate
interchangeability with most other dual and quad operational
amplifiers.
-
+
-
+
+IN2
HA-5104 (CERDIP)
HA-5102 Dual, Comp. HA-5104 Quad, Comp.
Refer to the /883 data sheet for military product.
TOP VIEW
OUT1
-IN1
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
-IN4
+IN4
V-
1
4
Ordering Information
-
-
+
+
+IN1
V+
TEMP. RANGE
PKG.
DWG. #
o
PART NUMBER
HA7-5102-2
( C)
PACKAGE
8 Ld CERDIP
14 Ld CERDIP
16 Ld SOIC
-55 to 125
-55 to 125
-40 to 85
F8.3A
+IN2
-IN2
OUT2
+IN3
-IN3
OUT3
+
-
+
-
HA1-5104-2
F14.3
M16.3
2
3
8
HA9P5104-9
HA5104 (SOIC)
TOP VIEW
OUT4
-IN4
+IN4
V-
OUT1
-IN1
+IN1
V+
16
1
2
3
4
5
6
7
8
1
4
15
14
13
12
11
10
9
-
-
+
+
+IN3
-IN3
OUT3
NC
+IN2
-IN2
OUT2
NC
+
-
+
-
2
3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HA-5102, HA-5104
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . 40V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Thermal Resistance (Typical, Note 2)
θ
( C/W)
θ
( C/W)
JA
JC
8 Lead CERDIP Package. . . . . . . . . . .
14 Lead CERDIP Package. . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
115
75
100
28
20
N/A
o
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
SUPPLY
Output Short Circuit Duration (Note 3). . . . . . . . . . . . . . . . Indefinite
Maximum Junction Temperature (Note 1, Hermetic Package) . .175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
Operating Conditions
o
o
Temperature Range
HA-510X-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
HA-5104-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
o
(SOIC - Lead Tips Only)
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
o
1. Maximum power dissipation, including output load, must be designed to maintain the maximum junction temperature below 175 C for hermetic
o
packages, and below 150 C for plastic packages.
2. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
3. Any one amplifier may be shorted to ground indefinitely.
Electrical Specifications
V
= ±15V, Unless Otherwise Specified
SUPPLY
HA-5102-2
HA-5104-2
TYP
HA-5104-9
TYP MAX UNITS
TEMP.
o
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage
( C)
MIN
TYP
MAX
MIN
MAX
MIN
25
Full
Full
25
-
0.5
2.0
2.5
-
-
0.5
2.5
3.0
-
-
0.5
2.5
3.0
-
mV
mV
-
-
3
-
-
3
-
-
3
o
Offset Voltage Average Drift
Bias Current
-
-
-
µV/ C
-
130
-
200
325
75
125
-
-
130
-
200
325
75
125
-
-
130
-
200
500
75
125
-
nA
nA
nA
nA
kΩ
V
Full
25
-
-
-
Offset Current
-
30
-
-
30
-
-
30
-
Full
25
-
-
-
-
-
-
Input Resistance
500
-
500
-
500
-
Common Mode Range
Full
±12
-
±12
-
±12
-
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain,
25
Full
Full
25
100
100
86
-
250
-
-
-
-
-
-
100
100
86
-
250
-
-
-
-
-
-
80
80
80
-
250
-
-
-
-
-
-
kV/V
kV/V
dB
(V
OUT
= ±5V, R = 2kΩ)
L
Common Mode Rejection Ratio (V
= ±5.0V)
95
8
95
8
95
8
CM
Small Signal Bandwidth, (A = 1)
V
MHz
dB
Channel Separation (Note 4)
OUTPUT CHARACTERISTICS
Output Voltage Swing
25
-
60
-
60
-
60
(R = 10kΩ)
Full
Full
Full
25
±12
±10
±10
16
±13
±12
±15
47
-
-
-
-
-
±12
±10
±10
16
±13
±12
±15
47
-
-
-
-
-
±12
±10
±7
16
-
±13
±12
±15
47
-
-
-
-
-
V
V
L
(R = 2kΩ)
L
Output Current, (V
OUT
= ±5V)
mA
kHz
Ω
Full Power Bandwidth (Note 5)
Output Resistance
STABILITY
25
-
110
-
110
110
Minimum Stable Closed Loop Gain
Full
1
-
-
1
-
-
1
-
-
V/V
TRANSIENT RESPONSE (Note 6)
FN2925.9
2
HA-5102, HA-5104
Electrical Specifications
V
= ±15V, Unless Otherwise Specified (Continued)
SUPPLY
HA-5102-2
HA-5104-2
HA-5104-9
TEMP.
( C)
o
PARAMETER
Rise Time
MIN
TYP
108
20
MAX
MIN
TYP
108
20
MAX
MIN
TYP
108
20
MAX UNITS
25
25
25
25
-
-
200
-
-
200
-
-
200
ns
%
Overshoot
35
-
35
-
35
-
Slew Rate
1
-
3
1
-
3
1
-
3
V/µs
µs
Settling Time (Note 7)
4.5
-
4.5
-
4.5
-
NOISE CHARACTERISTICS (Note 8)
Input Noise Voltage
Input Noise Current
f = 10Hz
25
25
25
25
25
-
-
-
-
-
9
25
6.0
15
3
-
-
-
-
-
9
25
6.0
15
3
-
-
-
-
-
9
25
6.0
15
3
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
f = 1kHz
4.3
4.3
4.3
f = 10Hz
5.1
5.1
5.1
f = 1kHz
0.57
870
0.57
870
0.57
870
Broadband Noise Voltage
f = DC to 30kHz
-
-
-
nV
RMS
POWER SUPPLY CHARACTERISTICS
Supply Current (All Amps)
25
-
3.0
5.0
-
-
5.0
6.5
-
-
5.0
6.5
-
mA
dB
Power Supply Rejection Ratio, (∆V = ±5V)
Full
86
100
86
100
80
100
S
NOTES:
4. Channel separation value is referred to the input of the amplifier. Input test conditions are: f = 10kHz; V = 100mV
IN
; R = 1kΩ.
PEAK
S
Slew Rate
5. Full power bandwidth is guaranteed by equation: Full power bandwidth = ---------------------------- .
2πV
PEAK
6. Refer to Test Circuits section of the data sheet.
7. Settling time is measured to 0.1% of final value for a 10V input step, A = -1.
V
8. The limits for these parameters are guaranteed based on lab characterization, and reflect lot-to-lot variation.
FN2925.9
3
HA-5102, HA-5104
Test Circuits and Waveforms
2kΩ
2kΩ
IN
+
-
IN
-
+
OUT
50pF
2kΩ
50pF
1kΩ
OUTPUT
+5V
INPUT
200mV
0V
INPUT
-5V
+5V
OUTPUT
0V
-5V
0V
Vertical = 40mV/Div., Horizontal = 50ns/Div. (A = +1)
V
Vertical = 5V/Div., Horizontal = 5µs/Div. (A = -1)
V
FIGURE 1. LARGE SIGNAL RESPONSE CIRCUIT
FIGURE 2. SMALL SIGNAL RESPONSE CIRCUIT
+15V
TO
2N4416
OSCILLOSCOPE
5kΩ
500Ω (NOTE 9)
5kΩ
2kΩ
+15V
+
V
OUT
-
V
IN
-15V
50pF
200Ω (NOTE 9)
2kΩ
2kΩ
NOTES:
9. A = -1.
V
10. Feedback and summing resistors should be 0.1% matched.
11. Clipping diodes are optional, HP5082-2810 recommended.
FIGURE 3. SETTLING TIME CIRCUIT
FN2925.9
4
HA-5102, HA-5104
Simplified Schematic
V+
OUTPUT
V-
+INPUT
-INPUT
Typical Performance Curves
15
10
o
o
V
= ±15V, T = 25 C
V
= ±15V, T = 25 C
A
S
A
S
5.0
HIGH
10
5
TYPICAL
LOW
1.0
0.5
0
0.1
10
100
FREQUENCY (Hz)
1K
10
100
1K
FREQUENCY (Hz)
FIGURE 4. INPUT NOISE VOLTAGE DENSITY
FIGURE 5. INPUT NOISE CURRENT DENSITY
FN2925.9
5
HA-5102, HA-5104
Typical Performance Curves (Continued)
o
o
V
= ±15V, T = 25 C, 50µV/Div., 1s/Div., A = 1000V/V
V
= ±15V, T = 25 C, 500µV/Div., 1s/Div., A = 1000V/V
S
A
V
S
A
V
Input Noise = 0.232µV
Total Output Noise = 2.075µV
FIGURE 7. 0.1Hz TO 1MHz NOISE
P-P
FIGURE 6. 0.1Hz TO 10Hz NOISE
P-P
2.0
2.0
1.5
1.0
0.5
0
o
V
S = ±15V
T
= 25 C
A
1.5
1.0
0.5
0
-60
-40
-20
0
20
40
60
o
80
100
120
0
2
4
6
8
10
12
14
16
18
TEMPERATURE ( C)
SUPPLY VOLTAGE (±V)
FIGURE 9. V vs V
FIGURE 8. V vs TEMPERATURE
IO
IO
S
4
2
0
100
90
V
= ±15V
V
= ±15V
S
S
-2
80
-4
-6
-8
-10
70
60
50
40
30
-12
-14
-16
-18
-20
20
10
0
-22
-24
-26
-60
-40
-20
0
20
40
60
80
100
120
-60
-40
-20
0
20
40
60
80
100 120
o
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 10. I vs TEMPERATURE
IO
FIGURE 11. I
vs TEMPERATURE
BIAS
FN2925.9
6
HA-5102, HA-5104
Typical Performance Curves (Continued)
5
4
5
4
o
V
= ±15V, I
OUT
= 0
T
= 25 C, I = 0
OUT
S
A
3
2
1
0
3
2
1
0
-60
-40
-20
0
20
40
60
80
100
120
0
2
4
6
8
10
12
14
16
18
o
TEMPERATURE ( C)
SUPPLY VOLTAGE (±V)
FIGURE 12. I
vs TEMPERATURE (HA-5104)
FIGURE 13. I
vs V (HA-5102)
CC S
CC
5
5.5
5.0
V
= ±15V, ∆V = ±10V, R = 2kΩ
O L
S
V
= ±10V, V = ±15V
O
S
o
125 C
4
o
25 C
3
2
1
0
4.0
3.0
o
-55 C
2.0
1K
-60
-40
-20
0
20
40
60
80
100 120
2K
4K
6K
8K 10K
o
TEMPERATURE ( C)
LOAD RESISTANCE (Ω)
FIGURE 14. A
vs TEMPERATURE
FIGURE 15. A
vs LOAD RESISTANCE
VOL
VOL
290
280
270
260
250
240
230
220
210
200
190
180
170
160
150
140
130
13
12
11
10
9
o
o
T
= 25 C, R = 2kΩ
T
= 25 C, R = 2kΩ
A
L
A
L
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
18
0
2
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (±V)
FIGURE 16. A
VOL
vs V
FIGURE 17. V vs V
OUT S
S
FN2925.9
7
HA-5102, HA-5104
Typical Performance Curves (Continued)
45
40
35
30
25
20
0
-20
-40
-60
-80
o
V
= ±15V, T = 25 C
A
S
V
= -15V
OUT
V
= +15V
OUT
-100
0
50
100 150
200
250 300 350
400 450
1K
10K
100K
1M
TIME (SECONDS)
FREQUENCY (Hz)
FIGURE 18. OUTPUT SHORT CIRCUIT CURRENT vs TIME
FIGURE 19. CMRR vs FREQUENCY
0
-20
-40
225
135
45
6
V
= ±15V, R = 2kΩ, C = 50pF
S
L
L
o
-55 C
GAIN
0
-3
-6
o
125 C
GAIN
0
+PSRR
-60
-45
-12
-18
o
125 C
-PSRR
PHASE
-80
o
-135
-225
-55 C
PHASE
-100
-24
10K
1K
10K
100K
1M
100K
1M
FREQUENCY (Hz)
10M
40M
FREQUENCY (Hz)
FIGURE 20. PSRR vs FREQUENCY
FIGURE 21. UNITY GAIN FREQUENCY RESPONSE
120
60
50
40
30
20
10
o
o
V
= ±15V, T = 25 C, R = 2kΩ
V
R
= ±15V, T = 25 C,
S
A
L
S
A
100
80
60
40
20
0
= 2kΩ, C = 50pF
L
L
GAIN
0
45
90
135
180
PHASE
10K
0
10
100
1K
10K
100
1K
100K
1M
10M
100M
LOAD CAPACITANCE (pF)
FREQUENCY (Hz)
FIGURE 22. OPEN LOOP GAIN vs FREQUENCY
FIGURE 23. SMALL SIGNAL OVERSHOOT vs C
LOAD
FN2925.9
8
HA-5102, HA-5104
Typical Performance Curves (Continued)
1.1
1.1
1.0
0.9
0.8
0.7
0.6
R
= 2kΩ, C = 50pF, V = ±15V
L
L
S
R
= 2kΩ, C = 50pF, V = ±15V
L
L
S
1.0
0.9
0.8
0.7
0.6
-60
-40
-20
0
20
40
60
80
100
120
-60
-40
-20
0
20
40
60
80
100 120
o
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 25. RISE TIME vs TEMPERATURE
FIGURE 24. SLEW RATE vs TEMPERATURE
PASSIVATION:
Type: Nitride (Si N ) over Silox (SiO , 5% Phos.)
Die Characteristics
3
4
2
DIE DIMENSIONS:
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
98.4 mils x 67.3 mils x 19 mils
2500µm x 1710µm x 483µm
SUBSTRATE POTENTIAL (POWERED UP):
METALLIZATION:
Unbiased
Type: Al, 1% Cu
TRANSISTOR COUNT:
Thickness: 16kÅ ±2kÅ
93
PROCESS:
Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5102
V-
+IN1
-IN1
OUT1
+IN2
-IN2
OUT2
V+
FN2925.9
9
HA-5102, HA-5104
SUBSTRATE POTENTIAL (POWERED UP):
Die Characteristics
Unbiased
DIE DIMENSIONS:
TRANSISTOR COUNT:
95 mils x 99 mils x 19 mils
2420µm x 2530µm x 483µm
175
METALLIZATION:
PROCESS:
Type: Al, 1% Cu
Bipolar Dielectric Isolation
Thickness: 16kÅ ±2kÅ
PASSIVATION:
Type: Nitride (Si N ) over Silox (SiO , 5% Phos.)
3
4
2
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
Metallization Mask Layout
HA-5104
V+
+IN2
+IN1
-IN1
-IN2
OUT1
OUT4
OUT2
OUT3
-IN3
-IN4
+IN3
V-
+IN4
FN2925.9
10
HA-5102, HA-5104
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES MILLIMETERS
MIN
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.405
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
10.29
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C
D
A - B
D
S
S
S
-
4
BASE
PLANE
Q
A
2
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
E
0.220
5.59
5
e
S
b
eA/2
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
C
A - B
D
aaa
C
A - B
D
S
M
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
8
8
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
FN2925.9
11
HA-5102, HA-5104
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES MILLIMETERS
MIN
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C
D
A - B
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
E
0.220
5.59
5
e
S
b
eA/2
aaa M
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
C
A - B
D
C
A - B S D S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
14
14
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
FN2925.9
12
HA-5102, HA-5104
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
10.50
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.3977
0.2914
-
-A-
o
0.4133 10.10
3
h x 45
D
0.2992
7.40
4
-C-
0.050 BSC
1.27 BSC
-
α
µ
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C A M B S
N
α
16
16
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN2925.9
13
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