EL5221CW-T7 [INTERSIL]
Dual 12MHz Rail-to-Rail Input-Output Buffer; 双12MHz的轨至轨输入，输出缓冲器
| 型号： | EL5221CW-T7 |
| 厂家： | 
Intersil |
| 描述： | Dual 12MHz Rail-to-Rail Input-Output Buffer |
| 文件： | 总11页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5221
®
Data Sheet
Augus t 2, 2005
FN7187.1
Dual 12MHz Rail-to-Rail Input-Output
Buffer
Features
• 12MHz -3dB bandwidth
• Unity gain buffer
The EL5221 is a dual, low power, high voltage rail-to-rail
input-output buffer. Operating on supplies ranging from 5V to
15V, while consuming only 500µA per channel, the EL5221
has a bandwidth of 12MHz -(-3dB). The EL5221 also
provides rail-to-rail input and output ability, giving the
maximum dynamic range at any supply voltage.
• Supply voltage = 4.5V to 16.5V
• Low supply current (per buffer) = 500µA
• High slew rate = 10V/µs
• Rail-to-rail operation
The EL5221 also features fast slewing and settling times, as
well as a high output drive capability of 30mA (sink and
source). These features make the EL5221 ideal for use as
voltage reference buffers in Thin Film Transistor Liquid
Crystal Displays (TFT-LCD). Other applications include
battery power, portable devices, and anywhere low power
consumption is important.
• Pb-Free plus anneal available (RoHS compliant)
Applications
• TFT-LCD drive circuits
• Electronics notebooks
• Electronics games
The EL5221 is available in space-saving 6-pin SOT-23 and
8-pin MSOP packages and operates over a temperature
range of -40°C to +85°C.
• Personal communication devices
• Personal Digital Assistants (PDA)
• Portable instrumentation
• Wireless LANs
Ordering Information
TAPE &
PART NUMBER
EL5221CW-T7
EL5221CW-T7A
PACKAGE
REEL
PKG. DWG. #
MDP0038
• Office automation
6-Pin SOT-23* 7” (3K pcs)
6-Pin SOT-23* 7” (250 pcs)
• Active filters
MDP0038
• ADC/DAC buffer
EL5221CWZ-T7
(See Note)
6-Pin SOT-23* 7” (3K pcs)
(Pb-free)
MDP0038
Pinouts
EL5221CWZ-T7A 6-Pin SOT-23* 7” (250 pcs)
MDP0038
EL5221
(6-PIN SOT-23)
TOP VIEW
(See Note)
(Pb-free)
EL5221CY
8-Pin MSOP
8-Pin MSOP
8-Pin MSOP
-
7”
13”
-
MDP0043
MDP0043
MDP0043
MDP0043
EL5221CY-T7
EL5221CY-T13
VINA
VS-
1
2
3
6
5
4
VOUTA
VS+
EL5221CYZ
(See Note)
8-Pin MSOP
(Pb-free)
VINB
VOUTB
EL5221CYZ-T7
(See Note)
8-Pin MSOP
(Pb-free)
7”
MDP0043
MDP0043
EL5221
(8-PIN MSOP)
TOP VIEW
EL5221CYZ-T13
(See Note)
8-Pin MSOP
(Pb-free)
13”
*EL5221CW symbol is .Mxxx where xxx represents date code.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
VOUTA
NC
1
2
3
4
8
VS+
7
6
5
VOUTB
NC
VINA
VS-
VINB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5221
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . .+18V
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
ESD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
S
S
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V - - 0.5V, V + +0.5V
S
S
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, R = 10kΩ and C = 10pF to 0V, T = 25°C unless otherwise specified.
S
S
L
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Impedance
V
= 0V
2
5
12
mV
µV/°C
nA
OS
CM
(Note 1)
= 0V
TCV
OS
I
V
2
50
B
CM
R
C
1
GΩ
IN
IN
V
Input Capacitance
Voltage Gain
1.35
pF
A
-4.5V ≤ V
≤ 4.5V
0.995
4.85
60
1.005
-4.85
V/V
OUT
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short Circuit Current
I = -5mA
-4.92
4.92
V
V
OL
L
I = 5mA
L
OH
I
Short to GND
±120
mA
SC
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current (Per Buffer)
DYNAMIC PERFORMANCE
SR Slew Rate (Note 2)
V
is moved from ±2.25V to ±7.75V
80
dB
µA
S
I
No load
500
750
S
-4.0V ≤ V
≤ 4.0V, 20% to 80%
7
10
500
12
V/µs
ns
OUT
t
Settling to +0.1%
-3dB Bandwidth
V = 2V step
O
S
BW
R
= 10kΩ, C = 10pF
MHz
dB
L
L
CS
Channel Separation
f = 5MHz
75
NOTES:
1. Measured over the operating temperature range
2. Slew rate is measured on rising and falling edges
2
EL5221
Electrical Specifications V + = +5V, V - = 0V, R = 10kΩ and C = 10pF to 2.5V, T = 25°C unless otherwise specified.
S
S
L
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Impedance
V
= 2.5V
2
5
10
mV
µV/°C
nA
OS
CM
(Note 1)
= 2.5V
TCV
OS
I
V
2
50
B
CM
R
1
GΩ
IN
IN
V
C
Input Capacitance
Voltage Gain
1.35
pF
A
0.5 ≤ V
≤ 4.5V
0.995
4.85
60
1.005
150
V/V
OUT
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short Circuit Current
I = -5mA
80
mV
V
OL
L
I = 5mA
4.92
±120
OH
L
I
Short to GND
mA
SC
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current (Per Buffer)
DYNAMIC PERFORMANCE
SR Slew Rate (Note 2)
V
is moved from 4.5V to 15.5V
80
dB
µA
S
I
No Load
500
750
S
1V ≤ V
≤4V, 20% to 80%
7
10
500
12
V/µs
ns
OUT
V = 2V Step
O
t
Settling to +0.1%
-3dB Bandwidth
S
BW
R = 10kΩ, C = 10pF
MHz
dB
L
L
CS
Channel Separation
f = 5MHz
75
NOTES:
1. Measured over the operating temperature range
2. Slew rate is measured on rising and falling edges
3
EL5221
Electrical Specifications V + = +15V, V - = 0V, R = 10kΩ and C = 10pF to 7.5V, T = 25°C unless otherwise specified.
S
S
L
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Impedance
V
= 7.5V
CM
2
5
14
mV
µV/°C
nA
OS
TCV
(Note 1)
= 7.5V
OS
I
V
2
50
B
CM
R
1
GΩ
IN
IN
V
C
Input Capacitance
Voltage Gain
1.35
pF
A
0.5 ≤ V
OUT
≤ 14.5V
0.995
14.85
60
1.005
150
V/V
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short Circuit Current
I = -5mA
80
mV
V
OL
L
I = 5mA
14.92
±120
OH
L
I
Short to GND
mA
SC
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current (Per Buffer)
DYNAMIC PERFORMANCE
SR Slew Rate (Note 2)
V
is moved from 4.5V to 15.5V
80
dB
µA
S
I
No Load
500
750
S
1V ≤ V
≤14V, 20% to 80%
V = 2V Step
O
7
10
500
12
V/µs
ns
OUT
t
Settling to +0.1%
-3dB Bandwidth
S
BW
R
= 10kΩ, C = 10pF
MHz
dB
L
L
CS
Channel Separation
f = 5MHz
75
NOTES:
1. Measured over the operating temperature range
2. Slew rate is measured on rising and falling edges
4
EL5221
Typical Performance Curves
Input Offset Voltage Distribution
2000
Input Offset Voltage Drift
35
30
25
20
15
10
5
V
T
=±5V
=25°C
V
T
=±5V
S
=25°C
Typical
Production
Distribution
Typical
Production
Distribution
S
A
A
1600
1200
800
400
0
0
Input Offset Voltage (mV)
Input Offset Voltage, TCVOS (µV/°C)
Input Offset Voltage vs Temperature
Input Bias Current vs Temperature
10
5
4
2
V
=±5V
V =±5V
S
S
0
0
-2
-4
-5
-10
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
Output Low Voltage vs Temperature
Output High Voltage vs Temperature
-4.91
-4.92
-4.93
-4.94
-4.95
-4.96
-4.97
4.97
4.96
4.95
4.94
4.93
V
I
=±5V
V
I
=±5V
S
S
=5mA
=-5mA
OUT
OUT
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
5
EL5221
Typical Performance Curves (Continued)
Slew Rate vs Temperature
Voltage Gain vs Temperature
1.001
13
12.5
12
V
=±5V
S
1.0005
V
=±5V
S
1.0000
0.9995
0.999
11.5
11
10.5
10
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
Supply Current per Channel vs Temperature
Supply Current per Channel vs Supply Voltage
0.55
0.5
650
550
450
350
250
V
=±5V
S
T
=25°C
A
0.45
0.4
-50
0
50
100
150
0
5
10
Supply Voltage (V)
15
20
Temperature (°C)
Frequency Response for Various C
Frequency Response for Various R
L
L
5
0
20
10
R =10kΩ
L
10kΩ
1kΩ
V
=±5V
S
12pF
50pF
0
560Ω
150Ω
C =10pF
L
S
-5
V
=±5V
-10
-20
-30
100pF
-10
1000pF
-15
1M
Frequency (Hz)
100M
100k
10M
1M
Frequency (Hz)
100M
100k
10M
6
EL5221
Typical Performance Curves (Continued)
Output Impedance vs Frequency
200
Maximum Output Swing vs Frequency
12
10
8
V
=±5V
S
A
160
120
80
T
=25°C
V
T
=±5V
=25°C
S
A
6
R =10kΩ
C =12pF
L
L
4
Distortion <1%
40
2
0
0
10k
100k
1M
10M
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
PSRR vs Frequency
Input Voltage Noise Spectral Density vs Frequency
80
60
40
20
0
600
100
PSRR+
PSRR-
10
V
=±5V
S
A
T
=25°C
1
1k
10k
Frequency (Hz)
100
1k
10k
100k
1M
10M
100M
100k
1M
100
10M
Frequency (Hz)
Total Harmonic Distortion + Noise vs Frequency
Channel Separation vs Frequency Response
0.010
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
-60
Dual measured Channel A to B
Quad measured Channel A to D or B to C
Other combinations yield improved
-80 rejection.
V
=±5V
S
R =10kΩ
V
L
=220mV
IN
RMS
-100
-120
-140
V
=±5V
S
L
R =10kΩ
V
=1V
IN
RMS
1k
10k
100k
1M
6M
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
7
EL5221
Typical Performance Curves (Continued)
Small-Signal Overshoot vs Load Capacitance
100
Settling Time vs Step Size
5
4
V
=±5V
S
L
L
V
=±5V
S
R =10kΩ
C =12pF
T
80
60
40
20
0
3
R =10kΩ
L
IN
0.1%
0.1%
V
T
=±50mV
=25°C
2
A
=25°C
A
1
0
-1
-2
-3
-4
-5
10
100
1000
0
200
400
600
800
Load Capacitance (pF)
Settling Time (nS)
Large Signal Transient Response
Small Signal Transient Response
50mV
200ns
1V
1µS
V
T
=±5V
=25°C
S
A
L
R =10kΩ
C =12pF
L
V
T
=±5V
=25°C
S
A
R =10kΩ
C =12pF
L
L
8
EL5221
Pin Des criptions
SOT23-6
MSOP-8
PIN NAME
FUNCTION
Buffer A Input
EQUIVALENT CIRCUIT
1
3
VINA
V
+
S
V
-
S
Circuit 1
2
3
4
4
5
7
VS-
VINB
Negative Supply Voltage
Buffer B Input
(Reference Circuit 1)
VOUTB
Buffer B Output
V
V
+
S
-
S
GND
Circuit 2
5
6
8
1
VS+
Positive Supply Voltage
Buffer A Output
VOUTA
(Reference Circuit 2)
input is a 10V
approximately 9.985V
sinusoid. The output voltage is
Applications Information
P-P
.
P-P
Product Des cription
The EL5221 unity gain buffer is fabricated using a high
voltage CMOS process. It exhibits rail-to-rail input and
output capability and has low power consumption (500µA
per buffer). These features make the EL5221 ideal for a wide
range of general-purpose applications. When driving a load
of 10kΩ and 12pF, the EL5221 has a -3dB bandwidth of
12MHz and exhibits 10V/µs slew rate.
5V
10µS
V
T
=±5V
=25°C
=10V
S
A
V
IN P-P
Operating Voltage, Input, and Output
5V
The EL5221 is specified with a single nominal supply voltage
from 5V to 15V or a split supply with its total range from 5V
to 15V. Correct operation is guaranteed for a supply range of
4.5V to 16.5V. Most EL5221 specifications are stable over
both the full supply range and operating temperatures of
-40°C to +85°C. Parameter variations with operating voltage
and/or temperature are shown in the typical performance
curves.
FIGURE 1. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
Short Circuit Current Limit
The EL5221 will limit the short circuit current to ±120mA if
the output is directly shorted to the positive or the negative
supply. If an output is shorted indefinitely, the power
dissipation could easily increase such that the device may
be damaged. Maximum reliability is maintained if the output
continuous current never exceeds ±30mA. This limit is set by
the design of the internal metal interconnects.
The output swings of the EL5221 typically extend to within
80mV of positive and negative supply rails with load currents
of 5mA. Decreasing load currents will extend the output
voltage range even closer to the supply rails. Figure 1 shows
the input and output waveforms for the device. Operation is
from ±5V supply with a 10kΩ load connected to GND. The
Output Phas e Revers al
The EL5221 is immune to phase reversal as long as the
input voltage is limited from V - -0.5V to V + +0.5V. Figure
S
S
2 shows a photo of the output of the device with the input
9
EL5221
voltage driven beyond the supply rails. Although the device's
output will not change phase, the input's overvoltage should
be avoided. If an input voltage exceeds supply voltage by
more than 0.6V, electrostatic protection diodes placed in the
input stage of the device begin to conduct and overvoltage
damage could occur.
where:
i = 1 to 2 for dual buffer
V = Total supply voltage
S
I
= Maximum supply current per channel
SMAX
V
i = Maximum output voltage of the application
OUT
1V
10µS
I
i = Load current
LOAD
If we set the two P
can solve for R
LOAD
equations equal to each other, we
i to avoid device overheat. Figure 3 and
DMAX
Figure 4 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
V
T
V
=±2.5V
=25°C
S
A
=6V
IN
P-P
1V
simple matter to see if P
exceeds the device's power
DMAX
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves shown in
Figure 3 and Figure 4.
FIGURE 2. OPERATION WITH BEYOND-THE-RAILS INPUT
Power Dis s ipation
Package Mounted on a JEDEC JESD51-7 High
Effective Thermal Conductivity Test Board
With the high-output drive capability of the EL5221 buffer, it
is possible to exceed the 125°C 'absolute-maximum junction
temperature' under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if load
conditions need to be modified for the buffer to remain in the
safe operating area.
1
870mW
MAX T =125°C
J
0.8
0.6
0.4
0.2
0
435mW
The maximum power dissipation allowed in a package is
determined according to:
T
- T
AMAX
JMAX
0
25
50
75 85 100
125
150
P
= --------------------------------------------
DMAX
Θ
Ambient Temperature (°C)
JA
where:
FIGURE 3. PACKAGE POWER DISSIPATION VS AMBIENT
TEMPERATURE
T
T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMAX
Package Mounted on a JEDEC JESD51-3 Low
Effective Thermal Conductivity Test Board
0.6
Θ
= Thermal resistance of the Package
= Maximum power dissipation in the package
JA
P
MAX T =125°C
DMAX
J
486mW
0.5
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
391mW
0.4
0.3
0.2
0.1
0
P
= Σi[V × I
+ (V + - V
i) × I
i]
LOAD
DMAX
S
SMAX
S
OUT
when sourcing, and:
0
25
50
75 85 100
125
150
Ambient Temperature (°C)
P
= Σi[V × I
+ (V
i - V -) × I
i]
LOAD
DMAX
S
SMAX
OUT
S
FIGURE 4. PACKAGE POWER DISSIPATION VS AMBIENT
TEMPERATURE
when sinking.
10
EL5221
Unus ed Buffers
It is recommended that any unused buffer have the input tied
to the ground plane.
Driving Capacitive Loads
The EL5221 can drive a wide range of capacitive loads. As
load capacitance increases, however, the -3dB bandwidth of
the device will decrease and the peaking increase. The
buffers drive 10pF loads in parallel with 10kΩ with just 1.5dB
of peaking, and 100pF with 6.4dB of peaking. If less peaking
is desired in these applications, a small series resistor
(usually between 5Ω and 50Ω) can be placed in series with
the output. However, this will obviously reduce the gain
slightly. Another method of reducing peaking is to add a
"snubber" circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values of
150Ω and 10nF are typical. The advantage of a snubber is
that it does not draw any DC load current or reduce the gain
Power Supply Bypas s ing and Printed Circuit
Board Layout
The EL5221 can provide gain at high frequency. As with any
high frequency device, good printed circuit board layout is
necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be
as short as possible, and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the V - pin is connected to ground,
S
a 0.1µF ceramic capacitor should be placed from V + to pin
S
to V - pin. A 4.7µF tantalum capacitor should then be
S
connected in parallel, placed in the region of the buffer. One
4.7µF capacitor may be used for multiple devices. This same
capacitor combination should be placed at each supply pin
to ground if split supplies are to be used.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
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