EL5221CY-T7 [ELANTEC]
Dual 12MHz Rail-to-Rail Input-Output Buffer; 双12MHz的轨至轨输入，输出缓冲器
| 型号： | EL5221CY-T7 |
| 厂家： | 
ELANTEC SEMICONDUCTOR |
| 描述： | Dual 12MHz Rail-to-Rail Input-Output Buffer |
| 文件： | 总13页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Features
General Description
• 12MHz -3dB bandwidth
• Unity gain buffer
• Supply voltage = 4.5V to 16.5V
• Low supply current (per buffer) =
500µA
The EL5221C is a dual, low power, high voltage rail-to-rail input-out-
put buffer. Operating on supplies ranging from 5V to 15V, while
consuming only 500µA per channel, the EL5221C has a bandwidth of
12MHz (-3dB). The EL5221C also provides rail-to-rail input and out-
put ability, giving the maximum dynamic range at any supply voltage.
• High slew rate = 10V/µs
• Rail-to-rail operation
The EL5221C also features fast slewing and settling times, as well as
a high output drive capability of 30mA (sink and source). These fea-
tures make the EL5221C ideal for use as voltage reference buffers in
Thin Film Transistor Liquid Crystal Displays (TFT-LCD). Other
applications include battery power, portable devices, and anywhere
low power consumption is important.
Applications
• TFT-LCD drive circuits
• Electronics notebooks
• Electronics games
The EL5221C is available in space-saving SOT23-6 and MSOP-8
packages and operates over a temperature range of -40°C to +85°C.
• Personal communication devices
• Personal Digital Assistants (PDA)
• Portable instrumentation
• Wireless LANs
• Office automation
• Active filters
• ADC/DAC buffer
Connection Diagrams
Ordering Information
Part No.
Package
SOT23-6
SOT23-6
MSOP-8
MSOP-8
Tape & Reel
Outline #
MDP0038
MDP0038
MDP0043
MDP0043
EL5221CW-T7
EL5221CW-T13
EL5221CY-T7
EL5221CY-T13
7”
13”
7”
VINA
VS-
1
2
3
6
5
4
VOUTA
VS+
13”
VINB
VOUTB
SOT23-6
VOUTA
NC
1
2
3
4
8
7
6
5
VS+
VOUTB
NC
VINA
VS-
VINB
MSOP-8
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
© 2000 Elantec Semiconductor, Inc.
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Absolute Maximum Ratings (T = 25°C)
A
Values beyond absolute maximum ratings can cause the device to be pre-
maturely damaged. Absolute maximum ratings are stress ratings only and
functional device operation is not implied
Maximum Die Temperature
Storage Temperature
Operating Temperature
Power Dissipation
+125°C
-65°C to +150°C
-40°C to +85°C
See Curves
Supply Voltage between VS+ and VS-
Input Voltage
+18V
VS- - 0.5V, VS+ +0.5V
30mA
ESD Voltage
2kV
Maximum Continuous Output Current
Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the
specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Characteristics
VS+ = +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = 25°C unless otherwise specified.
Parameter
Description
Condition
Min
Typ
Max
12
Unit
Input Characteristics
VOS
TCVOS
IB
Input Offset Voltage
VCM = 0V
[1]
2
5
mV
µV/°C
nA
Average Offset Voltage Drift
Input Bias Current
Input Impedance
VCM = 0V
2
50
RIN
CIN
AV
1
GΩ
Input Capacitance
Voltage Gain
1.35
pF
-4.5V ≤ VOUT ≤ 4.5V
0.995
4.85
60
1.005
-4.85
V/V
Output Characteristics
VOL
VOH
ISC
Output Swing Low
IL = -5mA
IL = 5mA
-4.92
4.92
120
V
V
Output Swing High
Short Circuit Current
Short to GND
mA
Power Supply Performance
PSRR
IS
Power Supply Rejection Ratio
Supply Current (Per Buffer)
V
S is moved from 2.25V to 7.75V
80
dB
No Load
500
750
µA
Dynamic Performance
SR
tS
Slew Rate [2]
-4.0V ≤ VOUT ≤ 4.0V, 20% to 80%
VO=2V Step
7
10
500
12
V/µs
ns
Settling to +0.1%
-3dB Bandwidth
Channel Separation
BW
CS
RL = 10kΩ, CL = 10pF
f = 5MHz
MHz
dB
75
1. Measured over the operating temperature range
2. Slew rate is measured on rising and falling edges
2
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Electrical Characteristics
VS+ = +5V, VS- = 0V, RL = 10kΩ and CL = 10pF to 2.5V, TA = 25°C unless otherwise specified.
Parameter
Description
Condition
Min
Typ
Max
10
Unit
Input Characteristics
VOS
TCVOS
IB
Input Offset Voltage
VCM = 2.5V
[1]
2
5
mV
µV/°C
nA
Average Offset Voltage Drift
Input Bias Current
Input Impedance
VCM = 2.5V
2
50
RIN
CIN
AV
1
GΩ
Input Capacitance
Voltage Gain
1.35
pF
0.5 ≤ VOUT ≤ 4.5V
0.995
4.85
60
1.005
150
V/V
Output Characteristics
VOL
VOH
ISC
Output Swing Low
IL = -5mA
IL = 5mA
80
mV
V
Output Swing High
Short Circuit Current
4.92
120
Short to GND
mA
Power Supply Performance
PSRR
IS
Power Supply Rejection Ratio
Supply Current (Per Buffer)
V
S is moved from 4.5V to 15.5V
80
dB
No Load
500
750
µA
Dynamic Performance
SR
tS
Slew Rate [2]
1V ≤ VOUT ≤4V, 20% to 80%
7
10
500
12
V/µs
ns
Settling to +0.1%
-3dB Bandwidth
Channel Separation
VO = 2V Step
BW
CS
R
L = 10 kΩ, CL = 10pF
MHz
dB
f = 5MHz
75
1. Measured over the operating temperature range
2. Slew rate is measured on rising and falling edges
3
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Electrical Characteristics
VS+ = +15V, VS- = 0V, RL = 10kΩ and CL = 10pF to 7.5V, TA = 25°C unless otherwise specified.
Parameter
Description
Condition
Min
Typ
Max
14
Unit
Input Characteristics
VOS
TCVOS
IB
Input Offset Voltage
VCM = 7.5V
[1]
2
5
mV
µV/°C
nA
Average Offset Voltage Drift
Input Bias Current
Input Impedance
VCM = 7.5V
2
50
RIN
CIN
AV
1
GΩ
Input Capacitance
Voltage Gain
1.35
pF
0.5 ≤ VOUT ≤ 14.5V
0.995
14.85
60
1.005
150
V/V
Output Characteristics
VOL
VOH
ISC
Output Swing Low
IL = -5mA
IL = 5mA
80
mV
V
Output Swing High
Short Circuit Current
14.92
120
Short to GND
mA
Power Supply Performance
PSRR
IS
Power Supply Rejection Ratio
Supply Current (Per Buffer)
V
S is moved from 4.5V to 15.5V
80
dB
No Load
500
750
µA
Dynamic Performance
SR
tS
Slew Rate [2]
1V ≤ VOUT ≤14V, 20% to 80%
7
10
500
12
V/µs
ns
Settling to +0.1%
-3dB Bandwidth
Channel Separation
VO = 2V Step
BW
CS
R
L = 10 kΩ, CL = 10pF
MHz
dB
f = 5MHz
75
1. Measured over the operating temperature range
2. Slew rate is measured on rising and falling edges
4
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Typical Performance Curves
Input Offset Voltage Distribution
Input Offset Voltage Drift
35
2000
V =±5V
T =25°C
A
V =±5V
S
T =25°C
A
S
Typical
Production
Distribution
Typical
Production
Distribution
30
25
20
15
10
5
1600
1200
800
400
0
0
Input Offset Voltage (mV)
Input Offset Voltage, TCVOS (µV/°C)
Input Offset Voltage vs Temperature
Input Bias Current vs Temperature
10
5
4
2
V =±5V
S
V =±5V
S
0
0
-2
-4
-5
-10
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
Output Low Voltage vs Temperature
Output High Voltage vs Temperature
-4.91
-4.92
-4.93
-4.94
-4.95
-4.96
-4.97
4.97
4.96
4.95
4.94
4.93
V =±5V
S
I
=-5mA
OUT
V =±5V
S
I
=5mA
OUT
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
5
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Typical Performance Curves
Slew Rate vs Temperature
Voltage Gain vs Temperature
1.001
13
12.5
12
V =±5V
S
1.0005
1.0000
0.9995
0.999
V =±5V
S
11.5
11
10.5
10
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
Supply Current per Channel vs Temperature
Supply Current per Channel vs Supply Voltage
0.55
0.5
650
550
450
350
250
V =±5V
S
T =25°C
A
0.45
0.4
-50
0
50
100
150
0
5
10
15
20
Temperature (°C)
Supply Voltage (V)
Frequency Response for Various C
Frequency Response for Various R
L
L
5
0
20
10
R =10kΩ
S
L
10kΩ
1kΩ
V =±5V
12pF
50pF
0
560Ω
150Ω
C =10pF
L
V =±5V
S
-5
-10
-20
-30
100pF
-10
1000pF
-15
100k
1M
10M
100M
1M
100M
100k
10M
Frequency (Hz)
Frequency (Hz)
6
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Typical Performance Curves
Output Impedance vs Frequency
Maximum Output Swing vs Frequency
200
12
V =±5V
T =25°C
A
S
10
8
160
120
80
V =±5V
S
T =25°C
A
6
4
2
0
R =10kΩ
L
C =12pF
L
Distortion <1%
40
0
10k
100k
1M
10M
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
PSRR vs Frequency
Input Voltage Noise Spectral Density vs Frequency
80
60
40
20
0
600
100
PSRR+
PSRR-
10
V =±5V
S
T =25°C
A
1
1k
10k
100
1k
10k
100k
1M
10M
100M
100k
1M
100
10M
Frequency (Hz)
Frequency (Hz)
Total Harmonic Distortion + Noise vs Frequency
Channel Separation vs Frequency Response
0.010
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
-60
-80
Dual measured Channel A to B
Quad measured Channel A to D or B to C
Other combinations yield improved rejection.
V =±5V
S
R =10kΩ
IN
L
V =220mV
RMS
-100
-120
-140
V =±5V
S
R =10kΩ
L
V =1V
IN
RMS
1k
10k
100k
1M
6M
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
7
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Typical Performance Curves
Small-Signal Overshoot vs Load Capacitance
Settling Time vs Step Size
100
5
4
V =±5V
S
V =±5V
S
R =10kΩ
L
80
60
40
20
0
3
R =10kΩ
L
C =12pF
T =25°C
A
L
0.1%
0.1%
V =±50mV
IN
2
T =25°C
A
1
0
-1
-2
-3
-4
-5
10
100
1000
0
200
400
600
800
Load Capacitance (pF)
Settling Time (nS)
Large Signal Transient Response
Small Signal Transient Response
50mV
200ns
1V
1µS
V =±5V
S
T =25°C
A
R =10kΩ
L
C =12pF
L
V =±5V
S
T =25°C
A
R =10kΩ
L
C =12pF
L
8
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Pin Descriptions
Pin
Name
SOT23-6 MSOP-8
Function
Buffer A Input
Equivalent Circuit
1
3
VINA
V
S+
V
S-
Circuit 1
2
3
4
4
5
7
VS-
VINB
Negative Supply Voltage
Buffer B Input
(Reference Circuit 1)
VOUTB
Buffer B Output
V
S+
V
S-
GND
Circuit 2
5
6
8
1
VS+
Positive Supply Voltage
Buffer A Output
VOUTA
(Reference Circuit 2)
9
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Applications Information
Product Description
Short Circuit Current Limit
The EL5221C unity gain buffer is fabricated using a
high voltage CMOS process. It exhibits rail-to-rail input
and output capability and has low power consumption
(500µA per buffer). These features make the EL5221C
ideal for a wide range of general-purpose applications.
When driving a load of 10kΩ and 12pF, the EL5221C
has a -3dB bandwidth of 12MHz and exhibits 10V/µS
slew rate.
The EL5221C will limit the short circuit current to
120mA if the output is directly shorted to the positive
or the negative supply. If an output is shorted indefi-
nitely, the power dissipation could easily increase such
that the device may be damaged. Maximum reliability is
maintained if the output continuous current never
exceeds 30mA. This limit is set by the design of the
internal metal interconnects.
Operating Voltage, Input, and Output
Output Phase Reversal
The EL5221C is specified with a single nominal supply
voltage from 5V to 15V or a split supply with its total
range from 5V to 15V. Correct operation is guaranteed
for a supply range of 4.5V to 16.5V. Most EL5221C
specifications are stable over both the full supply range
and operating temperatures of -40°C to +85°C. Parame-
ter variations with operating voltage and/or temperature
are shown in the typical performance curves.
The EL5221C is immune to phase reversal as long as the
input voltage is limited from VS- -0.5V to VS+ +0.5V.
Figure 2 shows a photo of the output of the device with
the input voltage driven beyond the supply rails.
Although the device's output will not change phase, the
input's overvoltage should be avoided. If an input volt-
age exceeds supply voltage by more than 0.6V,
electrostatic protection diodes placed in the input stage
of the device begin to conduct and overvoltage damage
could occur.
The output swings of the EL5221C typically extend to
within 80mV of positive and negative supply rails with
load currents of 5mA. Decreasing load currents will
extend the output voltage range even closer to the supply
rails. Figure 1 shows the input and output waveforms for
the device. Operation is from 5V supply with a 10kΩ
load connected to GND. The input is a 10VP-P sinusoid.
1V
10µS
The output voltage is approximately 9.985VP-P
.
V =±2.5V
S
T =25°C
A
V =6V
IN
P-P
5V
10µS
1V
V =±5V
S
T =25°C
A
V =10V
IN
P-P
Figure 2. Operation with Beyond-the-Rails
Input
Power Dissipation
5V
With the high-output drive capability of the EL5221C
buffer, it is possible to exceed the 125°C 'absolute-max-
imum junction temperature' under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
Figure 1. Operation with Rail-to-Rail Input and
Output
10
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
determine if load conditions need to be modified for the
buffer to remain in the safe operating area.
the device’s power derating curves. To ensure proper
operation, it is important to observe the recommended
derating curves shown in Figure 3 and Figure 4.
The maximum power dissipation allowed in a package is
determined according to:
Package Mounted on a JEDEC JESD51-7 High
Effective Thermal Conductivity Test Board
T
– T
AMAX
1
JMAX
P
= --------------------------------------------
DMAX
870mW
Θ
MAX T =125°C
J
JA
0.8
where:
TJMAX = Maximum Junction Temperature
AMAX= Maximum Ambient Temperature
JA = Thermal Resistance of the Package
DMAX = Maximum Power Dissipation in the
0.6
435mW
0.4
T
Θ
0.2
0
P
Package
0
25
50
75 85 100
125
150
Ambient Temperature (°C)
The maximum power dissipation actually produced by
an IC is the total quiescent supply current times the total
power supply voltage, plus the power in the IC due to the
loads, or:
Figure 3. Package Power Dissipation vs
Ambient Temperature
P
= Σi[V × I
+ (V + – V
i) × I
i]
DMAX
S
SMAX
S
OUT
LOAD
Package Mounted on a JEDEC JESD51-3 Low
Effective Thermal Conductivity Test Board
when sourcing, and
0.6
P
= Σi[V × I
+ (V
i – V -) × I
OUT S
i]
DMAX
S
SMAX
LOAD
MAX T =125°C
J
486mW
391mW
0.5
0.4
0.3
0.2
0.1
0
when sinking.
where:
i = 1 to 2 for Dual Buffer
VS = Total Supply Voltage
I
SMAX = Maximum Supply Current Per Channel
VOUTi = Maximum Output Voltage of the
0
25
50
75 85 100
125
150
Application
Ambient Temperature (°C)
ILOADi = Load Current
Figure 4. Package Power Dissipation vs
Ambient Temperature
If we set the two PDMAX equations equal to each other,
we can solve for RLOADi to avoid device overheat. Fig-
ure 3 and Figure 4 provide a convenient way to see if the
device will overheat. The maximum safe power dissipa-
tion can be found graphically, based on the package type
and the ambient temperature. By using the previous
equation, it is a simple matter to see if PDMAX exceeds
Unused Buffers
It is recommended that any unused buffer have the input
tied to the ground plane.
11
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Driving Capacitive Loads
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5221C can drive a wide range of capacitive
loads. As load capacitance increases, however, the -3dB
bandwidth of the device will decrease and the peaking
increase. The buffers drive 10pF loads in parallel with
10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB
of peaking. If less peaking is desired in these applica-
tions, a small series resistor (usually between 5Ω and
50Ω) can be placed in series with the output. However,
this will obviously reduce the gain slightly. Another
method of reducing peaking is to add a "snubber" circuit
at the output. A snubber is a shunt load consisting of a
resistor in series with a capacitor. Values of 150Ω and
10nF are typical. The advantage of a snubber is that it
does not draw any DC load current or reduce the gain
The EL5221C can provide gain at high frequency. As
with any high frequency device, good printed circuit
board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible, and the power
supply pins must be well bypassed to reduce the risk of
oscillation. For normal single supply operation, where
the VS- pin is connected to ground, a 0.1µF ceramic
capacitor should be placed from VS+ to pin to VS- pin. A
4.7µF tantalum capacitor should then be connected in
parallel, placed in the region of the buffer. One 4.7µF
capacitor may be used for multiple devices. This same
capacitor combination should be placed at each supply
pin to ground if split supplies are to be used.
12
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the cir-
cuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to sup-
port or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users con-
templating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elan-
tec, Inc.’s warranty is limited to replacement of defective
Elantec Semiconductor, Inc.
675 Trade Zone Blvd.
Milpitas, CA 95035
Telephone: (408) 945-1323
(888) ELANTEC
Fax:
(408) 945-9305
components and does not cover injury to persons or property or
other consequential damages.
European Office: +44-118-977-6080
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Printed in U.S.A.
13
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