EL5126CL-T7 [INTERSIL]

8-Channel TFT-LCD Reference Voltage Generator; 8通道TFT -LCD参考电压发生器


型号：	EL5126CL-T7
厂家：	Intersil
描述：	8-Channel TFT-LCD Reference Voltage Generator 8通道TFT -LCD参考电压发生器电压发生器 CD
文件：	总11页 (文件大小：390K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EL5126

Data Sheet

April 2003

FN7337.1

8-Channel TFT-LCD Reference Voltage

Generator

Features

• 8-channel reference outputs

The EL5126 is designed to produce

the reference voltages required in

• Accuracy of ±0.1%

• Supply voltage of 4.5V to 16.5V

• Digital supply 3.3V to 5V

• Low supply current of 10mA

• Rail-to-rail capability

TFT-LCD applications. Each output is

programmed to the required voltage with 10 bits of

resolution. Reference pins determine the high and low

voltages of the output range, which are capable of swinging

to either supply rail. Programming of each output is

performed using the serial interface.

• I C control interface

A number of the EL5126 can be stacked for applications

requiring more than 8 outputs. The reference inputs can be

tied to the rails, enabling each part to output the full voltage

range, or alternatively, they can be connected to external

resistors to split the output range and enable finer

resolutions of the outputs.

Applications

• TFT-LCD drive circuits

• Reference voltage generators

Pinout

The EL5126 has 8 outputs and is available in a 32-pin LPP

package. It is specified for operation over the full -40°C to

+85°C temperature range.

EL5126

(32-PIN LPP)

TOP VIEW

Ordering Information

PART NUMBER

PACKAGE

32-Pin LPP

TAPE & REEL

PKG. NO.

MDP0046

EL5126CL

VSD

25 OUTA

24 OUTB

23 OUTC

22 OUTD

21 DGND

20 OUTE

19 OUTF

18 OUTG

17 OUTH

EL5126CL-T7

EL5126CL-T13

7”

13”

REFH

REFL

AGND

CAP

THERMAL

PAD

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

EL5126

Absolute Maximum Ratings (T = 25°C)

Supply Voltage between V and GND. . . . . . . . . . . . . . . . . . . .+18V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Supply Voltage between V

and GND . . . . . . . . . . . . . . . . . . .+7V

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: T = T = T

Electrical Specifications

= 18V, V

= 5V, V

= 13V, V

= 2V, R = 1.5kΩ and C = 200pF to 0V, T = 25°C Unless

REFH

REFL

Otherwise Specified.

PARAMETER

SUPPLY

DESCRIPTION

CONDITION

MIN

TYP

MAX

UNIT

Supply Current

No load

7.6

1.9

Digital Supply Current

3.2

ANALOG

Output Swing Low

Output Swing High

Short Circuit Current

Power Supply Rejection Ratio

Program to Out Delay

Accuracy

Sinking 5mA

14.95

240

150

Sourcing 5mA

14.85

150

= 10Ω

PSRR

V + is moved from 14V to 16V

Droop Voltage

= 25kHz

CLOCK

mV/ms

kΩ

DROOP

Input Resistance @ V

Load Regulation

, V

REFH REFL

INH

REG

= 5mA step

0.5

1.5

mV/mA

OUT

DIGITAL

Logic 1 Input Voltage

Logic 0 Input Voltage

Clock Frequency

20%

20%*

400

kHz

GΩ

CLK

Input Resistance

SDIN

DIN

Setup Time

Hold Time

Rise Time

Fall Time

EL5126

Pin Descriptions

PIN NUMBER

PIN NAME

PIN TYPE

Power

PIN DESCRIPTION

1, 3, 9

Positive power supply for analog circuits

Positive power supply for digital circuits

High reference voltage

VSD

Power

REFH

REFL

GND

Analog Input

Power

Low reference voltage

6, 21, 11, 13

Ground

CAP

Analog

Decoupling capacitor for internal reference generator

8, 12, 14, 15, 16, 26

Logic Input

Analog Output

Logic Input

Development I C address input, bit 0

OUTH

OUTG

OUTF

OUTE

OUTD

OUTC

OUTB

OUTA

FILTER

STD/REG

SCL

Channel H programmable output voltage

Channel G programmable output voltage

Channel F programmable output voltage

Channel E programmable output voltage

Channel D programmable output voltage

Channel C programmable output voltage

Channel B programmable output voltage

Channel A programmable output voltage

Activates internal I C data filter, high = enable, low = disable

Logic Input

Selects mode, high = standard, low = register mode

Logic Input

I C clock

SDA

Logic Input

I C data input

OSC

IP/OP

Oscillator pin for synchronizing multiple chips

OSC_SEL

Logic Input

Selects internal/external OSC source, high = external, low = internal

Typical Performance Curves

0.3

0.2

0.1

7.8

ALL CHANNEL OUTPUT = 0V

7.6

7.4

7.2

7.0

6.8

6.6

6.4

-0.1

V =15V

=5V

-0.2

-0.3

=13V

=2V

REFH

REFL

(V)

210

410

INPUT CODE

610

810

1010

FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE

FIGURE 2. SUPPLY VOLTAGE vs SUPPLY CURRENT

EL5126

Typical Performance Curves (Continued)

V =V

=15V

M=400ns/DIV

REFH

1.2

V =V

=15V

REFH

=0V

REFL

1.0

0.8

0.6

0.4

0.2

0mA

5mA

5mA/DIV

C =4.7nF

R =20Ω

200mV/DIV

C =1nF

R =20Ω

C =180pF

3.2 3.4 3.5 3.8

4.2 4.4 4.5 4.8

(V)

FIGURE 3. DIGITAL SUPPLY VOLTAGE vs DIGITAL SUPPLY

CURRENT

FIGURE 4. TRANSIENT LOAD REGULATION (SOURCING)

V =V

=15V

M=400ns/DIV

REFH

SCLK

5mA

0mA

SDA

C =1nF

R =20Ω

10V

C =4.7nF

R =20Ω

OUTPUT

C =180pF

M=400µs/DIV

FIGURE 5. TRANSIENT LOAD REGULATION (SINKING)

FIGURE 6. LARGE SIGNAL RESPONSE (RISING FROM 0V

TO 8V)

SCLK

SDA

SCLK

SDA

OUTPUT

200mV

OUTPUT

M=400µs/DIV

FIGURE 7. LARGE SIGNAL RESPONSE (FALLING FROM 8V

TO 0V)

FIGURE 8. SMALL SIGNAL RESPONSE (RISING FROM 0V

TO 200mV)

EL5126

Typical Performance Curves (Continued)

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD - LPP EXPOSED

DIEPAD SOLDERED TO PCB PER JESD51-5

2.5

SCLK

SDA

2.857W

1.5

OUTPUT

0.5

75 85 100

125

150

M=400µs/DIV

AMBIENT TEMPERATURE (°C)

FIGURE 9. SMALL SIGNAL RESPONSE (FALLING FROM

200mV TO 0V)

FIGURE 10. POWER DISSIPATION vs AMBIENT

TEMPERATURE

JEDEC JESD51-3 AND SEMI G42-88

(SINGLE LAYER) TEST BOARD

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

758mW

75 85 100

125

150

AMBIENT TEMPERATURE (°C)

FIGURE 11. POWER DISSIPATION vs AMBIENT TEMPERATURE

Digital Interface

General Description

The EL5126 uses a simple two-wire I C digital interface to

program the outputs. The bus line SCLK is the clock signal

line and bus SDA is the data information signal line. The

EL5126 can support the clock rate up to 400kHz. External

pull up resistor is required for each bus line. The typical

value for these two pull up resistor is about 1kΩ.

The EL5126 provides a versatile method of providing the

reference voltages that are used in setting the transfer

characteristics of LCD display panels. The V/T

(Voltage/Transmission) curve of the LCD panel requires that

a correction is applied to make it linear; however, if the panel

is to be used in more than one application, the final curve

may differ for different applications. By using the EL5126,

the V/T curve can be changed to optimize its characteristics

according to the required application of the display product.

Each of the eight reference voltage outputs can be set with a

10-bit resolution. These outputs can be driven to within

50mV of the power rails of the EL5126. As all of the output

buffers are identical, it is also possible to use the EL5126 for

applications other than LCDs where multiple voltage

references are required that can be set to 10 bit accuracy.

START AND STOP CONDITION

The Start condition is a high to low transition on the SDA line

while SCLK is high. The Stop condition is a low to high

transition on the SDA line while SCLK is high. The start and

stop conditions are always generated by the master. The

bus is considered to be busy after the start condition and to

be free again a certain time after the stop condition. The two

bus lines must be high when the buses are not in use. The

I C Timing Diagram 2 shows the format.

EL5126

DATA VALIDITY

the eight outputs at one time. Two data bytes are required for

10-bit data for each channel output and there are total of 16

data bytes for 8 channels. Data in data byte 1 and 2 is for

channel A. Data in data byte 15 and 16 is for channel H. D9

to D0 are the 10-bit data for each channel. The unused bits

in the data byte are "don't care" and can be set to either one

or zero. See Table 1 for program sample for one channel

setting:

The data on the SDA line must be stable during the high

period of the clock. The high or low state of the data line can

only change when the clock signal on the SCLK line is low.

BYTE FORMAT AND ACKNOWLEDGE

Every byte put on the SDA line must be eight bits long. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an

acknowledge bit. Data is transferred with the most significant

bit first (MSB).

TABLE 1.

DATA

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

CONDITION

Data value = 0

The master puts a resistive high level on the SDA line during

the acknowledge clock pulse. The peripheral that

acknowledges has to pull down the SDA line during the

acknowledge clock pulse.

Data value = 512

Data value = 31

Data value = 1023

DEVICES ADDRESS AND W/R BIT

Data transfers follow the format shown in Timing Diagram 1.

After the Start condition, a first byte is sent which contains

the Device Address and write/read bit. This address is a 7-

bit long device address and only two device addresses (74H

and 75H) are allowed for the EL5126. The first 6 bits (A6 to

A1, MSBs) of the device address have been factory

programmed and are always 111010. Only the least

significant bit A0 is allowed to change the logic state, which

can be tied to VSD or DGND. A maximum of two EL5126

may be used on the same bus at one time. The EL5126

monitors the bus continuously and waiting for the start

condition followed by the device address. When a device

recognizes its device address, it will start to accept data. An

eighth bit is followed by the device address, which is a data

direction bit (W/R). A "0" indicates a Write transmission and

a "1" indicates a Read transmission.

When the W/R bit is high, the master can read the data from

the EL5126. See Timing Diagram 1 for detail formats.

The part operates at Register Mode if pin 28 (STD/REG) is

held low. The Register Mode allows the user to program

each output individually. Followed by the first byte, the

second byte sets the register address for the programmed

output channel. Bits R0 to R3 set the output channel

address. For the unused bits in the R4 to R7 are "don't care".

See Table 2 for program sample.

The EL5126 also allows the user to read the data at Register

Mode. See Timing Diagram 1 for detail formats.

DIGITAL FILTER

A user selectable digital filter can be used to filter noise

spikes from the SCLK and SDA inputs. When the Filter pin

(pin27) is high, the digital filter is enabled. When the Filter

pin is low, the digital filter is disabled.

The EL5126 can be operated as Standard mode and

formats.

STANDARD MODE

The part operates at Standard Mode if pin 28 (STD/REG) is

held high. The Standard Mode allows the user to program

TABLE 2.

DATA

CONDITION

Channel A, Value = 0

Channel B, Value = 512

Channel C, Value = 31

Channel H, Value = 1023

I C Timing Diagram 1

STANDARD MODE (STD/REG = HIGH) WRITE MODE

= don’t care

Data 1

I C

Start

Device Address

Data 2

Data 3

Data 16

Stop

Data

I C

Data In

A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5

D2 D1 D0

I C

CLK In

6 7 8

STANDARD MODE (STD/REG = HIGH) READ MODE

I C

Start

Device Address

Data 1

Data 2

Data 3

Data 16

Stop

Data

I C

Data In

A6 A5 A4 A3 A2 A1 A0

I C

Data Out

D7 D6 D5 D4 D3 D2 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5

D2 D1 D0

I C

CLK In

6 7 8

I C

Start

Device Address

Data 1

Data 2

Stop

Data

I C

Data In

A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 R3 R2 R1 R0

D7 D6 D5 D4 D3 D2 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

I C

CLK In

3 4 5 6 7 8

I C

Start

Device Address

Start

Device Address

Data 1

Data 2

NA Stop

Data

I C

Data In

A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 R3 R2 R1 R0

A6 A5 A4 A3 A2 A1 A0

I C

Data Out

D7 D6 D5 D4 D3 D2 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

I C

CLK In

1 2 3 4 5 6 7 8

EL5126

positive than the V

potential. The second EL5126 can

I C Timing Diagram 2

COM

provide the Gamma correction voltage more negative than

the V

potential. The Application Drawing shows a

COM

START

STOP CONDITION

system connected in this way.

CONDITION

CLOCK OSCILLATOR

DATA

The EL5126 requires an internal clock or external clock to

refresh its outputs. The outputs are refreshed at the falling OSC

clock edges. The output refreshed switches open at the rising

edges of the OSC clock. The driving load shouldn’t be changed

at the rising edges of the OSC clock. Otherwise, it will generate

a voltage error at the outputs. This clock may be input or output

via the clock pin labeled OSC. The internal clock is provided by

an internal oscillator running at approximately 21kHz and can

be output to the OSC pin. In a 2 chip system, if the driving loads

are stable, one chip may be programmed to use the internal

oscillator; then the OSC pin will output the clock from the

internal oscillator. The second chip may have the OSC pin

connected to this clock source.

CLOCK

START, STOP & TIMING DETAILS OF I C INTERFACE

Analog Section

TRANSFER FUNCTION

The transfer function is:

data

------------

= V

× (V

- V

)

REFL

OUT(IDEAL)

REFL

REFH

1024

For transient load application, the external clock Mode

should be used to ensure all functions are synchronized

together. The positive edge of the external clock to the OSC

pin should be timed to avoid the transient load effect. The

Application Drawing shows the LCD H rate signal used, here

the positive clock edge is timed to avoid the transient load of

the column driver circuits.

where data is the decimal value of the 10-bit data binary

input code.

The output voltages from the EL5126 will be derived from

the reference voltages present at the V

and V

REFH

REFL

pins. The impedance between those two pins is about 32kΩ.

After power on, the chip will start with the internal oscillator

mode. At this time, the OSC pin will be in a high impedance

condition to prevent contention. By setting pin 32 to high, the

chip is on external clock mode. Setting pin 32 to low, the chip

is on internal clock mode.

Care should be taken that the system design holds these two

reference voltages within the limits of the power rails of the

EL5126. GND < V

REFH

≤ V and GND ≤ V

REFL

≤ V .

REFH

In some LCD applications that require more than 8 channels,

the system can be designed such that one EL5126 will

provide the Gamma correction voltages that are more

EL5126

Block Diagram

REFERENCE HIGH

OUT

EIGHT

VOLTAGE

SOURCES

CHANNEL

MEMORY

REFERENCE LOW

REFERENCE DECOUPLE

I C DATA IN

CONTROL IF

I C CLOCK IN

FILTER

STD/REG

OSCILLATOR OSCILLATOR

SELECT INPUT/OUTPUT

CHANNEL OUTPUTS

POWER DISSIPATION

Each of the channel outputs has a rail-to-rail buffer. This

enables all channels to have the capability to drive to within

100mV of the power rails, (see Electrical Characteristics for

details).

With the 30mA maximum continues output drive capability

for each channel, it is possible to exceed the 125°C absolute

maximum junction temperature. Therefore, it is important to

calculate the maximum junction temperature for the

application to determine if load conditions need to be

modified for the part to remain in the safe operation.

When driving large capacitive loads, a series resistor should

be placed in series with the output. (Usually between 5Ω and

50Ω).

The maximum power dissipation allowed in a package is

determined according to:

Each of the channels is updated on a continuous cycle, the

time for the new data to appear at a specific output will

depend on the exact timing relationship of the incoming data

to this cycle.

- T

AMAX

JMAX

= --------------------------------------------

DMAX

The best-case scenario is when the data has just been

captured and then passed on to the output stage

immediately; this can be as short as 48µs. In the worst-case

scenario this will be 380µs, when the data has just missed

the cycle.

where:

• T

= Maximum junction temperature

= Maximum ambient temperature

JMAX

AMAX

• θ = Thermal resistance of the package

When a large change in output voltage is required, the

change will occur in 2V steps, thus the requisite number of

timing cycles will be added to the overall update time. This

means that a large change of 16V can take between 3ms

and 3.4ms depending on the absolute timing relative to the

update cycle.

• P

DMAX

= Maximum power dissipation in the package

EL5126

The maximum power dissipation actually produced by the IC

is the total quiescent supply current times the total power

supply voltage and plus the power in the IC due to the loads.

POWER SUPPLY BYPASSING AND PRINTED CIRCUIT

BOARD LAYOUT

Good printed circuit board layout is necessary for optimum

performance. A low impedance and clean analog ground

plane should be used for the EL5126. The traces from the

two ground pins to the ground plane must be very short. The

thermal pad of the EL5126 should be connected to the

analog ground plane. Lead length should be as short as

possible and all power supply pins must be well bypassed. A

= V × I + Σ[(V - V

i) × I

LOAD

DMAX

OUT

when sourcing, and:

= V × I + Σ(V

i × I

LOAD

DMAX

OUT

when sinking.

Where:

0.1µF ceramic capacitor must be place very close to the V ,

, V , and CAP pins. A 4.7µF local bypass

REFH REFL

tantalum capacitor should be placed to the V , V

REFH

, and

• i = 1 to total 8

pins.

REFL

• V = Supply voltage

APPLICATION USING THE EL5126

• I = Quiescent current

In the first application drawing, the schematic shows the

interconnect of a pair of EL5126 chips connected to give

• V

• I

i = Output voltage of the i channel

i = Load current of the i channel

OUT

8 gamma corrected voltages above the V

8 gamma corrected voltages below the V

voltage, and

voltage.

COM

LOAD

By setting the two P

equations equal to each other, we

DMAX

can solve for the R

's to avoid the device overheat. The

LOAD

package power dissipation curves provide a convenient way

to see if the device will overheat.

EL5126

Application Drawing

HIGH REFERENCE

VOLTAGE

COLUMN

(SOURCE)

DRIVER

+10V

REFH

OUTA

OUTB

OUTC

OUTD

OUTE

OUTF

0.1µF

+12V

+5V

0.1µF

LCD PANEL

VSD

MICROCONTROLLER

0.1µF

FILTER

I C DATA IN

SDA

ADDRESS = H74

I C CLOCK

SCL

OSC

OSC_SEL

CAP

LCD

HORIZONTAL RATE

TIMING

CONTROLLER

+5V

0.1µF

OUT

REFL

STD

GND

OUTH

EL5126

MIDDLE REFERENCE VOLTAGE

+5.5V

REFH

OSC

OUTA

OUTB

OUTC

OUTD

OUTE

OUTF

+5V

OSC_SEL

+12V

0.1µF

+5V

VSD

0.1µF

FILTER

SDA

I C DATA IN

I C CLOCK

ADDRESS = H75

SCL

CAP

0.1µF

LOW REFERENCE

VOLTAGE

+1V

REFL

0.1µF

OUT

STD

GND

OUTH

EL5126

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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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EL5126CL-T7 [INTERSIL]

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