EL5126CLZ [INTERSIL]
8-Channel TFT-LCD Reference Voltage Generator; 8通道TFT -LCD参考电压发生器![EL5126CLZ](http://pdffile.icpdf.com/pdf1/p00113/img/icpdf/EL5126_613633_icpdf.jpg)
型号: | EL5126CLZ |
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描述: | 8-Channel TFT-LCD Reference Voltage Generator |
文件: | 总12页 (文件大小:323K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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EL5126
®
Data Sheet
August 24, 2006
FN7337.2
8-Channel TFT-LCD Reference Voltage
Generator
Features
• 8-channel reference outputs
• Accuracy of ±0.1%
The EL5126 is designed to produce
the reference voltages required in
• Supply voltage of 4.5V to 16.5V
• Digital supply 3.3V to 5V
• Low supply current of 10mA
• Rail-to-rail capability
TFT-LCD applications. Each output is
programmed to the required voltage with 10 bits of
resolution. Reference pins determine the high and low
voltages of the output range, which are capable of swinging
to either supply rail. Programming of each output is
performed using the serial interface.
2
• I C control interface
A number of the EL5126 can be stacked for applications
requiring more than 8 outputs. The reference inputs can be
tied to the rails, enabling each part to output the full voltage
range, or alternatively, they can be connected to external
resistors to split the output range and enable finer
resolutions of the outputs.
Applications
• TFT-LCD drive circuits
• Reference voltage generators
Pinout
The EL5126 has 8 outputs and is available in a 32 Ld QFN
package. It is specified for operation over the full -40°C to
+85°C temperature range.
EL5126
(32 LD 5X6 QFN)
TOP VIEW
Ordering Information
TAPE
PART
PART
AND
NUMBER
MARKING PACKAGE REEL
PKG. NO.
MDP0046
MDP0046
VS
VSD
VS
1
2
3
4
5
6
7
8
9
25 OUTA
24 OUTB
23 OUTC
22 OUTD
21 DGND
20 OUTE
19 OUTF
18 OUTG
17 OUTH
EL5126CL
5126CL
32 Ld QFN
-
-
EL5126CLZ
(Note)
5126CLZ
32 Ld QFN
(Pb-free)
EL5126CL-T7
5126CL
32 Ld QFN
7”
7”
MDP0046
MDP0046
REFH
REFL
AGND
CAP
NC
PAD
EL5126CLZ-T7
(Note)
5126CLZ
32 Ld QFN
(Pb-free)
THERMAL
EL5126CL-T13
5126CL
32 Ld QFN
13”
13”
MDP0046
MDP0046
EL5126CLZ-T13 5126CLZ
(Note)
32 Ld QFN
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
VS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL5126
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage between V and GND. . . . . . . . . . . . . . . . . . . .+18V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
S
Supply Voltage between V
and GND . . . . . . . . . . . . . . . . . . .+7V
SD
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
Electrical Specifications
V
= 18V, V
= 5V, V
= 13V, V
= 2V, R = 1.5kΩ and C = 200pF to 0V, T = +25°C Unless
S
SD
REFH
REFL
L
L
A
Otherwise Specified.
PARAMETER
SUPPLY
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
I
I
Supply Current
No load
7.6
1.9
9
mA
mA
S
Digital Supply Current
3.2
SD
ANALOG
V
V
Output Swing Low
Output Swing High
Short Circuit Current
Power Supply Rejection Ratio
Program to Out Delay
Accuracy
Sinking 5mA
50
14.95
240
60
150
mV
V
OL
Sourcing 5mA
14.85
150
45
OH
I
R
= 10Ω
L
mA
SC
PSRR
V + is moved from 14V to 16V
dB
S
t
4
ms
D
V
20
mV
AC
V
Droop Voltage
F
= 25kHz
CLOCK
1
2
mV/ms
kΩ
DROOP
R
Input Resistance @ V
Load Regulation
, V
REFH REFL
32
INH
REG
I
= 5mA step
0.5
1.5
mV/mA
OUT
DIGITAL
V
Logic 1 Input Voltage
Logic 0 Input Voltage
Clock Frequency
V
-
V
V
IH
SD
20%
V
20%*
IL
V
SD
F
400
kHz
GΩ
ns
CLK
R
S
Input Resistance
1
SDIN
DIN
t
t
t
t
Setup Time
Hold Time
Rise Time
Fall Time
40
40
20
20
S
ns
H
R
F
ns
ns
2
EL5126
Pin Descriptions
PIN NUMBER
PIN NAME
VS
PIN TYPE
Power
PIN DESCRIPTION
1, 3, 9
Positive power supply for analog circuits
Positive power supply for digital circuits
High reference voltage
2
VSD
Power
4
REFH
REFL
GND
Analog Input
Analog Input
Power
5
Low reference voltage
6, 21, 11, 13
Ground
7
CAP
Analog
Decoupling capacitor for internal reference generator
8, 12, 14, 15, 16, 26
NC
2
10
17
18
19
20
22
23
24
25
27
28
29
30
31
32
A0
Logic Input
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Logic Input
Development I C address input, bit 0
OUTH
OUTG
OUTF
OUTE
OUTD
OUTC
OUTB
OUTA
FILTER
STD/REG
SCL
Channel H programmable output voltage
Channel G programmable output voltage
Channel F programmable output voltage
Channel E programmable output voltage
Channel D programmable output voltage
Channel C programmable output voltage
Channel B programmable output voltage
Channel A programmable output voltage
2
Activates internal I C data filter, high = enable, low = disable
Logic Input
Selects mode, high = standard, low = register mode
2
Logic Input
I C clock
2
SDA
Logic Input
I C data input
OSC
IP/OP
Oscillator pin for synchronizing multiple chips
OSC_SEL
Logic Input
Selects internal/external OSC source, high = external, low = internal
Typical Performance Curves
0.3
0.2
0.1
0
7.8
ALL CHANNEL OUTPUT = 0V
7.6
7.4
7.2
7.0
6.8
6.6
6.4
-0.1
V =15V
S
V
=5V
=13V
=2V
SD
-0.2
-0.3
V
V
REFH
REFL
4
6
8
10
V
12
(V)
14
16
18
10
210
410
610
810
1010
S
INPUT CODE
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. SUPPLY VOLTAGE vs SUPPLY CURRENT
3
EL5126
Typical Performance Curves (Continued)
V =V
=15V
M=400ns/DIV
S
REFH
1.2
V =V
=15V
S
REFH
=0V
V
REFL
1.0
0.8
0.6
0.4
0.2
0
0mA
5mA
5mA/DIV
C =4.7nF
L
R =20Ω
S
5V
200mV/DIV
C =1nF
L
R =20Ω
S
C =180pF
L
3
3.2 3.4 3.5 3.8
4
4.2 4.4 4.5 4.8
(V)
5
V
SD
FIGURE 3. DIGITAL SUPPLY VOLTAGE vs DIGITAL SUPPLY
CURRENT
FIGURE 4. TRANSIENT LOAD REGULATION (SOURCING)
V =V
=15V
M=400ns/DIV
S
REFH
SCLK
5mA
0mA
5V
0V
SDA
C =1nF
L
5V
R =20Ω
S
0V
10V
5V
C =4.7nF
L
R =20Ω
S
OUTPUT
C =180pF
L
0V
M=400µs/DIV
FIGURE 5. TRANSIENT LOAD REGULATION (SINKING)
FIGURE 6. LARGE SIGNAL RESPONSE (RISING FROM 0V
TO 8V)
SCLK
SDA
SCLK
5V
0V
SDA
5V
0V
OUTPUT
200mV
OUTPUT
0V
M=400µs/DIV
M=400µs/DIV
FIGURE 7. LARGE SIGNAL RESPONSE (FALLING FROM 8V
TO 0V)
FIGURE 8. SMALL SIGNAL RESPONSE (RISING FROM 0V
TO 200mV)
4
EL5126
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - LPP EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3
2.5
2
SCLK
SDA
2.857W
1.5
1
OUTPUT
0.5
0
0
25
50
75 85 100
125
150
M=400µs/DIV
AMBIENT TEMPERATURE (°C)
FIGURE 9. SMALL SIGNAL RESPONSE (FALLING FROM
200mV TO 0V)
FIGURE 10. POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 AND SEMI G42-88
(SINGLE LAYER) TEST BOARD
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
758mW
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 11. POWER DISSIPATION vs AMBIENT TEMPERATURE
Digital Interface
General Description
2
The EL5126 uses a simple two-wire I C digital interface to
program the outputs. The bus line SCLK is the clock signal
line and bus SDA is the data information signal line. The
EL5126 can support the clock rate up to 400kHz. External
pull up resistor is required for each bus line. The typical
value for these two pull up resistor is about 1kΩ.
The EL5126 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5126,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5126. As all of the output
buffers are identical, it is also possible to use the EL5126 for
applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
START AND STOP CONDITION
The Start condition is a high to low transition on the SDA line
while SCLK is high. The Stop condition is a low to high
transition on the SDA line while SCLK is high. The start and
stop conditions are always generated by the master. The
bus is considered to be busy after the start condition and to
be free again a certain time after the stop condition. The two
bus lines must be high when the buses are not in use. The
2
I C Timing Diagram 2 shows the format.
5
EL5126
DATA VALIDITY
the eight outputs at one time. Two data bytes are required for
10-bit data for each channel output and there are total of 16
data bytes for 8 channels. Data in data byte 1 and 2 is for
channel A. Data in data byte 15 and 16 is for channel H. D9
to D0 are the 10-bit data for each channel. The unused bits
in the data byte are "don't care" and can be set to either one
or zero. See Table 1 for program sample for one channel
setting:
The data on the SDA line must be stable during the high
period of the clock. The high or low state of the data line can
only change when the clock signal on the SCLK line is low.
BYTE FORMAT AND ACKNOWLEDGE
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
TABLE 1.
DATA
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CONDITION
Data value = 0
The master puts a resistive high level on the SDA line during
the acknowledge clock pulse. The peripheral that
acknowledges has to pull down the SDA line during the
acknowledge clock pulse.
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Data value = 512
Data value = 31
Data value = 1023
DEVICES ADDRESS AND W/R BIT
Data transfers follow the format shown in Timing Diagram 1.
After the Start condition, a first byte is sent which contains
the Device Address and write/read bit. This address is a 7-
bit long device address and only two device addresses (74H
and 75H) are allowed for the EL5126. The first 6 bits (A6 to
A1, MSBs) of the device address have been factory
programmed and are always 111010. Only the least
significant bit A0 is allowed to change the logic state, which
can be tied to VSD or DGND. A maximum of two EL5126
may be used on the same bus at one time. The EL5126
monitors the bus continuously and waiting for the start
condition followed by the device address. When a device
recognizes its device address, it will start to accept data. An
eighth bit is followed by the device address, which is a data
direction bit (W/R). A "0" indicates a Write transmission and
a "1" indicates a Read transmission.
When the W/R bit is high, the master can read the data from
the EL5126. See Timing Diagram 1 for detail formats.
REGISTER MODE
The part operates at Register Mode if pin 28 (STD/REG) is
held low. The Register Mode allows the user to program
each output individually. Followed by the first byte, the
second byte sets the register address for the programmed
output channel. Bits R0 to R3 set the output channel
address. For the unused bits in the R4 to R7 are "don't care".
See Table 2 for program sample.
The EL5126 also allows the user to read the data at Register
Mode. See Timing Diagram 1 for detail formats.
DIGITAL FILTER
A user selectable digital filter can be used to filter noise
spikes from the SCLK and SDA inputs. When the Filter pin
(pin27) is high, the digital filter is enabled. When the Filter
pin is low, the digital filter is disabled.
The EL5126 can be operated as Standard mode and
Register mode. See the I C Timing Diagram 1 for detail
formats.
2
STANDARD MODE
The part operates at Standard Mode if pin 28 (STD/REG) is
held high. The Standard Mode allows the user to program
TABLE 2.
DATA
D5
REGISTER ADDRESS
R3
X
R2
0
R1
0
R0
0
D9
0
D8
0
D7
0
D6
0
D4
0
D3
0
D2
0
D1
0
D0
0
CONDITION
0
0
0
1
Channel A, Value = 0
Channel B, Value = 512
Channel C, Value = 31
Channel H, Value = 1023
X
0
0
1
1
0
0
0
0
0
0
0
0
X
0
1
0
0
0
0
0
1
1
1
1
1
X
1
1
1
1
1
1
1
1
1
1
1
1
6
2
I C Timing Diagram 1
STANDARD MODE (STD/REG = HIGH) WRITE MODE
= don’t care
Data 1
2
I C
Data
Start
Device Address
W
A
A
Data 2
A
Data 3
Data 16
A
Stop
2
I C
Data In
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5
D2 D1 D0
2
I C
CLK In
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
6 7 8
STANDARD MODE (STD/REG = HIGH) READ MODE
2
I C
Start
Device Address
R
A
Data 1
A
Data 2
A
Data 3
Data 16
NA
Stop
Data
2
I C
Data In
A6 A5 A4 A3 A2 A1 A0
2
I C
Data Out
D7 D6 D5 D4 D3 D2 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5
D2 D1 D0
2
I C
CLK In
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
6 7 8
REGISTER MODE (STD/REG = LOW) WRITE MODE
2
I C
Start
Device Address
W
A
Register Address
A
Data 1
A
Data 2
A
Stop
Data
2
I C
Data In
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 R3 R2 R1 R0
D7 D6 D5 D4 D3 D2 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
2
I C
CLK In
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3 4 5 6 7 8
REGISTER MODE (STD/REG = LOW) READ MODE
2
I C
Start
Device Address
W
A
Register Address
A
Start
Device Address
R
A
Data 1
A
Data 2
NA Stop
Data
2
I C
Data In
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 R3 R2 R1 R0
A6 A5 A4 A3 A2 A1 A0
2
I C
Data Out
D7 D6 D5 D4 D3 D2 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
2
I C
CLK In
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1 2 3 4 5 6 7 8
EL5126
2
positive than the V
potential. The second EL5126 can
I C Timing Diagram 2
COM
provide the Gamma correction voltage more negative than
the V potential. The Application Drawing shows a
COM
START
t
STOP CONDITION
system connected in this way.
CONDITION
F
t
R
CLOCK OSCILLATOR
DATA
The EL5126 requires an internal clock or external clock to
refresh its outputs. The outputs are refreshed at the falling OSC
clock edges. The output refreshed switches open at the rising
edges of the OSC clock. The driving load shouldn’t be changed
at the rising edges of the OSC clock. Otherwise, it will generate
a voltage error at the outputs. This clock may be input or output
via the clock pin labeled OSC. The internal clock is provided by
an internal oscillator running at approximately 21kHz and can
be output to the OSC pin. In a 2 chip system, if the driving loads
are stable, one chip may be programmed to use the internal
oscillator; then the OSC pin will output the clock from the
internal oscillator. The second chip may have the OSC pin
connected to this clock source.
CLOCK
t
t
t
t
F
S
H
R
t
t
H
S
2
START, STOP & TIMING DETAILS OF I C INTERFACE
Analog Section
TRANSFER FUNCTION
The transfer function is:
data
+ ------------ × (V
V
= V
- V
)
REFL
OUT(IDEAL)
REFL
REFH
1024
For transient load application, the external clock Mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect. The
Application Drawing shows the LCD H rate signal used, here
the positive clock edge is timed to avoid the transient load of
the column driver circuits.
where data is the decimal value of the 10-bit data binary
input code.
The output voltages from the EL5126 will be derived from
the reference voltages present at the V and V
REFL
REFH
pins. The impedance between those two pins is about 32kΩ.
After power on, the chip will start with the internal oscillator
mode. At this time, the OSC pin will be in a high impedance
condition to prevent contention. By setting pin 32 to high, the
chip is on external clock mode. Setting pin 32 to low, the chip
is on internal clock mode.
Care should be taken that the system design holds these two
reference voltages within the limits of the power rails of the
EL5126. GND < V
REFH
≤ V and GND ≤ V
REFL
≤ V .
REFH
S
In some LCD applications that require more than 8 channels,
the system can be designed such that one EL5126 will
provide the Gamma correction voltages that are more
8
EL5126
Block Diagram
REFERENCE HIGH
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
EIGHT
CHANNEL
MEMORY
VOLTAGE
SOURCES
REFERENCE LOW
REFERENCE DECOUPLE
2
I C DATA IN
CONTROL IF
2
I C CLOCK IN
FILTER
STD/REG
A0
OSCILLATOR OSCILLATOR
SELECT INPUT/OUTPUT
CHANNEL OUTPUTS
POWER DISSIPATION
Each of the channel outputs has a rail-to-rail buffer. This
enables all channels to have the capability to drive to within
100mV of the power rails, (see Electrical Characteristics for
details).
With the 30mA maximum continues output drive capability
for each channel, it is possible to exceed the 125°C absolute
maximum junction temperature. Therefore, it is important to
calculate the maximum junction temperature for the
application to determine if load conditions need to be
modified for the part to remain in the safe operation.
When driving large capacitive loads, a series resistor should
be placed in series with the output. (Usually between 5Ω and
50Ω).
The maximum power dissipation allowed in a package is
determined according to:
Each of the channels is updated on a continuous cycle, the
time for the new data to appear at a specific output will
depend on the exact timing relationship of the incoming data
to this cycle.
T
- T
AMAX
JMAX
P
= --------------------------------------------
DMAX
Θ
JA
The best-case scenario is when the data has just been
captured and then passed on to the output stage
immediately; this can be as short as 48µs. In the worst-case
scenario this will be 380µs, when the data has just missed
the cycle.
where:
• T
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMAX
• θ = Thermal resistance of the package
JA
When a large change in output voltage is required, the
change will occur in 2V steps, thus the requisite number of
timing cycles will be added to the overall update time. This
means that a large change of 16V can take between 3ms
and 3.4ms depending on the absolute timing relative to the
update cycle.
• P
DMAX
= Maximum power dissipation in the package
9
EL5126
The maximum power dissipation actually produced by the IC
is the total quiescent supply current times the total power
supply voltage and plus the power in the IC due to the loads.
POWER SUPPLY BYPASSING AND PRINTED CIRCUIT
BOARD LAYOUT
Good printed circuit board layout is necessary for optimum
performance. A low impedance and clean analog ground
plane should be used for the EL5126. The traces from the
two ground pins to the ground plane must be very short. The
thermal pad of the EL5126 should be connected to the
analog ground plane. Lead length should be as short as
possible and all power supply pins must be well bypassed. A
P
= V × I + Σ[(V - V
i) × I
LOAD
i]
DMAX
S
S
S
OUT
when sourcing, and:
P
= V × I + Σ(V
i × I
i)
LOAD
DMAX
S
S
OUT
when sinking.
Where:
0.1µF ceramic capacitor must be place very close to the V ,
S
V
, V , and CAP pins. A 4.7µF local bypass
REFH REFL
tantalum capacitor should be placed to the V , V
, and
• i = 1 to total 8
S
REFH
V
pins.
REFL
• V = Supply voltage
S
APPLICATION USING THE EL5126
• I = Quiescent current
S
In the first application drawing, the schematic shows the
interconnect of a pair of EL5126 chips connected to give
8 gamma corrected voltages above the V
• V
i = Output voltage of the i channel
i = Load current of the i channel
OUT
voltage, and
voltage.
• I
COM
COM
LOAD
8 gamma corrected voltages below the V
By setting the two P
equations equal to each other, we
DMAX
can solve for the R
's to avoid the device overheat. The
LOAD
package power dissipation curves provide a convenient way
to see if the device will overheat.
10
EL5126
Application Drawing
HIGH REFERENCE
VOLTAGE
COLUMN
(SOURCE)
DRIVER
+10V
REFH
OUTA
OUTB
OUTC
OUTD
OUTE
OUTF
0.1µF
+12V
+5V
VS
0.1µF
LCD PANEL
VSD
MICROCONTROLLER
0.1µF
FILTER
AO
2
I C DATA IN
SDA
ADDRESS = H74
2
I C CLOCK
SCL
LCD
TIMING
CONTROLLER
HORIZONTAL RATE
OSC
+5V
OSC_SEL
CAP
0.1µF
OUT
REFL
STD
GND
OUTH
EL5126
MIDDLE REFERENCE VOLTAGE
+5.5V
REFH
OSC
OUTA
OUTB
OUTC
OUTD
OUTE
OUTF
+5V
OSC_SEL
VS
+12V
0.1µF
+5V
VSD
0.1µF
FILTER
AO
2
I C DATA IN
SDA
2
I C CLOCK
ADDRESS = H75
SCL
CAP
0.1µF
LOW REFERENCE
VOLTAGE
+1V
REFL
0.1µF
OUT
STD
GND
OUTH
EL5126
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
EL5126
QFN (Quad Flat No-Lead) Package Family
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
A
SYMBOL QFN44 QFN38
QFN32
TOLERANCE
±0.10
NOTES
D
B
A
A1
b
0.90
0.02
0.25
0.20
7.00
5.10
7.00
5.10
0.50
0.55
44
0.90 0.90
0.90
0.02
0.22
0.20
5.00
-
-
0.02 0.02
0.25 0.23
0.20 0.20
5.00 8.00
+0.03/-0.02
±0.02
-
1
2
3
PIN #1
I.D. MARK
c
Reference
Basic
-
D
-
E
D2
E
3.80 5.80 3.60/2.48
7.00 8.00 6.00
5.80 5.80 4.60/3.40
Reference
Basic
8
-
E2
e
Reference
Basic
8
-
2X
0.075 C
0.50 0.80
0.40 0.53
0.50
0.50
32
L
±0.05
-
2X
0.075 C
N
38
7
32
8
Reference
Reference
Reference
4
6
5
TOP VIEW
ND
NE
11
7
11
12
8
9
0.10 M C A B
b
TOLER-
ANCE NOTES
L
SYMBOL QFN28 QFN24
QFN20
QFN16
0.90
PIN #1 I.D.
A
0.90
0.02
0.90 0.90
0.02 0.02
0.90
0.02
±0.10
-
-
3
1
2
3
A1
0.02
+0.03/
-0.02
b
c
0.25
0.20
4.00
2.65
5.00
3.65
0.50
0.40
28
0.25 0.30
0.20 0.20
4.00 5.00
2.80 3.70
5.00 5.00
3.80 3.70
0.50 0.65
0.40 0.40
0.25
0.20
4.00
2.70
4.00
2.70
0.50
0.40
20
0.33
±0.02
-
-
(E2)
0.20 Reference
4.00 Basic
2.40 Reference
4.00 Basic
2.40 Reference
D
-
5
NE
D2
E
-
-
E2
e
-
7
(D2)
0.65
0.60
16
Basic
-
L
±0.05
-
BOTTOM VIEW
N
24
5
20
5
Reference
Reference
Reference
4
6
5
0.10 C
ND
NE
6
5
4
e
C
8
7
5
5
4
SEATING
PLANE
Rev 10 12/04
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
0.08 C
SEE DETAIL "X"
N LEADS
& EXPOSED PAD
SIDE VIEW
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
(c)
2
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
A
C
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
(L)
A1
DETAIL X
N LEADS
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
12
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