LXT971ABC [INTEL]
3.3V Dual-Speed Fast Ethernet PHY Transceiver; 3.3V双速快速以太网PHY收发器
| 型号： | LXT971ABC |
| 厂家： | 
INTEL |
| 描述： | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| 文件： | 总90页 (文件大小：651K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® LXT971A
3.3V Dual-Speed Fast Ethernet PHY Transceiver
Datasheet
The LXT971A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both
100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs). The LXT971A also provides a
Low Voltage PECL (LVPECL) interface for use with 100BASE-FX fiber networks.
This document also supports the LXT971 device.
The LXT971A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition
can be set using auto-negotiation, parallel detection, or manual control.
The LXT971A is fabricated with an advanced CMOS process and requires only a single 3.3V
power supply.
Applications
■ Combination 10BASE-T/100BASE-TX or ■ 10/100 PCMCIA Cards
100BASE-FX Network Interface Cards
(NICs)
■ Cable Modems and Set-Top Boxes
Product Features
■ 3.3V Operation.
■ Configurable via MDIO serial port or
hardware control pins.
■ Low power consumption (300 mW
typical).
■ Integrated, programmable LED drivers.
■ 64-ball Plastic Ball Grid Array (PBGA).
■ Low-power “Sleep” mode.
■ 10BASE-T and 100BASE-TX using a
— LXT971ABC - Commercial (0° to
single RJ-45 connection.
70°C ambient).
■ Supports auto-negotiation and parallel
—LXT971ABE - Extended (-40° to 85°C
detection.
ambient).
■ MII interface with extended register
■ 64-pin Low-profile Quad Flat Package
capability.
(LQFP).
■ Robust baseline wander correction
— LXT971ALC - Commercial (0° to
performance.
70°C ambient).
■ 100BASE-FX fiber-optic capable.
— LXT971ALE - Extended (-40° to 85°C
■ Standard CSMA/CD or full-duplex
ambient).
operation.
■ Supports JTAG boundary scan.
Order Number: 249414-002
August 2002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELÆ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S
TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY
EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition
and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT971A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized
errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2002
*Third-party brands and names are the property of their respective owners.
2
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
Contents
1.0
2.0
3.0
Pin Assignments ..............................................................................................................................12
Signal Descriptions..........................................................................................................................16
Functional Description.....................................................................................................................21
3.1
Introduction .......................................................................................................................21
3.1.1
3.1.2
Comprehensive Functionality .............................................................................21
OSP™ Architecture ............................................................................................21
3.2
Network Media / Protocol Support....................................................................................22
3.2.1
10/100 Network Interface ...................................................................................22
3.2.1.1 Twisted-Pair Interface ..........................................................................22
3.2.1.2 Fiber Interface.......................................................................................22
3.2.1.3 Fault Detection and Reporting..............................................................23
MII Data Interface...............................................................................................23
3.2.2.1 Increased MII Drive Strength...............................................................23
Configuration Management Interface .................................................................24
3.2.3.1 MDIO Management Interface ..............................................................24
3.2.3.2 Hardware Control Interface..................................................................25
3.2.2
3.2.3
3.3
3.4
Operating Requirements....................................................................................................26
3.3.1
3.3.2
Power Requirements ...........................................................................................26
Clock Requirements............................................................................................26
3.3.2.1 External Crystal/Oscillator ...................................................................26
3.3.2.2 MDIO Clock.........................................................................................26
Initialization.......................................................................................................................26
3.4.1
3.4.2
3.4.3
MDIO Control Mode ..........................................................................................26
Hardware Control Mode .....................................................................................27
Reduced Power Modes........................................................................................28
3.4.3.1 Hardware Power Down ........................................................................28
3.4.3.2 Software Power Down..........................................................................29
3.4.3.3 Sleep Mode...........................................................................................29
Reset....................................................................................................................29
Hardware Configuration Settings........................................................................30
3.4.4
3.4.5
3.5
3.6
Establishing Link...............................................................................................................31
3.5.1
Auto-Negotiation ................................................................................................31
3.5.1.1 Base Page Exchange.............................................................................31
3.5.1.2 Next Page Exchange.............................................................................31
3.5.1.3 Controlling Auto-Negotiation...............................................................31
Parallel Detection................................................................................................31
3.5.2
MII Operation....................................................................................................................32
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
MII Clocks ..........................................................................................................32
Transmit Enable ..................................................................................................33
Receive Data Valid .............................................................................................33
Carrier Sense.......................................................................................................33
Error Signals .......................................................................................................33
Collision..............................................................................................................33
Loopback.............................................................................................................34
3.6.7.1 Operational Loopback ..........................................................................35
Datasheet
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Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.6.7.2 Test Loopback...................................................................................... 35
3.7
3.8
100 Mbps Operation ......................................................................................................... 36
3.7.1
3.7.2
3.7.3
100BASE-X Network Operations...................................................................... 36
Collision Indication............................................................................................ 38
100BASE-X Protocol Sublayer Operations ....................................................... 38
3.7.3.1 PCS Sublayer ....................................................................................... 38
3.7.3.2 PMA Sublayer...................................................................................... 41
3.7.3.3 Twisted-Pair PMD Sublayer................................................................ 42
3.7.3.4 Fiber PMD Sublayer ............................................................................ 43
10 Mbps Operation ........................................................................................................... 43
3.8.1
3.8.2
3.8.3
3.8.4
10BASE-T Preamble Handling.......................................................................... 43
10BASE-T Carrier Sense ................................................................................... 43
10BASE-T Dribble Bits ..................................................................................... 43
10BASE-T Link Integrity Test........................................................................... 44
3.8.4.1 Link Failure.......................................................................................... 44
10BASE-T SQE (Heartbeat).............................................................................. 44
10BASE-T Jabber .............................................................................................. 44
10BASE-T Polarity Correction.......................................................................... 44
3.8.5
3.8.6
3.8.7
3.9
Monitoring Operations ..................................................................................................... 44
3.9.1
3.9.2
Monitoring Auto-Negotiation ............................................................................ 44
3.9.1.1 Monitoring Next Page Exchange......................................................... 45
LED Functions ................................................................................................... 45
3.9.2.1 LED Pulse Stretching........................................................................... 45
3.10
Boundary Scan (JTAG1149.1) Functions ........................................................................ 46
3.10.1 Boundary Scan Interface .................................................................................... 46
3.10.2 State Machine..................................................................................................... 46
3.10.3 Instruction Register ............................................................................................ 46
3.10.4 Boundary Scan Register (BSR).......................................................................... 46
4.0
5.0
Application Information.................................................................................................................. 48
4.1
4.2
4.3
Magnetics Information ..................................................................................................... 48
Typical Twisted-Pair Interface ......................................................................................... 48
The Fiber Interface ........................................................................................................... 52
Test Specifications .......................................................................................................................... 56
5.1
5.2
Electrical Parameters ........................................................................................................ 56
Timing Diagrams.............................................................................................................. 61
6.0
7.0
8.0
Register Definitions ........................................................................................................................ 71
Package Specifications.................................................................................................................... 88
Product Ordering Information......................................................................................................... 90
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Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figures
1
LXT971A Block Diagram...................................................................................................9
64-Pin PBGA Pin Assignments.........................................................................................10
64-Pin LQFP Pin Assignments..........................................................................................11
Management Interface Read Frame Structure...................................................................21
Management Interface Write Frame Structure..................................................................21
Interrupt Logic...................................................................................................................22
Initialization Sequence ......................................................................................................24
Hardware Configuration Settings......................................................................................26
Link Establishment Overview...........................................................................................28
10BASE-T Clocking .........................................................................................................30
100BASE-X Clocking.......................................................................................................30
Link Down Clock Transition.............................................................................................30
Loopback Paths .................................................................................................................31
100BASE-X Frame Format...............................................................................................32
100BASE-TX Data Path....................................................................................................33
100BASE-TX Reception with no Errors...........................................................................33
100BASE-TX Reception with Invalid Symbol.................................................................33
100BASE-TX Transmission with no Errors......................................................................34
100BASE-TX Transmission with Collision......................................................................34
Protocol Sublayers.............................................................................................................35
LED Pulse Stretching ........................................................................................................42
Typical Twisted-Pair Interface - Switch............................................................................45
Typical Twisted-Pair Interface - NIC................................................................................46
Typical MII Interface ........................................................................................................47
Typical Fiber Interface ......................................................................................................48
100BASE-TX Receive Timing - 4B Mode .......................................................................53
100BASE-TX Transmit Timing - 4B Mode......................................................................54
100BASE-FX Receive Timing..........................................................................................55
100BASE-FX Transmit Timing ........................................................................................56
10BASE-T Receive Timing ..............................................................................................57
10BASE-T Transmit Timing.............................................................................................58
10BASE-T Jabber and Unjabber Timing ..........................................................................59
10BASE-T SQE (Heartbeat) Timing.................................................................................59
Auto Negotiation and Fast Link Pulse Timing..................................................................60
Fast Link Pulse Timing .....................................................................................................60
MDIO Input Timing ..........................................................................................................61
MDIO Output Timing........................................................................................................61
Power-Up Timing..............................................................................................................62
RESET Pulse Width and Recovery Timing ......................................................................62
PHY Identifier Bit Mapping..............................................................................................68
PBGA Package Specification............................................................................................79
LXT971A LQFP Package Specifications..........................................................................80
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
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40
41
42
Datasheet
5
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
Tables
1
LQFP Numeric Pin List.................................................................................................... 12
2
LXT971A MII Signal Descriptions.................................................................................. 14
LXT971A Network Interface Signal Descriptions........................................................... 15
LXT971A Miscellaneous Signal Descriptions................................................................. 16
LXT971A Power Supply Signal Descriptions.................................................................. 17
LXT971A JTAG Test Signal Descriptions ...................................................................... 17
LXT971A LED Signal Descriptions ................................................................................ 17
Hardware Configuration Settings ..................................................................................... 26
Carrier Sense, Loopback, and Collision Conditions......................................................... 32
4B/5B Coding................................................................................................................... 36
BSR Mode of Operation................................................................................................... 43
Supported JTAG Instructions ........................................................................................... 43
Device ID Register ........................................................................................................... 43
Magnetics Requirements .................................................................................................. 44
I/O Pin Comparison of NIC and Switch RJ-45 Setups..................................................... 44
Absolute Maximum Ratings............................................................................................. 49
Operating Conditions........................................................................................................ 49
Digital I/O Characteristics 1............................................................................................. 50
Digital I/O Characteristics - MII Pins............................................................................... 50
I/O Characteristics - REFCLK/XI and XO Pins............................................................... 50
I/O Characteristics - LED/CFG Pins ................................................................................ 50
100BASE-TX Transceiver Characteristics....................................................................... 51
100BASE-FX Transceiver Characteristics....................................................................... 51
10BASE-T Transceiver Characteristics............................................................................ 51
10BASE-T Link Integrity Timing Characteristics ........................................................... 52
100BASE-TX Receive Timing Parameters - 4B Mode.................................................... 53
100BASE-TX Transmit Timing Parameters - 4B Mode.................................................. 54
100BASE-FX Receive Timing Parameters ...................................................................... 55
100BASE-FX Transmit Timing Parameters..................................................................... 56
10BASE-T Receive Timing Parameters........................................................................... 57
10BASE-T Transmit Timing Parameters ......................................................................... 58
10BASE-T Jabber and Unjabber Timing Parameters....................................................... 59
10BASE-T SQE Timing Parameters ................................................................................ 59
Auto Negotiation and Fast Link Pulse Timing Parameters .............................................. 60
MDIO Timing Parameters................................................................................................ 61
Power-Up Timing Parameters .......................................................................................... 62
RESET Pulse Width and Recovery Timing Parameters.................................................. 62
Register Set....................................................................................................................... 63
Register Bit Map............................................................................................................... 64
Control Register (Address 0)............................................................................................ 66
MII Status Register #1 (Address 1) .................................................................................. 67
PHY Identification Register 1 (Address 2)....................................................................... 68
PHY Identification Register 2 (Address 3)....................................................................... 68
Auto Negotiation Advertisement Register (Address 4).................................................... 69
Auto Negotiation Link Partner Base Page Ability Register (Address 5) ......................... 70
Auto Negotiation Expansion (Address 6)......................................................................... 71
Auto Negotiation Next Page Transmit Register (Address 7) ........................................... 71
Auto Negotiation Link Partner Next Page Receive Register (Address 8)........................ 72
Configuration Register (Address 16, Hex 10).................................................................. 73
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
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47
48
49
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Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
50
51
52
53
54
Status Register #2 (Address 17) ........................................................................................74
Interrupt Enable Register (Address 18).............................................................................75
Interrupt Status Register (Address 19, Hex 13).................................................................76
LED Configuration Register (Address 20, Hex 14)..........................................................77
Transmit Control Register (Address 30) ...........................................................................78
Datasheet
7
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
Revision History
Revision 002
Revision Date: August 6, 2002
Page
Description
Globally replaced “pseudo-PECL” with Low-Voltage PECL”, except when identified with 5 V.
Front Page: Changed “pseudo-ECL (PECL)” to “Low Voltage PECL (LVPECL).
Added “JTAG Boundary Scan” to Product Features on front page.
1
12
13
14
Modified Figure 2 “LXT971A 64-Ball PBGA Assignments” (replaced TEST1 and TEST0 with GND).
Modified Figure 3 “LXT971A 64-Pin LQFP Assignments” (replaced TEST1 and TEST0 with GND).
Modified Table 1 “LQFP Numeric Pin List” (replaced TEST1 and TEST0 with GND).
Added note under Section 2.0, “Signal Descriptions”: “Intel recommends that all inputs and multi-
function pins be tied to the inactive states and all outputs be left floating, if unused.”
16
17
Modified SD/TP description in Table 3 “LXT971A Network Interface Signal Descriptions”.
Added Table note 2.
18
19
20
22
23
Modified Table 4 “LXT971A Miscellaneous Signal Descriptions”.
Modified Table 5 “LXT971A Power Supply Signal Descriptions”.
Added Table 8 “LXT971A Pin Types and Modes”.
Replaced second paragraph under Section 3.2.1.2, “Fiber Interface”.
Added Section 3.2.2.1, “Increased MII Drive Strength”.
Changed “Far-End Fault” title to ‘100BASE-FX Far-End Fault”.
Modified first sentence under this heading.
23
30
35
43
47
47
52
53
54
55
56
56
57
58
58
60
65
72
86
87
90
Modified Figure 8 “Hardware Configuration Settings”.
Added paragraph after bullets under Section 3.6.7.2, “Test Loopback”.
Modified text under Section 3.7.3.4, “Fiber PMD Sublayer”.
Modified Table 13 “Supported JTAG Instructions”.
Modified Table 14 “Device ID Register”.
Added a new Section 4.3, “The Fiber Interface”.
Replaced Figure 25 “Typical LXT971A-to-3.3 V Fiber Transceiver Interface Circuitry”.
Added Figure 26 “Typical LXT971A-to-5 V Fiber Transceiver Interface Circuitry”.
Added Figure 27 “ON Semiconductor Triple PECL-to-LVPECL Translator”.
Modified Table 17 “Absolute Maximum Ratings”.
Modified Table 18 “Operating Conditions”: Added Typ values to Vcc current.
Modified Table 20 “Digital I/O Characteristics - MII Pins”.
Modified Table 22 “I/O Characteristics - LED/CFG Pins”.
Added Table 23 “I/O Characteristics – SD/TP Pin”.
Added Table 28 “LXT971A Thermal Characteristics”.
Modified Table 33 “10BASE-T Receive Timing Parameters”
Modified Table 42 “Register Bit Map”. (Added Table 26 information).
Added Table 57 “Digital Config Register (Address 26)”.
Modified Table 58 “Transmit Control Register (Address 30)”.
Added Section 8.0, “Product Ordering Information”.
8
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
Revision 001
Revision Date: January 2001
Page
Description
Clock Requirements: Modified language under Clock Requirements heading.
N/A
Table 21 I/O Characteristics REFCLK: Changed values for Input Clock Duty Cycle under Min from
40 to 35 and under Max from 60 to 65.
Datasheet
9
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
10
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 1. LXT971A Block Diagram
RESET
VCC
Power Supply
GND
Management /
Mode Select
Logic
ADDR<4:0>
MDIO
PWRDWN
Register Set
REFCLK
Clock
MDC
Generator
MDINT
TxSLEW<1:0>
MDDIS
+
Manchester
Encoder
10
TX_EN
TXD<3:0>
TX_ER
TP
OSP™
Driver
TPFOP
TPFON
Pulse
Parallel/Serial
Converter
Scrambler
& Encoder
-
+
100
TP/Fiber
Out
Shaper
TX_CLK
ECL
Auto
Driver
Negotiation
-
TDIO
TMS
TCK
Register
Set
5
LED/CFG<3:1>
COL
JTAG
OSP™
TRST
Adaptive EQ with
Baseline Wander
Cancellation
+
Collision
Detect
Media
Select
Clock
100TX
100FX
10BT
Generator
-
RX_CLK
RXD<3:0>
RXDV
+
TPFIP
TPFIN
SD/TP
Manchester
Serial-to-
Parallel
TP/Fiber In
10
Decoder
OSP™
Slicer
-
Converter
Decoder &
Carrier Sense
100
CRS
Descrambler
+
Data Valid
Error Detect
RX_ER
-
Datasheet
11
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
1.0
Pin Assignments
Figure 2. LXT971A 64-Ball PBGA Assignments
1
2
3
4
5
6
7
8
A
B
C
D
E
F
MDINT
CRS
TXD3
TXD0
RX_ER VCCD RX_DV
RXD0
A
B
C
D
E
F
REF
RX_
COL
TXD2
GND
TX_EN TX_ER
N/C
N/C
RXD1
RXD2
MDIO
CLK/XI
CLK
TX_
TXD1
XO
Tx
RESET
Tx
GND
CLK
MDDIS
GND
GND
GND
GND
VCCA
VCCIO
VCCIO
TDI
RXD3
N/C
SLEW0 SLEW1
LED/
PWR
DWN
ADDR0 ADDR1
MDC
CFG1
LED/
LED/
ADDR3 ADDR2
ADDR4 SD/TP
GND
TMS
TCK
CFG2
CFG3
G
H
VCCA
TDO
GND
GND
G
H
RBIAS TPFOP TPFON TPFIP
TPFIN
5
TRST
6
SLEEP PAUSE
1
2
3
4
7
8
12
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 3. LXT971A 64-Pin LQFP Assignments
48 RXD0
1
2
3
4
5
6
7
REFCLK/XI
XO
MDDIS
RESET
TXSLEW0
TXSLEW1
GND
RXD1
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RXD2
RXD3
N/C
MDC
MDIO
GND
Part #
LOT #
FPO #
LXT971ALC XX
XXXXXX
Rev #
8
9
VCCIO
N/C
N/C
GND
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
VCCIO
PWRDWN
LED/CFG1
LED/CFG2
LED/CFG3
GND
XXXXXXXX
10
11
12
13
14
15
16
GND
PAUSE
Datasheet
13
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 1. LQFP Numeric Pin List
Reference for
Pin
Symbol
Type
Full Description
1
REFCLK/XI
XO
Input
Output
Input
Input
Input
Input
–
Table 4 on page 18
Table 4 on page 18
Table 2 on page 16
Table 4 on page 18
Table 4 on page 18
Table 4 on page 18
Table 5 on page 19
Table 5 on page 19
Table 4 on page 18
Table 4 on page 18
Table 5 on page 19
Table 4 on page 18
Table 4 on page 18
Table 4 on page 18
Table 4 on page 18
Table 4 on page 18
Table 4 on page 18
Table 5 on page 19
Table 3 on page 17
Table 3 on page 17
Table 5 on page 19
Table 5 on page 19
Table 3 on page 17
Table 3 on page 17
Table 5 on page 19
Table 3 on page 17
Table 6 on page 19
Table 6 on page 19
Table 6 on page 19
Table 6 on page 19
Table 6 on page 19
Table 4 on page 18
Table 4 on page 18
Table 5 on page 19
Table 5 on page 19
Table 7 on page 19
2
3
MDDIS
RESET
TxSLEW0
TxSLEW1
GND
4
5
6
7
8
VCCIO
N/C
–
9
–
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
N/C
–
GND
–
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
RBIAS
GND
Input
Input
Input
Input
Input
Analog Input
–
TPFOP
TPFON
VCCA
VCCA
TPFIP
TPFIN
GND
Output
Output
–
–
Input
Input
–
SD/TP
TDI
Input
Input
Output
Input
Input
Input
Input
Input
–
TDO
TMS
TCK
TRST
SLEEP
PAUSE
GND
GND
–
LED/CFG3
I/O
14
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 1. LQFP Numeric Pin List (Continued)
Reference for
Pin
Symbol
Type
Full Description
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
LED/CFG2
LED/CFG1
PWRDWN
VCCIO
GND
I/O
I/O
Table 7 on page 19
Table 7 on page 19
Table 4 on page 18
Table 5 on page 19
Table 5 on page 19
Table 2 on page 16
Table 2 on page 16
Table 4 on page 18
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 5 on page 19
Table 5 on page 19
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 5 on page 19
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Input
–
–
MDIO
I/O
MDC
Input
–
N/C
RXD3
Output
Output
Output
Output
Output
–
RXD2
RXD1
RXD0
RX_DV
GND
VCCD
RX_CLK
RX_ER
TX_ER
TX_CLK
TX_EN
TXD0
–
Output
Output
Input
Output
Input
Input
Input
Input
Input
–
TXD1
TXD2
TXD3
GND
COL
Output
Output
Open Drain
CRS
MDINT
Datasheet
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Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
2.0
Signal Descriptions
Note: Intel recommends that all inputs and multi-function pins be tied to the inactive states and all
outputs be left floating, if unused.
Table 2. LXT971A MII Signal Descriptions
PBGA LQFP
Symbol
Type1
Signal Description
Pin#
Pin#
Data Interface Pins
A3
B3
C4
A4
60
59
58
57
TXD3
Transmit Data. TXD is a bundle of parallel data signals that are
driven by the MAC. TXD<3:0> transitions synchronously with
respect to the TX_CLK. TXD<0> is the least significant bit.
TXD2
TXD1
TXD0
I
Transmit Enable. The MAC asserts this signal when it drives valid
B4
56
TX_EN
I
data on TXD. This signal must be synchronized to TX_CLK.
Transmit Clock. TX_CLK is sourced by the PHY in both 10 and
100 Mbps operations.
C5
55
TX_CLK
O
2.5 MHz for 10 Mbps operation, 25 MHz for 100 Mbps operation.
D6
C8
B8
A8
45
46
47
48
RXD3
RXD2
RXD1
RXD0
Receive Data. RXD is a bundle of parallel signals that transition
synchronously with respect to the RX_CLK. RXD<0> is the least
significant bit.
O
Receive Data Valid. The LXT971A asserts this signal when it drives
A7
A5
B5
49
53
54
RX_DV
RX_ER
TX_ER
O
O
I
valid data on RXD. This output is synchronous to RX_CLK.
Receive Error. Signals a receive error condition has occurred.
This output is synchronous to RX_CLK.
Transmit Error. Signals a transmit error condition. This signal must
be synchronized to TX_CLK.
Receive Clock. 25 MHz for 100 Mbps operation, 2.5 MHz for
10 Mbps operation. Refer to “Clock Requirements” on page 26 in
Section 3.0, “Functional Description”.
B6
B2
52
62
RX_CLK
COL
O
O
Collision Detected. The LXT971A asserts this output when a
collision is detected. This output remains High for the duration of the
collision. This signal is asynchronous and is inactive during full-
duplex operation.
Carrier Sense. During half-duplex operation (Register bit 0.8 = 0),
the LXT971A asserts this output when either transmitting or
receiving data packets. During full-duplex operation (Register bit 0.8
= 1), CRS is asserted only during receive. CRS assertion is
asynchronous with respect to RX_CLK. CRS is de-asserted on loss
of carrier, synchronous to RX_CLK.
A2
63
CRS
O
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
16
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 2. LXT971A MII Signal Descriptions (Continued)
PBGA LQFP
Symbol
Type1
Signal Description
Pin#
Pin#
MII Control Interface Pins
Management Disable. When MDDIS is High, the MDIO is disabled
from read and write operations.
When MDDIS is Low at power-up or reset, the Hardware Control
Interface pins control only the initial or “default” values of their
respective register bits. After the power-up/reset cycle is complete,
bit control reverts to the MDIO serial channel.
D3
3
MDDIS
I
Management Data Clock. Clock for the MDIO serial data channel.
E7
D8
43
42
MDC
I
Maximum frequency is 8 MHz.
Management Data Input/Output. Bidirectional serial data channel
MDIO
I/O
for PHY/STA communication.
Management Data Interrupt. When Register bit 18.1 = 1, an active
Low output on this pin indicates status change. Interrupt is cleared
by reading Register 19.
A1
64
MDINT
OD
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
Table 3. LXT971A Network Interface Signal Descriptions
PBGA
Pin#
LQFP
Pin#
Symbol
Type1
Signal Description
Twisted-Pair/Fiber Outputs, Positive & Negative.
During 100BASE-TX or 10BASE-T operation, TPFOP/N pins drive
H2
H3
19
20
TPFOP
TPFON
O
802.3 compliant pulses onto the line.
During 100BASE-FX operation, TPFOP/N pins produce differential
LVPECL outputs for fiber transceivers.
Twisted-Pair/Fiber Inputs, Positive & Negative.
During 100BASE-TX or 10BASE-T operation, TPFIP/N pins receive
H4
H5
23
24
TPFIP
TPFIN
I
I
differential 100BASE-TX or 10BASE-T signals from the line.
During 100BASE-FX operation, TPFIP/N pins receive differential
LVPECL inputs from fiber transceivers.
Signal Detect2: Dual function input depending on the state of the
device.
Reset and Power-Up. Media mode selection:
Tie High for FX mode (Register bit 16.0 = 1)
Tie Low for TP mode (Register bit 16.0 = 0)
G2
26
SD/TP
Normal Operation (FX Mode): SD input from the fiber transceiver.
Normal Operation (TP Mode): Tie to GND (uses an internal pull-
down).
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
2. For standard digital loopback testing (Register bit 0.14) in FX mode, the SD pin should be tied to an
LVPECL logic High (2.4 V).
Datasheet
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Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 4. LXT971A Miscellaneous Signal Descriptions
PBGA
Pin#
LQFP
Pin#
Symbol
Type1
Signal Description
Tx Output Slew Controls 0 and 1. These pins select the TX
output slew rate (rise and fall time) as follows:
TxSLEW1
TxSLEW0
Slew Rate (Rise and Fall Time)
TxSLEW0
TxSLEW1
D1
D2
5
6
0
0
1
1
0
1
0
1
3.0 ns
3.4 ns
3.9 ns
4.4 ns
I
Reset. This active Low input is OR’ed with the control
register Reset bit (Register bit 0.15). The LXT971A reset
cycle is extended to 258 µs (nominal) after reset is de-
asserted.
C2
4
RESET
I
16
15
14
13
12
G1
F1
F2
E2
E1
H1
H8
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
I
I
I
I
I
Address <4:0>. Sets device address.
Bias. This pin provides bias current for the internal circuitry.
Must be tied to ground through a 22.1 kΩ, 1% resistor.
17
33
RBIAS
AI
I
Pause. When set High, the LXT971A advertises Pause
PAUSE
capabilities during auto-negotiation.
Sleep. When set High, this pin enables the LXT971A to go
into a low-power sleep mode. The value of this pin can be
overridden by Register bit 16.6 when in managed mode.
H7
E8
32
39
SLEEP
I
I
Power Down. When set High, this pin puts the LXT971A in a
PWRDWN
power-down mode.
Crystal Input and Output. A 25 MHz crystal oscillator circuit
can be connected across XI and XO. A clock can also be
used at XI. Refer to “Clock Requirements” on page 26 in the
Functional Description section.
B1
C1
1
2
REFCLK/XI
XO
I
O
B7, C7
D7
9, 10
44
No Connection. These pins are not used and should not be
N/C
-
terminated.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
18
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 5. LXT971A Power Supply Signal Descriptions
PBGA
Pin#
LQFP
Pin#
Symbol
VCCD
Type
Signal Description
A6
51
–
Digital Power. Requires a 3.3V power supply.
D4, E3
E4, F3
F4, C6,
C3, G7,
G8
7, 11, 18,
25, 34,
35, 41,
50, 61
GND
–
Ground.
MII Power. Requires either a 3.3V or a 2.5V supply. Must
be supplied from the same source used to power the MAC
on the other side of the MII.
E5, D5
G3, G4
8, 40
VCCIO
VCCA
–
–
21, 22
Analog Power. Requires a 3.3V power supply.
Table 6. LXT971A JTAG Test Signal Descriptions
PBGA
Pin#
LQFP
Pin#
Symbol
TDI2
Type1
Signal Description
Test Data Input. Test data sampled with respect to the
F5
27
28
I
rising edge of TCK.
Test Data Output. Test data driven with respect to the
G5
TDO2
O
falling edge of TCK.
F6
G6
H6
29
30
31
TMS2
TCK2
TRST2
I
I
I
Test Mode Select.
Test Clock. Test clock input sourced by ATE.
Test Reset. Test reset input sourced by ATE.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
2. If JTAG port is not used, these pins do not need to be terminated.
Table 7. LXT971A LED Signal Descriptions
PBGA
LQFP
Symbol
Type1
Signal Description
Pin#
Pin#
LED Drivers 1-3. These pins drive LED indicators. Each
LED can display one of several available status
conditions as selected by the LED Configuration Register
(refer to Table 56 on page 85 for details).
Configuration Inputs 1-3. These pins also provide initial
configuration settings (refer to Table 9 on page 30 for
details).
E6
F7
F8
38
37
36
LED/CFG1
LED/CFG2
LED/CFG3
I/O
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
2. Pull-up/pull-down resistors of 10 k can be implemented if LEDs are used in the design.
Datasheet
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Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 8. LXT971A Pin Types and Modes
Tx/Rx
RXER
COL
CRS
TXD 0-3
Input
TXEN
Input
TXER
Input
Modes
RXD 0-3
RXDV
CLKS
Output Output Output
Output
HWReset
DL
DL
DH
DL
DL
DL
DL
DL
DL
IPLD
IPLD
IPLD
SFTPWRDN DL
DL
Active
High Z
IPLD
IPLD
IPLD
HWPWRDN
ISOLATE
SLEEP
High Z
High Z
High Z High Z High Z
High Z
High Z
High Z
HZ w/
IPLD
HZ w/
IPLD
HZ w/
IPLD
HZ w/
IPLD
HZ w/
IPLD
HZ w/
IPLD
IPLD
IPLD
IPLD
DL
DL
DL
DL
DL
DL
IPLD
IPLD
IPLD
1. A High Z (High impedance) or three-state determines when the device is drawing a current of less than
20 nA. A High Z with PLD (High impedance with pull-down) state determines when the device is drawing a
current of less than 20 µA.
2. DL = Driven Low (Logic 0), DH = Driven High (Logic 1), IPLD = Internal Pull-Down (Weak)
20
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.0
Functional Description
3.1
Introduction
The LXT971A is a single-port Fast Ethernet 10/100 transceiver that supports 10 Mbps and 100
Mbps networks and complies with all applicable requirements of IEEE 802.3. The LXT971A
directly drives either a 100BASE-TX line (up to 140 meters) or a 10BASE-T line (up to 185
meters). The device also supports 100BASE-FX operation via a Low Voltage PECL (LVPECL)
interface.
3.1.1
Comprehensive Functionality
The LXT971A provides a standard Media Independent Interface (MII) for 10/100 MACs. The
LXT971A performs all functions of the Physical Coding Sublayer (PCS) and Physical Media
Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X standard. This device also
performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX
connections.
The LXT971A reads its configuration pins on power-up to check for forced operation settings. If
not configured for forced operation, the device uses auto-negotiation/parallel detection to
automatically determine line operating conditions. If the PHY device on the other side of the link
supports auto-negotiation, the LXT971A auto-negotiates with it using Fast Link Pulse (FLP)
Bursts. If the PHY partner does not support auto-negotiation, the LXT971A automatically detects
the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and sets its
operating conditions accordingly.
The LXT971A provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps.
3.1.2
OSP™ Architecture
The LXT971A incorporates high-efficiency Optimal Signal Processing™ design techniques,
combining the best properties of digital and analog signal processing to produce a truly optimal
device.
The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by
as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques
in the receive equalizer avoids the quantization noise and calculation truncation errors found in
traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results
in improved receiver noise and cross-talk performance.
The OSP signal processing scheme also requires substantially less computational logic than
traditional DSP-based designs. This lowers power consumption and also reduces the logic
switching noise generated by DSP engines. This logic switching noise can be a considerable source
of EMI generated on the device’s power supplies.
The OSP-based LXT971A provides improved data recovery, EMI performance and low power
consumption.
Datasheet
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Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.2
Network Media / Protocol Support
The LXT971A supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or
100 Mbps Ethernet over fiber media (100BASE-FX).
3.2.1
10/100 Network Interface
The network interface port consists of five external pins (two differential signal pairs and a signal
detect pin). The I/O pins are shared between twisted-pair (TP) and fiber. Refer to Figure 3 on page
13 for specific pin assignments.
The LXT971A output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output.
When not transmitting data, the LXT971A generates 802.3-compliant link pulses or idle code.
Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input, depending
on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine
the speed of this interface.
3.2.1.1
Twisted-Pair Interface
The LXT971A supports either 100BASE-TX or 10BASE-T connections over 100Ω, Category 5,
Unshielded Twisted Pair (UTP) cable. When operating at 100 Mbps, the LXT971A continuously
transmits and receives MLT3 symbols. When not transmitting data, the LXT971A generates
“IDLE” symbols.
During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being
exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link
up.
Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete
this interface. On the transmit side, the LXT971A has an active internal termination and does not
require external termination resistors. Intel's patented waveshaping technology shapes the outgoing
signal to help reduce the need for external EMI filters. Four slew rate settings (refer to Table 4 on
page 18) allow the designer to match the output waveform to the magnetic characteristics. On the
receive side, the internal impedance is high enough that it has no practical effect on the external
termination circuit.
3.2.1.2
Fiber Interface
The LXT971A fiber port is designed to interface with common industry-standard fiber modules. It
incorporates a Low Voltage PECL interface that complies with the ANSI X3.166 standard for
seamless integration.
Fiber mode is selected through Register bit 16.0 by the following two methods:
1. Drive the SD input to a value greater than 600 mV during power-up and reset states (all
LVPECL signaling levels from a fiber transceiver are acceptable).
2. Configure Register bit 16.0 = 1 through the MDIO interface.
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Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.2.1.3
Fault Detection and Reporting
The LXT971A supports two fault detection and reporting mechanisms. “Remote Fault” refers to a
MAC-to-MAC communication function that is essentially transparent to PHY layer devices. It is
used only during auto-negotiation, and is applicable only to twisted-pair links. “Far-End Fault” is
an optional PMA-layer function that may be embedded within PHY devices. The LXT971A
supports both functions (see Section 3.2.1.3.1 and Section 3.2.1.3.2).
3.2.1.3.1 Remote Fault
Register bit 4.13 in the Auto-Negotiation Advertisement Register is reserved for Remote Fault
indications. It is typically used when re-starting the auto-negotiation sequence to indicate to the
link partner that the link is down because the advertising device detected a fault.
When the LXT971A receives a Remote Fault indication from its partner during auto-negotiation it
does the following:
• Sets Register bit 5.13 in the Link Partner Base Page Ability Register, and
• Sets the Remote Fault Register bit 1.4 in the MII Status Register to pass this information to the
local controller.
3.2.1.3.2 100BASE-FX Far-End Fault
The SD/TP pin monitors signal quality during normal operation in fiber mode. If the signal quality
degrades beyond the fault threshold, the fiber transceiver reports a signal quality fault condition via
the SD/TP pin. Loss of signal quality blocks any fiber data from being received and causes a link
loss.
If the LXT971A detects a signal fault condition, it can transmit the Far-End Fault Indication (FEFI)
over the fiber link. The FEFI consists of 84 consecutive ones followed by a single zero. This
pattern must be repeated at least three times. The LXT971A transmits the far-end fault code a
minimum of three times if all the following conditions are true:
• Fiber mode is selected.
• Fault Code transmission is enabled (Register bit 16.2 = 1).
• Either Signal Detect indicates no signal or the receive PLL cannot lock.
• Loopback is not enabled.
3.2.2
MII Data Interface
The LXT971A supports a standard Media Independent Interface (MII). The MII consists of a data
interface and a management interface. The MII Data Interface passes data between the LXT971A
and a Media Access Controller (MAC). Separate parallel buses are provided for transmit and
receive. This interface operates at either 10 Mbps or 100 Mbps. The speed is set automatically,
once the operating conditions of the network link have been determined. Refer to “MII Operation”
on page 32 for additional details.
3.2.2.1
Increased MII Drive Strength
A higher Media Independent Interface (MII) drive strength may be desired in some designs to drive
signals over longer PCB trace lengths, or over high-capacitive loads, through multiple vias, or
through a connector. The MII drive strength in the LXT971A can be increased by setting Register
Datasheet
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Document #: 249414
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
bit 26.11 through software control. Setting Register bit 26.11 = 1 through the MDC/MDIO
interface sets the MII pins (RXD[0:3], RX_DV, RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a
higher drive strength.
3.2.3
Configuration Management Interface
The LXT971A provides both an MDIO interface and a Hardware Control Interface for device
configuration and management.
3.2.3.1
MDIO Management Interface
The LXT971A supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT971A. The MDIO interface consists of a physical
connection, a specific protocol that runs across the connection, and an internal set of addressable
registers.
Some registers are required and their functions are defined by the IEEE 802.3 standard. The
LXT971A also supports additional registers for expanded functionality. The LXT971A supports
multiple internal registers, each of which is 16 bits wide. Specific register bits are referenced using
an “X.Y” notation, where X is the register number (0-31) and Y is the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write
operations are disabled and the Hardware Control Interface provides primary configuration control.
When MDDIS is Low, the MDIO port is enabled for both read and write operations and the
Hardware Control Interface is not used.
3.2.3.1.1 MDIO Addressing
The protocol allows one controller to communicate with multiple LXT971A chips. Pins
ADDR<4:0> determine the chip address.
3.2.3.1.2 MDIO Frame Structure
The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is
shown in Figures 4 and 5 (read and write). MDIO Interface timing is shown in Table 38 on
page 69.
Figure 4. Management Interface Read Frame Structure
MDC
MDIO
D0
A4
A3
A0
R4
R3
R0
D14 D1
D15
Z
0
32 "1"s
0
1
1
0
(Read)
Turn
Around
Data
Read
Idle
Preamble
ST
Op Code
PHY Address
Register Address
High Z
Write
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Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 5. Management Interface Write Frame Structure
MDC
MDIO
A4
A3
A0
R4
R3
R0
D15
D14
D1
D0
32 "1"s
0
1
0
1
0
1
(Write)
Turn
Around
Idle
Preamble
ST
Op Code
PHY Address
Register Address
Data
Idle
Write
3.2.3.1.3 MII Interrupts
The LXT971A provides a single interrupt pin (MDINT). Interrupt logic is shown in Figure 6. The
LXT971A also provides two dedicated interrupt registers. Register 18 provides interrupt enable
and mask functions and Register 19 provides interrupt status. Setting Register bit 18.1 = 1, enables
the device to request interrupt via the MDINT pin. An active Low on this pin indicates a status
change on the LXT971A. Interrupts may be caused by four conditions:
• Auto-negotiation complete
• Speed status change
• Duplex status change
• Link status change
3.2.3.2
Hardware Control Interface
The LXT971A provides a Hardware Control Interface for applications where the MDIO is not
desired. The Hardware Control Interface uses the three LED driver pins to set device configuration.
Refer to the Hardware Configuration Settings section on page 30 for additional details.
Figure 6. Interrupt Logic
Even X Mask Reg
Even X Status Reg
AND
OR
Interrupt Pin (MDINT)
NAND
Force Interrupt
Interrupt Enable
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Document #: 249414
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.3
Operating Requirements
3.3.1
Power Requirements
The LXT971A requires three power supply inputs (VCCD, VCCA, and VCCIO). The digital and
analog circuits require 3.3V supplies (VCCD and VCCA). These inputs may be supplied from a
single source. Each supply input must be de-coupled to ground.
An additional supply may be used for the MII (VCCIO). The supply may be either +2.5V or
+3.3V. Also, the inputs on the MII interface are tolerant to 5V signals from the controller on the
other side of the MII interface. Refer to Table 20 on page 57 for MII I/O characteristics.
As a matter of good practice, these supplies should be as clean as possible.
3.3.2
Clock Requirements
3.3.2.1
External Crystal/Oscillator
The LXT971A requires a reference clock input that is used to generate transmit signals and recover
receive signals. It may be provided by either of two methods: by connecting a crystal across the
oscillator pins (XI and XO), or by connecting an external clock source to pin XI. The connection of
a clock source to the XI pin requires the XO pin to be left open. A crystal-based clock is
recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to the
LXT971A/972A Design and Layout Guide for a list of recommended clock sources.
A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a
crystal, is frequently used in switch applications. Refer to Table 21 on page 57 for clock timing
requirements.
3.3.2.2
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock
(MDC) speed is a maximum of 8 MHz. Refer to Table 38 on page 69 for details.
3.4
Initialization
When the LXT971A is first powered on, reset, or encounters a link failure state, it checks the
MDIO register configuration bits to determine the line speed and operating conditions to use for
the network link. The configuration bits may be set by the Hardware Control or MDIO interface as
shown in Figure 7.
3.4.1
MDIO Control Mode
In the MDIO Control mode, the LXT971A reads the Hardware Control Interface pins to set the
initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to
the MDIO interface.
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Datasheet
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.4.2
Hardware Control Mode
In the Hardware Control Mode, LXT971A disables direct write operations to the MDIO registers
via the MDIO Interface. On power-up or hardware reset the LXT971A reads the Hardware Control
Interface pins and sets the MDIO registers accordingly.
The following modes are available using either Hardware Control or MDIO Control:
• Force network link to 100FX (Fiber).
• Force network link operation to:
— 100BASE-TX, Full-Duplex.
— 100BASE-TX, Half-Duplex.
— 10BASE-T, Full-Duplex.
— 10BASE-T, Half-Duplex.
• Allow auto-negotiation/parallel-detection.
When the network link is forced to a specific configuration, the LXT971A immediately begins
operating the network interface as commanded. When auto-negotiation is enabled, the LXT971A
begins the auto-negotiation/parallel-detection operation.
Datasheet
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Document #: 249414
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 7. Initialization Sequence
Power-up or Reset
Read H/W Control
Interface
Initialize MDIO Registers
MDIO Control
Mode
Hardware Control
Mode
MDDIS Voltage
Level?
Low
High
MDIO Controlled Operation
(MDIO Writes Enabled)
Disable MDIO Read and
Write Operations
No
Software
Reset?
Yes
Reset MDIO Registers to
values read at H/W
Control Interface at last
Hardware Reset
3.4.3
Reduced Power Modes
The LXT971A offers two power-down modes and a sleep mode.
3.4.3.1
Hardware Power Down
The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High,
the following conditions are true:
• The LXT971A network port and clock are shut down.
• All outputs are three-stated.
• All weak pad pull-up and pull-down resistors are disabled.
• The MDIO registers are not accessible.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.4.3.2
3.4.3.3
Software Power Down
Software power-down control is provided by Register bit 0.11 in the Control Register (refer to
Table 43 on page 74). During soft power-down, the following conditions are true:
• The network port is shut down.
• The MDIO registers remain accessible.
Sleep Mode
The LXT971A supports a power-saving sleep mode. Sleep mode is enabled when SLEEP is
asserted via pin 32(LQFP)/H7(PBGA). The value of pin 32/H7 can be overridden by Register bit
16.6 when in managed mode as shown in Table 4 on page 18. The LXT971A enters into sleep
mode when SLEEP is enabled and no energy is detected on the twisted-pair input for 1-3 seconds
(the time is controlled by Register bits 16.4:3 in the Configuration Register, with a default of 3.04
seconds).
During this mode, the LXT971A still responds to management transactions (MDC/MDIO). In this
mode the power consumption is minimized, and the supply current is reduced below the maximum
value given in Table 18 on page 56. If the LXT971A detects activity on the twisted-pair inputs, it
comes out of the sleep state and check for link. If no link is detected in 1-3 seconds
(programmable) it reverts back to the low power sleep state.
Note: Sleep Mode is not functional in fiber network applications.
3.4.4
Reset
The LXT971A provides both hardware and software resets. Configuration control of auto-
negotiation, speed, and duplex mode selection is handled differently for each. During a hardware
reset, auto-negotiation and speed configuration settings are read in from pins (refer to Table 9 on
page 30 for pin settings and to Table 43 on page 74 for register bit definitions).
During a software reset (0.15 = 1), these bit settings are not re-read from the pins. They revert back
to the values that were read in during the last hardware reset. Therefore, any changes to pin values
made since the last hardware reset is not detected during a software reset.
During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset.
During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be
polled to see when the part has completed reset (0.15 = 0).
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.4.5
Hardware Configuration Settings
The LXT971A provides a hardware option to set the initial device configuration. The hardware
option uses the three LED driver pins. This provides three control bits, as listed in Table 9. The
LED drivers can operate as either open-drain or open-source circuits as shown in Figure 8.
Figure 8. Hardware Configuration Settings
3.3 V
Configuration Bit = 1
Configuration Bit = 0
LED/CFG Pin
LED/CFG Pin
1. The LED/CFG pins automatically adjust their
polarity upon power-up or reset.
2. Unused LEDs may be implemented with pull-up/
pull-down resistors of 10 K.
Table 9. Hardware Configuration Settings
Resulting Register Bit Values
LED/CFGn
Desired Mode
Pin Settings1
Control Register
AN Advertisement Registers
Auto-
Auto-
Speed
(Mbps)
Speed
0.13
FD
0.8
100FD 100TX 10FD 10T
Duplex
1
2
3
Neg
0.12
Neg
4.8
4.7
4.6
4.5
Half
Full
Half
Full
Half
Full
Low Low Low
Low Low High
Low High Low
Low High High
High Low Low
High Low High
0
1
0
1
0
1
10
0
1
N/A
Disabled
0
1
Auto-Negotiation Adver-
tisement
100
0
1
1
1
0
0
0
0
100
Only
Half
Enabled
1
High High Low
High High High
0
1
0
1
1
1
0
1
1
1
Only
10/100
Full or
Half
1. Refer to Table 7 on page 19 for LED/CFG pin assignments.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.5
Establishing Link
See Figure 9 for an overview of link establishment.
3.5.1
Auto-Negotiation
If not configured for forced operation, the LXT971A attempts to auto-negotiate with its link
partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of up to 33 link pulses spaced
62.5 µs apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may
be present or absent to indicate a “1” or a “0”. Each FLP burst exchanges 16 bits of data, which are
referred to as a “link code word”. All devices that support auto-negotiation must implement the
“Base Page” defined by IEEE 802.3 (registers 4 and 5). LXT971A also supports the optional “Next
Page” function as described in Tables 50 and 51 on page 80 (registers 7 and 8).
3.5.1.1
Base Page Exchange
By exchanging Base Pages, the LXT971A and its link partner communicate their capabilities to
each other. Both sides must receive at least three identical base pages for negotiation to continue.
Each side identifies the highest common capabilities that both sides support and configures itself
accordingly.
3.5.1.2
3.5.1.3
Next Page Exchange
Additional information, above that required by base page exchange is also sent via “Next Pages”.
The LXT971A fully supports the IEEE 802.3ab method of negotiation via Next Page exchange.
Controlling Auto-Negotiation
When auto-negotiation is controlled by software, the following steps are recommended:
• After power-up, power-down, or reset, the power-down recovery time, as specified in Table 40
on page 70, must be exhausted before proceeding.
• Set the Auto-Negotiation Advertisement Register bits.
• Enable auto-negotiation (set MDIO Register bit 0.12 = 1).
3.5.2
Parallel Detection
For the parallel detection feature of auto-negotiation, the LXT971A also monitors for 10BASE-T
Normal Link Pulses (NLP) and 100BASE-TX Idle symbols. If either is detected, the device
automatically reverts to the corresponding operating mode. Parallel detection allows the LXT971A
to communicate with devices that do not support auto-negotiation.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 9. Link Establishment Overview
Power-Up, Reset,
Waking up from
Sleep mode, or
Link Failure
Start
Disable
Enable
0.12 = 0
0.12 = 1
Auto-Negotiation
Auto-Neg/Parallel Detection
Check Value
0.12
Go To Forced
Settings
Attempt Auto-
Negotiation
Listen for 100TX
Idle Symbols
Listen for 10T
Link Pulses
YES
NO
Done
Link Up?
3.6
MII Operation
The LXT971A device implements the Media Independent Interface (MII) as defined in the IEEE
802.3 standard. Separate channels are provided for transmitting data from the MAC to the
LXT971A (TXD), and for passing data received from the line (RXD) to the MAC. Each channel
has its own clock, data bus, and control signals. Nine signals are used to pass received data to the
MAC: RXD<3:0>, RX_CLK, RX_DV, RX_ER, COL, and CRS. Seven signals are used to transmit
data from the MAC: TXD<3:0>, TX_CLK, TX_EN, and TX_ER.
The LXT971A supplies both clock signals as well as separate outputs for carrier sense and
collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles.
3.6.1
MII Clocks
The LXT971A is the master clock source for data transmission and supplies both MII clocks
(RX_CLK and TX_CLK). It automatically sets the clock speeds to match link conditions. When
the link is operating at 100 Mbps, the clocks are set to 25 MHz. When the link is operating at 10
Mbps, the clocks are set to 2.5 MHz. Figures 10 through 12 show the clock cycles for each mode.
The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The
LXT971A samples these signals on the rising edge of TX_CLK.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.6.2
3.6.3
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN
after the last bit of the packet.
Receive Data Valid
The LXT971A asserts RX_DV when it receives a valid packet. Timing changes depend on line
operating speed:
• For 100BASE-TX links, RX_DV is asserted from the first nibble of preamble to the last nibble
of the data packet.
• For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the
Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.
3.6.4
Carrier Sense
Carrier Sense (CRS) is an asynchronous output. It is always generated when a packet is received
from the line and in half-duplex mode when a packet is transmitted. Table 10 summarizes the
conditions for assertion of carrier sense, collision, and data loopback signals.
Carrier sense is not generated when a packet is transmitted and in full-duplex mode.
3.6.5
3.6.6
Error Signals
When LXT971A is in 100 Mbps mode and receives an invalid symbol from the network, it asserts
RX_ER and drives “1110” on the RXD pins.
When the MAC asserts TX_ER, the LXT971A drives “H” symbols out on the TPFOP/N pins.
Collision
The LXT971A asserts its collision signal, asynchronously to any clock, whenever the line state is
half-duplex and the transmitter and receiver are active at the same time. Table 10 summarizes the
conditions for assertion of carrier sense, collision, and data loopback signals.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 10. 10BASE-T Clocking
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
TX_CLK
(Sourced by LXT971A)
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
RX_CLK
(Sourced by LXT971A)
Constant 25 MHz
XI
Figure 11. 100BASE-X Clocking
25 MHz once 100BASE-X
2.5 MHz during auto-negotiation
2.5 MHz during auto-negotiation
Link Established
TX_CLK
(Sourced by LXT971A)
25 MHz once 100BASE-X
Link Established
RX_CLK
(Sourced by LXT971A)
Constant 25 MHz
XI
Figure 12. Link Down Clock Transition
Link-Down Condition/Auto-Negotiate Enabled
2.5 MHz Clock
RX_CLK
TX_CLK
Any Clock
Clock transition time will not exceed
2X the nominal clock period:
10 Mbps = 2.5 MHz
100 Mbps = 25 MHz
3.6.7
Loopback
The LXT971A provides two loopback functions, operational and test (see Table 10). Loopback
paths are shown in Figure 13.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.6.7.1
3.6.7.2
Operational Loopback
Operational loopback is provided for 10 Mbps half-duplex links when Register bit 16.8 = 0. Data
transmitted by the MAC (TXData) is looped back on the receive side of the MII (RXData).
Operational loopback is not provided for 100 Mbps links, full-duplex links, or when 16.8 = 1.
Test Loopback
A test loopback function is provided for diagnostic testing of the LXT971A. During test loopback,
twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped
back by the LXT971A and returned to the MAC.
Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled by
setting the following register bits:
• Register bit 0.14 = 1
• Register bit 0.8 = 1 (full-duplex)
• Register bit 0.12 = 0 (disable auto-negotiation).
Test loopback is also available for 100BASE-FX operation. Test loopback in this mode is enabled
by setting Register bit 0.14 = 1 and tying the SD input to an LVPECL logic High value (2.4 V).
Figure 13. Loopback Paths
LXT971A
FX Driver
TX Driver
10T
Loopback
Digital
Block
100X
Analog
Block
MII
Loopback
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 10. Carrier Sense, Loopback, and Collision Conditions
Test1
Operational
Loopback
Speed
Duplex Condition
Carrier Sense
Collision
Loopback
Full-Duplex
Half-Duplex
Full-Duplex
Half-Duplex,
Receive Only
Yes
No
No
No
No
None
100 Mbps
Transmit or Receive
Receive Only
Transmit and Receive
None
Yes
Transmit or Receive
Transmit or Receive
Yes
No
Yes
No
Transmit and Receive
Transmit and Receive
10 Mbps Register bit 16.8 = 0
Half-Duplex,
Register bit 16.8 = 1
1. Test Loopback is enabled when 0.14 = 1
3.7
100 Mbps Operation
3.7.1
100BASE-X Network Operations
During 100BASE-X operation, the LXT971A transmits and receives 5-bit symbols across the
network link. Figure 14 shows the structure of a standard frame packet. When the MAC is not
actively transmitting data, the LXT971A sends out Idle symbols on the line.
In 100BASE-TX mode, the LXT971A scrambles and transmits the data to the network using MLT-
3 line code (Figure 15 on page 37). MLT-3 signals received from the network are de-scrambled,
decoded, and sent across the MII to the MAC.
In 100BASE-FX mode, the LXT971A transmits and receives NRZI signals across the LVPECL
interface. An external 100FX transceiver module is required to complete the fiber connection. To
enable 100BASE-FX operation, auto-negotiation must be disabled and FX selected.
Figure 14. 100BASE-X Frame Format
64-Bit Preamble
Destination and Source
Address (6 Octets each)
Packet Length
(2 Octets)
Data Field
Frame Check Field InterFrame Gap / Idle Code
(8 Octets)
(Pad to minimum packet size)
(4 Octets)
(> 12 Octets)
CRC
IFG
SFD
P0 P1 P6
DA DA SA SA L1
L2
D0 D1 Dn
I0
Replaced by
Replaced by
Start-of-Frame
Delimiter (SFD)
/T/R/ code-groups
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
End-of-Stream Delimiter (ESD)
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 15. 100BASE-TX Data Path
Standard Data Flow
+1
Parallel
D0
to
0
0
0
Serial
D1
Scramble
-1
4B/5B
MLT3
D0 D1 D2 D3
S0 S1 S2 S3 S4
De-
D2
D3
Transition = 1.
Serial
to
Scramble
No Transition = 0.
All transitions must follow
Parallel
pattern: 0, +1, 0, -1, 0, +1...
Scrambler Bypass Data Flow
S0
+1
Parallel
to
S1
0
0
0
Serial
-1
MLT3
S2
S0 S1 S2 S3 S4
Transition = 1.
Serial
S3
to
No Transition = 0.
All transitions must follow
Parallel
S4
pattern: 0, +1, 0, -1, 0, +1...
As shown in Figure 14 on page 36, the MAC starts each transmission with a preamble pattern. As
soon as the LXT971A detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD,
symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the
balance of the preamble, the SFD, packet data, and CRC.
Once the packet ends, the LXT971A transmits the End-of- Stream Delimiter (ESD, symbols T and
R) and then returns to transmitting Idle symbols. 4B/5B coding is shown in Table 11 on page 40.
Figure 16 shows normal reception with no errors. When the LXT971A receives invalid symbols
from the line, it asserts RX_ER as shown in Figure 17.
Figure 16. 100BASE-TX Reception with No Errors
RX_CLK
RX_DV
preamble SFD SFD DA DA DA DA
CRC
CRC
CRC
CRC
RXD<3:0>
RX_ER
Figure 17. 100BASE-TX Reception with Invalid Symbol
RX_CLK
RX_DV
preamble SFD SFD DA DA XX XX XX XX XX XX XX XX XX XX
RXD<3:0>
RX_ER
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.7.2
Collision Indication
Figure 18 shows normal transmission. Upon detection of a collision, the COL output is asserted
and remains asserted for the duration of the collision as shown in Figure 19.
Figure 18. 100BASE-TX Transmission with No Errors
TX_CLK
TX_EN
TXD<3:0>
CRS
P
R
E
A
M
B
L
E
DA DA DA DA DA DA DA DA DA
COL
Figure 19. 100BASE-TX Transmission with Collision
TX_CLK
TX_EN
TXD<3:0>
CRS
P
R
E
A
M
B
L
E
JAM
JAM
JAM
JAM
COL
3.7.3
100BASE-X Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT971A is a Physical Layer 1 (PHY)
device. The LXT971A implements the Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model
defined by the IEEE 802.3u standard. The following paragraphs discuss LXT971A operation from
the reference model point of view.
3.7.3.1
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/
decoding function.
For 100BASE-TX and 100FX operation, the PCS layer provides IDLE symbols to the PMD-layer
line driver as long as TX_EN is de-asserted.
3.7.3.1.1 Preamble Handling
When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-of-
Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues
to encode the remaining MII data, following the coding in Table 11, until TX_EN is de-asserted. It
then returns to supplying IDLE symbols to the line driver.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
In the receive direction, the PCS layer performs the opposite function, substituting two preamble
nibbles for the SSD.
3.7.3.1.2 Dribble Bits
The LXT971A handles dribbles bits in all modes. If one to four dribble bits are received, the nibble
is passed across the MII, and padded with ones if necessary. If five to seven dribble bits are
received, the second nibble is not sent to the MII bus.
Figure 20. Protocol Sublayers
MII Interface
LXT971A
PCS
Encoder/Decoder
Sublayer
Serializer/De-serializer
PMA
Link/Carrier Detect
Sublayer
PECL Interface
PMD
Scrambler/
De-scrambler
Fiber Transceiver
Sublayer
100BASE-TX
100BASE-FX
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 11. 4B/5B Coding
4B Code
5B Code
4 3 2 1 0
Code Type
Name
Interpretation
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
undefined
0
1
1 1 1 1 0
0 1 0 0 1
1 0 1 0 0
1 0 1 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 1 0
0 1 1 1 1
1 0 0 1 0
1 0 0 1 1
1 0 1 1 0
1 0 1 1 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 11
Data 0
Data 1
2
Data 2
3
Data 3
4
Data 4
5
Data 5
6
Data 6
7
Data 7
DATA
8
Data 8
9
Data 9
A
B
C
D
E
F
I 1
Data A
Data B
Data C
Data D
Data E
Data F
IDLE
Used as inter-stream fill code
Start-of-Stream Delimiter (SSD),
part 1 of 2
0 1 0 1
0 1 0 1
J 2
K 2
T 3
R 3
1 1 0 0 0
1 0 0 0 1
0 1 1 0 1
0 0 1 1 1
Start-of-Stream Delimiter (SSD),
part 2 of 2
CONTROL
End-of-Stream Delimiter (ESD),
part 1 of 2
undefined
undefined
End-of-Stream Delimiter (ESD),
part 2 of 2
1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 11. 4B/5B Coding (Continued)
4B Code
Code Type
5B Code
Name
Interpretation
3 2 1 0
4 3 2 1 0
Transmit Error. Used to force signaling
errors
undefined
H 4
0 0 1 0 0
undefined
undefined
undefined
undefined
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 1 0 0 1
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
INVALID
undefined
undefined
undefined
undefined
undefined
undefined
1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
3.7.3.2
PMA Sublayer
3.7.3.2.1 Link
In 100 Mbps mode, the LXT971A establishes a link whenever the scrambler becomes locked and
remains locked for approximately 50 ms. Whenever the scrambler loses lock (receiving less than
12 consecutive idle symbols during a 2 ms window), the link is taken down. This provides a very
robust link, essentially filtering out any small noise hits that may otherwise disrupt the link.
Furthermore, 100 Mbps idle patterns will not bring up a 10 Mbps link.
The LXT971A reports link failure via the MII status bits (Register bits 1.2 and 17.10) and interrupt
functions. Link failure causes the LXT971A to re-negotiate if auto-negotiation is enabled.
3.7.3.2.2 Link Failure Override
The LXT971A normally transmits data packets only if it detects the link is up. Setting Register bit
16.14 = 1 overrides this function, allowing the LXT971A to transmit data packets even when the
link is down. This feature is provided as a diagnostic tool. Note that auto-negotiation must be
disabled to transmit data packets in the absence of link. If auto-negotiation is enabled, the
LXT971A automatically transmits FLP bursts if the link is down.
3.7.3.2.3 Carrier Sense
For 100BASE-TX and 100FX links, a start-of-stream delimiter (SSD) or /J/K symbol pair causes
assertion of carrier sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes de-
assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R;
however, in this case RX_ER is asserted for one clock cycle when CRS is de-asserted.
Usage of CRS for Interframe Gap (IFG) timing is not recommended for the following reasons:
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
• De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to
appear somewhat shorter to the MAC than it actually is on the wire.
• CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-
duplex mode.
3.7.3.2.4 Receive Data Valid
The LXT971A asserts RX_DV to indicate that the received data maps to valid symbols. However,
RXD outputs zeros until the received data is decoded and available for transfer to the controller.
3.7.3.3
Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and de-
scrambling, line coding and decoding (MLT-3 for 100BASE-TX, Manchester for 10BASE-T), as
well as receiving, polarity correction, and baseline wander correction functions.
Scrambler/De-scrambler
The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using
an 11-bit, data-independent polynomial. The receiver automatically decodes the polynomial
whenever IDLE symbols are received.
Scrambler Seeding
Once the transmit data (or Idle symbols) are properly encoded, they are scrambled to further reduce
EMI and to spread the power spectrum using an 11-bit scrambler seed. Five seed bits are
determined by the PHY address, and the remaining bits are hard coded in the design.
Scrambler Bypass
The scrambler/de-scrambler can be bypassed by setting Register bit 16.12 = 1. The scrambler is
automatically bypassed when the fiber port is enabled. Scrambler bypass is provided for diagnostic
and test support.
3.7.3.3.1 Baseline Wander Correction
The LXT971A provides a baseline wander correction function which makes the device robust
under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by
definition “unbalanced”. This means that the average value of the signal voltage can “wander”
significantly over short time intervals (tenths of seconds). This wander can cause receiver errors at
long-line lengths (100 meters) in less robust designs. Exact characteristics of the wander are
completely data dependent.
The LXT971A baseline wander correction characteristics allow the device to recover error-free
data while receiving worst-case “killer” packets over all cable lengths.
3.7.3.3.2 Polarity Correction
The 100BASE-TX de-scrambler automatically detects and corrects for the condition where the
receive signal at TPFIP and TPFIN is inverted.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.7.3.3.3 Programmable Slew Rate Control
The LXT971A device supports a slew rate mechanism whereby one of four pre-selected slew rates
can be used. This allows the designer to optimize the output waveform to match the characteristics
of the magnetics. The slew rate is determined by the TxSLEW pins as shown in Table 4 on
page 18.
3.7.3.4
Fiber PMD Sublayer
The LXT971A provides a Low Voltage PECL interface for connection to an external 3.3 V or 5.0 V
fiber-optic transceiver. (The external transceiver provides the PMD function for fiber media.) The
LXT971A uses an NRZI format for the fiber interface. The fiber interface operates at 100 Mbps
and does not support 10FL applications.
3.8
10 Mbps Operation
The LXT971A operates as a standard 10BASE-T transceiver. The LXT971A supports all the
standard 10 Mbps functions. During 10BASE-T operation, the LXT971A transmits and receives
Manchester-encoded data across the network link. When the MAC is not actively transmitting data,
the LXT971A drives link pulses onto the line.
In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded
signals received from the network are decoded by the LXT971A and sent across the MII to the
MAC.
The LXT971A does not support fiber connections at 10 Mbps.
3.8.1
10BASE-T Preamble Handling
The LXT971A offers two options for preamble handling, selected by Register bit 16.5. In
10BASE-T Mode when 16.5 = 0, the LXT971A strips the entire preamble off of received packets.
CRS is asserted coincident with SFD. RX_DV is held Low for the duration of the preamble. When
RX_DV is asserted, the very first two nibbles driven by the LXT971A are the SFD “5D” hex
followed by the body of the packet.
In 10BASE-T mode with 16.5 = 1, the LXT971A passes the preamble through the MII and asserts
RX_DV and CRS simultaneously. In 10BASE-T loopback, the LXT971A loops back whatever the
MAC transmits to it, including the preamble.
3.8.2
3.8.3
10BASE-T Carrier Sense
For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on
reception of an end-of-frame (EOF) marker. Register bit 16.7 allows CRS de-assertion to be
synchronized with RX_DV de-assertion. Refer to Table 52 on page 81.
10BASE-T Dribble Bits
The LXT971A device handles dribbles bits in all modes. If one to four dribble bits are received, the
nibble is passed across the MII, padded with ones if necessary. If five to seven dribble bits are
received, the second nibble is not sent to the MII bus.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.8.4
10BASE-T Link Integrity Test
In 10BASE-T mode, the LXT971A always transmits link pulses. When the Link Integrity Test
function is enabled (the normal configuration), it monitors the connection for link pulses. Once link
pulses are detected, data transmission is enabled and remains enabled as long as either the link
pulses or data transmission continue. If the link pulses stop, the data transmission is disabled.
If the Link Integrity Test function is disabled, the LXT971A transmits to the connection regardless
of detected link pulses. The Link Integrity Test function can be disabled by setting Register bit
16.14 = 1.
3.8.4.1
3.8.5
3.8.6
Link Failure
Link failure occurs if the Link Integrity Test is enabled and link pulses or packets stop being
received. If this condition occurs, the LXT971A returns to the auto-negotiation phase if auto-
negotiation is enabled. If the Link Integrity Test function is disabled by setting Register bit
16.14 = 1 in the Configuration Register, the LXT971A transmits packets, regardless of link status.
10BASE-T SQE (Heartbeat)
By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT971A. To
enable this function, set Register bit 16.9 = 1. When this function is enabled, the LXT971A asserts
its COL output for 5-15 BT after each packet. See Figure 35 on page 67 for SQE timing
parameters.
10BASE-T Jabber
If a transmission exceeds the jabber timer, the LXT971A disables the transmit and loopback
functions. See Figure 34 on page 67 for jabber timing parameters.
The LXT971A automatically exits jabber mode after the unjabber time has expired. This function
can be disabled by setting Register bit 16.10 = 1.
3.8.7
10BASE-T Polarity Correction
The LXT971A automatically detects and corrects for the condition where the receive signal
(TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted
end-of-frame (EOF) markers, are received consecutively. If link pulses or data are not received by
the maximum receive time-out period (96-128 ms), the polarity state is reset to a non-inverted
state.
3.9
Monitoring Operations
3.9.1
Monitoring Auto-Negotiation
Auto-negotiation can be monitored as follows:
• Register bit 17.7 is set to 1 once the auto-negotiation process is completed.
• Register bits 1.2 and 17.10 are set to 1 once the link is established.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
• Register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and
duplex).
3.9.1.1
3.9.2
Monitoring Next Page Exchange
The LXT971A offers an Alternate Next Page mode to simplify the next page exchange process.
Normally, Register bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode
is enabled Register bit 6.1 is automatically cleared whenever a new negotiation process takes place.
This prevents the user from reading an old value in 6.1 and assuming that Registers 5 and 8
(Partner Ability) contain valid information. Additionally, the LXT971A uses Register bit 6.5 to
indicate when the current received page is the base page. This information is useful for recognizing
when next pages must be resent due to a new negotiation process starting. Register bits 6.1 and 6.5
are cleared when read.
LED Functions
The LXT971A incorporates three direct LED drivers. On power up all the drivers are asserted for
approximately 1 second after reset de-asserts. Each LED driver can be programmed using the LED
Configuration Register (refer to Table 56 on page 85) to indicate one of the following conditions:
• Operating Speed
• Transmit Activity
• Receive Activity
• Collision Condition
• Link Status
• Duplex Mode
The LED drivers can also be programmed to display various combined status conditions. For
example, setting Register bits 20.15:12 = 1101 produces the following combination of Link and
Activity indications:
• If Link is down LED is off.
• If Link is up LED is on.
• If Link is up and activity is detected, the LED blinks at the stretch interval selected by Register
bits 20.3:2 and continues to blink as long as activity is present.
The LED driver pins also provide initial configuration settings. The LED pins are sensitive to
polarity and automatically pull up or pull down to configure for either open drain or open collector
circuits (10 mA Max current rating) as required by the hardware configuration. Refer to the
discussion of “Hardware Configuration Settings” on page 30 for details.
3.9.2.1
LED Pulse Stretching
The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms.
The pulse stretch time is further extended if the event occurs again during this pulse stretch period.
When an event such as receiving a packet occurs it is edge detected and it starts the stretch timer.
The LED driver remains asserted until the stretch timer expires. If another event occurs before the
stretch timer expires then the stretch timer is reset and the stretch time is extended.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
When a long event (such as duplex status) occurs it is edge detected and it starts the stretch timer.
When the stretch timer expires the edge detector is reset so that a long event causes another pulse to
be generated from the edge detector which resets the stretch timer and causes the LED driver to
remain asserted. Figure 21 shows how the stretch operation functions.
Figure 21. LED Pulse Stretching
Event
LED
stretch
stretch
stretch
Note: The direct drive LED outputs in this diagram are shown as activeLow.
3.10
Boundary Scan (JTAG1149.1) Functions
LXT971A includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input,
output, and input/output pins are accessible. The BSDL file is available by contacting your local
sales office or by accessing the Intel website (www.intel.com).
3.10.1
3.10.2
3.10.3
3.10.4
Boundary Scan Interface
This interface consists of five pins (TMS, TDI, TDO, TRST, and TCK). It includes a state machine,
data register array, and instruction register. The TMS and TDI pins are internally pulled up. TCK is
internally pulled down. TDO does not have an internal pull-up or pull-down.
State Machine
The TAP controller is a 16 state machine driven by the TCK and TMS pins. Upon reset the
TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are
high for five TCK periods.
Instruction Register
After the state machine resets, the IDCODE instruction is always invoked. The decode logic
ensures the correct data flow to the Data registers according to the current instruction. Valid
instructions are listed in Table 13.
Boundary Scan Register (BSR)
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the
serial shift stage and the parallel output stage. There are four modes of operation as listed in
Table 12.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 12. BSR Mode of Operation
Mode
Description
1
2
3
4
Capture
Shift
Update
System Function
Table 13. Supported JTAG Instructions
Name
EXTEST
Code
Description
External Test
Mode
Data Register
BSR
1111 1111 1110 1000
1111 1111 1111 1110
1111 1111 1111 1000
1111 1111 1100 1111
1111 1111 1110 1111
1111 1111 1111 1111
Test
IDCODE
SAMPLE
HIGHZ
ID Code Inspection
Sample Boundary
Force Float
Normal
Normal
Normal
Test
ID REG
BSR
Bypass
Bypass
Bypass
CLAMP
BYPASS
Control Boundary to 1/0
Bypass Scan
Normal
Table 14. Device ID Register
31:28
27:12
11:8
7:1
0
Version2
Part ID (hex)
Jedec Continuation Characters
JEDEC ID1
Reserved
XXXX
03CB
0000
111 1110
1
1. The JEDEC IS is an 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC ID is FE
(1111 1110), which becomes 111 1110.
2. See the LXT971A/972A Specification Update (document number 249354) for the current version of the
Jedec continuation characters.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
4.0
Application Information
4.1
Magnetics Information
The LXT971A requires a 1:1 ratio for both the receive and transmit transformers. The transformer
isolation voltage should be rated at 2 kV to protect the circuitry from static voltages across the
connectors and cables. Refer to Table 15 for transformer requirements.
A cross-reference list of magnetic manufacturers and part numbers is available in Magnetic
Manufacturers for Networking Product Applications (document number 248991) and is found on
the Intel web site (www.Intel.com). Before committing to a specific component, contact the
manufacturer for current product specifications and validate the magnetics for the specific
application.
Table 15. Magnetics Requirements
Parameter
Min
Nom
Max
Units
Test Condition
Rx turns ratio
–
–
1 : 1
1 : 1
0.6
–
–
–
–
–
Tx turns ratio
–
–
Insertion loss
0.0
350
–
1.1
–
dB
µH
kV
dB
dB
dB
dB
–
–
Primary inductance
Transformer isolation
1.5
–
–
–
40
35
-16
-10
–
.1 to 60 MHz
60 to 100 MHz
30 MHz
80 MHz
Differential to common mode rejection
Return Loss
–
–
–
–
–
–
4.2
Typical Twisted-Pair Interface
Table 16 provides a comparison of the RJ-45 connections for NIC and Switch applications in a
typical twisted-pair interface setting.
Table 16. I/O Pin Comparison of NIC and Switch RJ-45 Setups
RJ-45
Symbol
Switch
NIC
TPIP
TPIN
1
2
3
6
3
6
1
2
TPOP
TPON
Figure 22 on page 49 shows a typical twisted-pair interface with the RJ-45 connections crossed
over for a Switch configuration. Figure 23 on page 50 provides a typical twisted-pair interface with
the RJ-45 connections configured for a NIC application.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 22. Typical Twisted-Pair Interface - Switch
270 pF 5%
TPFIP
RJ-45
50Ω 1%
1:1
1:1
1
2
3
4
5
6
7
8
0.01 µF
3
50Ω 1%
270 pF 5%
2
TPFIN
50
50
Ω
50
50
Ω
Ω
TPFOP
LXT971A
50
50
Ω
Ω
0.1µF
Ω
TPFON
1
* = 0.001 µF / 2.0 kV
*
*
4
VCCA
GND
.01µF
0.1µF
SD/TP
1. Center-tap current may be supplied from 3.3 V VCCA as shown. Additional power savings
may be realized by supplying the center-tap from a 2.5 V current source. A separate ferrite
bead (rated at 50 mA) should be used to supply center-tap current.
2. The 100 Ω transmit load termination resistor typically required is integrated in the
LXT971A.
3. Magnetics without a receive pair center-tap do not require a 2 kV termination.
4. RJ-45 connections shown are for a standard switch application. For a standard NIC RJ-45
setup, see Figure 23 on page 50.
Datasheet
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Document #: 249414
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 23. Typical Twisted-Pair Interface - NIC
RJ-45
50
50
Ω
50
50
Ω
Ω
270 pF 5%
TPFIN
8
7
6
5
4
3
2
1
50Ω 1%
1:1
1:1
50
50
Ω
Ω
0.01 µF
50Ω 1%
3
Ω
TPFIP
270 pF 5%
TPFON
LXT971A
2
0.1µF
4
TPFOP
1
* = 0.001 µF / 2.0 kV
*
*
VCCA
GND
.01µF
0.1µF
SD/TP
1. Center-tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may
be realized by supplying the center-tap from a 2.5 V current source. A separate ferrite bead
(rated at 50 mA) should be used to supply center-tap current.
2. The 100 Ω transmit load termination resistor typically required is integrated in the LXT971A.
3. Magnetics without a receive pair center-tap do not require a 2 kV termination.
4. RJ-45 connections shown for standard NIC. TX/RX crossover may be required for repeater and
switch applications.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 24. Typical MII Interface
TX_EN
TX_ER
TXD<3:0>
TX_CLK
RX_CLK
X
F
RX_DV
MAC
LXT971A
RJ-45
RX_ER
M
R
RXD<3:0>
CRS
COL
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
4.3
The Fiber Interface
The fiber interface consists of an LVPECL transmit and receive pair to an external fiber-optic
transceiver. Both 3.3 V fiber-optic transceivers and 5 V fiber-optic transceivers can be used with
the LXT971A.
The following should occur in 3.3 V fiber transceiver applications as shown in Figure 25:
• The transmit pair should be DC-coupled with the 50 Ω/16 Ω pull-up combination
• The receive pair should be DC-coupled with an emitter current path for the fiber transceiver
• The signal detect pin should be DC-coupled with an emitter current path for the fiber
transceiver
Refer to the fiber transceiver manufacturer’s recommendations for termination circuitry. Figure 25
shows a typical example of an LXT971A-to-3.3 V fiber transceiver interface.
The following occurs in 5 V fiber transceiver applications as shown in Figure 26:
• The transmit pair should be AC-coupled and re-biased to 5 V PECL input levels
• The receive pair should be AC-coupled with an emitter current path for the fiber transceiver
and re-biased to 3.3 V LVPECL input levels.
The signal detect pin on a 5 V fiber transceiver interface should use the logic translator circuitry as
shown in Figure 27. Refer to the fiber transceiver manufacturer’s recommendations for termination
circuitry. Figure 26 shows a typical example of an LXT971A-to-5 V fiber transceiver interface,
while Figure 27 shows the interface circuitry for the logic translator.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 25. Typical LXT971A-to-3.3 V Fiber Transceiver Interface Circuitry
+3.3V
+3.3V
16Ω
0.01µF − 0.1µ F
50Ω
50Ω
TPFON
TPFOP
TD -
TD +
Fiber Txcvr
LXT971A
+3.3V
130Ω
SD/TP
SD
82Ω
+3.3V
1
0.01µF
130Ω
130Ω
− 0.1µ F
RD -
TPFIN
TPFIP
RD +
82Ω
82Ω
1. Refer to the transceiver manufacturer’s recommendations for termination circuitry.
Datasheet
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 26. Typical LXT971A-to-5 V Fiber Transceiver Interface Circuitry
+5V
+3.3V
+3.3V
0.01µF
− 0.1µF
0.01µF
− 0.1µF
16Ω
1.1kΩ
1.1kΩ
50Ω
50Ω
0.01µF
0.01µF
TD -
TPFON
TPFOP
TD +
3.1kΩ
3.1kΩ
Fiber Txcvr
LXT971A
2
ON Semiconductor
MC100LVEL92
SD/TP
SD
PECL-to-LVPECL
Logic Translator
+3.3V
1
0.01µF
− 0.1µF
102Ω
102Ω
0.01µF
0.01µF
RD -
TPFIN
TPFIP
RD +
154Ω
154Ω
270Ω
270Ω
1. Refer to the transceiver manufacturer’s recommendations for termination circuitry.
2. See Figure 27 for recommended logic translator interface circuitry.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 27. ON Semiconductor Triple PECL-to-LVPECL Translator
5V
0.01 µF
0.01 µF
5V
3.3V
ON Semiconductor
82Ω
130Ω
82Ω
1
2
3
Vcc
Vcc
20
19
18
17
16
15
14
13
12
11
D0
__
Q0
__
PECL Input
Signal
LVPECL
Output Signal
(LXT971A)
D0
Q0
130Ω
(5V Fiber
Txcvr)
VBB PECL
4
5
LVCC
D1
__
Q1
__
3.3V
6
7
D1
Q1
VBB PECL
LVCC
D2
__
Q2
__
8
9
0.01 µF
3.3V
D2
Q2
GND
Vcc
10
130Ω
MC100LVEL92
82Ω
Datasheet
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
5.0
Test Specifications
Note: Table 17 through Table 40 and Figure 28 through Figure 41 represent the performance
specifications of the LXT971A. These specifications are guaranteed by test except where noted “by
design.” Minimum and maximum values listed in Table 19 through Table 40 apply over the
recommended operating conditions specified in Table 18.
5.1
Electrical Parameters
Table 17. Absolute Maximum Ratings
Parameter
Sym
VCC
Min
-0.3
-15
Max
4.0
Units
Supply voltage
LXT971A_C
V
TOPA
+85
ºC
(Commercial)
Operating temperature
LXT971A_E
TOPA
TST
-55
-65
+100
+150
ºC
ºC
(Extended)
Storage temperature
Caution: Exceeding these values may cause permanent damage.
Functional operation under these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device
reliability.
Table 18. Operating Conditions
1
Parameter
Sym
Min
Typ
Max
Units
LXT971A_C
(Commercial)
TOPA
0
–
70
ºC
Recommended operating
temperature
LXT971A_E
(Extended)
TOPA
-40
–
85
ºC
Analog & Digital
I/O
Vcca, Vccd
Vccio
ICC
3.14
3.3
–
3.45
3.45
110
82
V
Recommended supply voltage2
2.35
–
V
100BASE-TX
10BASE-T
92
66
72
40
–
mA
mA
mA
mA
mA
mA
mA
ICC
–
100BASE-FX
Sleep Mode
ICC
–
95
VCC current
ICC
–
45
Hard Power Down
Soft Power Down
Auto-Negotiation
ICC
–
1
Icc
–
51
90
–
ICC
–
110
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Voltages with respect to ground unless otherwise specified.
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 19. Digital I/O Characteristics2
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Input Low voltage
Input High voltage
Input current
VIL
VIH
II
–
–
–
–
–
–
0.8
–
V
V
–
2.0
-10
–
–
10
0.4
–
µA
V
0.0 < VI < VCC
IOL = 4 mA
IOH = -4 mA
Output Low voltage
Output High voltage
VOL
VOH
2.4
V
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Applies to all pins except MII, LED, XI/XO, and SD/TP pins. Refer to Table 20 for MII I/O Characteristics,
Table 21 for XI/XO and Table 22 for LED Characteristics.
Table 20. Digital I/O Characteristics - MII Pins
1
Parameter
Input Low voltage
Symbol
Min
Typ
Max
Units
Test Conditions
VIL
VIH
II
–
2.0
-10
–
–
–
0.8
–
V
V
–
Input High voltage
Input current
–
–
10
0.4
–
µA
V
0.0 < VI < VCCIO
IOL = 4 mA
Output Low voltage
VOL
VOH
VOH
–
2.2
2.0
–
–
V
IOH = -4 mA, VCCIO = 3.3V
IOH = -4 mA, VCCIO = 2.5V
VCCIO = 2.5V
Output High voltage
–
–
V
2
RO
100
100
–
W
W
Driver output resistance
2
(Line driver output enabled)
RO
–
–
VCCIO = 3.3V
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Parameter is guaranteed by design; not subject to production testing.
Table 21. I/O Characteristics - REFCLK/XI and XO Pins
Parameter
Input Low Voltage
Symbol
Min
Typ1
Max
Units
Test Conditions
VIL
VIH
∆f
–
2.0
–
–
–
0.8
–
V
V
–
–
–
–
–
Input High Voltage
Input Clock Frequency Tolerance2
Input Clock Duty Cycle2
Input Capacitance
–
±100
65
ppm
%
Tdc
CIN
35
–
–
3.0
–
pF
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Parameter is guaranteed by design; not subject to production testing.
Datasheet
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 22. I/O Characteristics - LED/CFG Pins
Parameter
Input Low Voltage
Symbol
Min
Typ
Max
Units
Test Conditions
VIL
VIH
II
–
–
–
–
–
–
0.8
–
V
V
–
Input High Voltage
Input Current
2.0
-10
–
–
10
0.4
–
µA
V
0 < VI < VCCIO
IOL = 10 mA
IOH = -10 mA
Output Low Voltage
Output High Voltage
VOL
VOH
2.0
V
Table 23. I/O Characteristics – SD/TP Pin
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
Reset and Power-Up States – FX/TP Mode Configuration
Fiber Mode (Register bit 16.0 = 1)
VFX
VTP
600 1600-2400
GND
–
mV
mV
–
–
Twisted-Pair Mode (Register bit 16.0 = 0)
–
500
100BASE-FX Mode Normal Operation – SD Input from Fiber Transceiver
Input Low Voltage
Input High Voltage
VIL
1.49
2.14
1.6
2.4
1.83
2.42
V
V
VCCD = 3.3 V
VCCD = 3.3 V
VIH
1. Typical values are for design aid only; not guaranteed and not subject to production testing.
Table 24. 100BASE-TX Transceiver Characteristics
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Peak differential output voltage
Signal amplitude symmetry
Signal rise/fall time
VP
Vss
TRF
TRFS
0.95
98
–
–
–
–
1.05
102
5.0
V
Note 2
Note 2
Note 2
Note 2
%
ns
ns
3.0
–
Rise/fall time symmetry
0.5
Offset from 16 ns pulse
width at 50% of pulse
peak
Duty cycle distortion
DCD
35
50
65
%
Overshoot/Undershoot
VOS
–
–
–
–
–
5
%
–
–
Jitter (measured differentially)
1.4
ns
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. Measured at the line side of the transformer, line replaced by 100Ω(+/-1%) resistor.
58
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 25. 100BASE-FX Transceiver Characteristics
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Transmitter
Peak differential output voltage
(single ended)
VOP
0.6
–
1.5
V
–
10 <–> 90%
2.0 pF load
Signal rise/fall time
TRF
–
–
–
–
–
1.9
1.3
ns
ns
Jitter (measured differentially)
–
Receiver
Peak differential input voltage
Common mode input range
VIP
0.55
–
–
–
1.5
V
V
–
–
VCMIR
VCC - 0.7
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
Table 26. 10BASE-T Transceiver Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Transmitter
With transformer, line
replaced by 100 Ω
resistor
Peak differential output
voltage
VOP
–
2.2
2.5
2
2.8
11
V
After line model
specified by IEEE
802.3 for 10BASE-T
MAU
Transition timing jitter added
by the MAU and PLS
sections
0
ns
Receiver
Receive Input Impedance
ZIN
–
–
22
kΩ
–
–
Differential Squelch
Threshold
VDS
300
420
585
mV
Table 27. 10BASE-T Link Integrity Timing Characteristics
Parameter
Symbol
Min
Typ
Max
Units
ms
Test Conditions
Time Link Loss Receive
Link Pulse
TLL
TLP
50
2
–
–
–
–
–
–
150
7
–
Link Pulses
–
–
–
–
–
Link Min Receive Timer
Link Max Receive Timer
Link Transmit Period
Link Pulse Width
TLR MIN
TLR MAX
Tlt
2
7
ms
ms
ms
ns
50
8
150
24
150
Tlpw
60
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
Datasheet
59
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 28. LXT971A Thermal Characteristics
Parameter
Package
LXT971ALC
LXT971ALE
LXT971ABE
1 0x 10 x1.4 64 LD LQFP 10 x 10 x 1.4 64 LQFP
7 x 7 x .96 64 BGA-CSP
Theta-JA
Theta-JC
Psi - JT
58 C/W
27 C/W
3.4 C/W
56 C/W
25 C/W
3.0 C/W
42 C/W
20 C/W
–
60
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
5.2
Timing Diagrams
Figure 28. 100BASE-TX Receive Timing - 4B Mode
0ns
250ns
TPFI
t4
t5
CRS
t3
RX_DV
t1
t2
RXD<3:0>
RX_CLK
t6
t7
COL
Table 29. 100BASE-TX Receive Timing Parameters - 4B Mode
1
Parameter
Sym
Min
Typ
Max
Units2
Test Conditions
RXD<3:0>, RX_DV, RX_ER setup
to RX_CLK High
t1
10
–
–
ns
–
RXD<3:0>, RX_DV, RX_ER hold
from RX_CLK High
t2
10
–
–
ns
–
CRS asserted to RXD<3:0>, RX_DV
Receive start of “J” to CRS asserted
Receive start of “T” to CRS de-asserted
Receive start of “J” to COL asserted
Receive start of “T” to COL de-asserted
t3
t4
t5
t6
t7
3
–
–
–
–
–
5
BT
BT
BT
BT
BT
–
–
–
–
–
12
10
16
17
16
17
22
20
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
100BASE-T bit time = 10-8 s or 10 ns.
Datasheet
61
Document #: 249414
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 29. 100BASE-TX Transmit Timing - 4B Mode
0ns
250ns
t1
TXCLK
TX_EN
t2
TXD<3:0>
t5
TPFO
t3
t4
CRS
Table 30. 100BASE-TX Transmit Timing Parameters - 4B Mode
1
Parameter
Symbol
Min
Typ
Max
Units2
Test Conditions
TXD<3:0>, TX_EN, TX_ER setup to
TX_CLK High
t1
12
–
–
ns
ns
–
TXD<3:0>, TX_EN, TX_ER hold from
TX_CLK High
t2
0
–
–
–
TX_EN sampled to CRS asserted
TX_EN sampled to CRS de-asserted
t3
t4
20
24
–
–
24
28
BT
BT
–
–
TX_EN sampled to TPFO out (Tx
latency)
t5
5.3
–
5.7
BT
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
100BASE-T bit time = 10-8 s or 10 ns.
62
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 30. 100BASE-FX Receive Timing
0ns
250ns
TPFI
t4
t5
CRS
t3
RX_DV
t1
t2
RXD<3:0>
RX_CLK
t6
t7
COL
Table 31. 100BASE-FX Receive Timing Parameters
1
Parameter
Sym
Min
Typ
Max
Units2
Test Conditions
RXD<3:0>, RX_DV, RX_ER setup
to RX_CLK High
t1
10
–
–
ns
–
RXD<3:0>, RX_DV, RX_ER hold
from RX_CLK High
t2
10
–
–
ns
–
CRS asserted to RXD<3:0>, RX_DV
Receive start of “J” to CRS asserted
Receive start of “T” to CRS de-asserted
Receive start of “J” to COL asserted
Receive start of “T” to COL de-asserted
t3
t4
t5
t6
t7
3
–
–
–
–
–
5
BT
BT
BT
BT
BT
–
–
–
–
–
12
16
10
14
16
22
15
18
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
100BASE-T bit time = 10-8 s or 10 ns.
Datasheet
63
Document #: 249414
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 31. 100BASE-FX Transmit Timing
0ns
250ns
t1
TXCLK
TX_EN
t2
TXD<3:0>
t5
TPFO
t3
t4
CRS
Table 32. 100BASE-FX Transmit Timing Parameters
1
Parameter
Symbol
Min
Typ
Max
Units2
Test Conditions
TXD<3:0>, TX_EN, TX_ER setup to
TX_CLK High
t1
12
–
–
ns
–
TXD<3:0>, TX_EN, TX_ER hold from
TX_CLK High
t2
0
–
–
ns
–
TX_EN sampled to CRS asserted
TX_EN sampled to CRS de-asserted
t3
t4
17
22
–
–
20
24
BT
BT
–
–
TX_EN sampled to TPFO out (Tx
latency)
t5
5
–
5.3
BT
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
100BASE-T bit time = 10-8 s or 10 ns.
64
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 32. 10BASE-T Receive Timing
RX_CLK
t
1
t2
t
3
RXD,
RX_DV,
RX_ER
t
5
t
4
CRS
t
6
t
t
7
9
TPFI
COL
t
8
Table 33. 10BASE-T Receive Timing Parameters
1
Parameter
Sym
Min
Typ
Max
Units2
Test Conditions
RXD, RX_DV, RX_ER Setup to
RX_CLK High
t1
10
–
–
ns
–
RXD, RX_DV, RX_ER Hold from
RX_CLK High
t2
t3
t4
10
4.2
5
–
–
–
–
ns
BT
BT
–
–
–
TPFIP/N in to RXD out (Rx latency)
6.6
32
CRS asserted to RXD, RX_DV,
RX_ER asserted
RXD, RX_DV, RX_ER de-asserted to
CRS de-asserted
t5
0.3
–
0.5
BT
–
TPFI in to CRS asserted
t6
t7
t8
t9
2
6
1
5
–
–
–
–
28
10
31
10
BT
BT
BT
BT
–
–
–
–
TPFI quiet to CRS de-asserted
TPFI in to COL asserted
TPFI quiet to COL de-asserted
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
10BASE-T bit time = 10-7 s or 100 ns.
Datasheet
65
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 33. 10BASE-T Transmit Timing
TX_CLK
t1
t2
TXD,
TX_EN,
TX_ER
t
3
t4
CRS
t
5
TPFO
Table 34. 10BASE-T Transmit Timing Parameters
1
Parameter
Symbol
Min
Typ
Max
Units2
Test Conditions
TXD, TX_EN, TX_ER setup to
TX_CLK High
t1
10
–
–
ns
–
TXD, TX_EN, TX_ER hold from
TX_CLK High
t2
0
–
–
ns
–
TX_EN sampled to CRS asserted
TX_EN sampled to CRS de-asserted
t3
t4
–
–
2
1
–
–
BT
BT
–
–
TX_EN sampled to TPFO out (Tx
latency)
t5
–
72.5
–
BT
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
10BASE-T bit time = 10-7 s or 100 ns.
66
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 34. 10BASE-T Jabber and Unjabber Timing
TX_EN
TXD
t
1
t
2
COL
Table 35. 10BASE-T Jabber and Unjabber Timing Parameters
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Maximum transmit time
Unjab time
t1
t2
20
–
–
150
750
ms
ms
–
–
250
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
Figure 35. 10BASE-T SQE (Heartbeat) Timing
TX_CLK
TX_EN
COL
t1
t2
Table 36. 10BASE-T SQE Timing Parameters
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
COL (SQE) Delay after TX_EN off
COL (SQE) Pulse duration
t1
t2
0.65
0.5
–
–
1.6
1.5
us
us
–
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
Datasheet
67
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 36. Auto-Negotiation and Fast Link Pulse Timing
Clock Pulse
Data Pulse
Clock Pulse
TPFOP
t1
t1
t3
t2
Figure 37. Fast Link Pulse Timing
FLP Burst
FLP Burst
TPFOP
t4
t5
Table 37. Auto-Negotiation and Fast Link Pulse Timing Parameters
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Clock/Data pulse width
Clock pulse to Data pulse
Clock pulse to Clock pulse
FLP burst width
t1
t2
t3
t4
t5
–
–
55.5
123
–
100
–
–
63.8
127
–
ns
µs
–
–
–
–
–
–
–
µs
2
ms
ms
ea
FLP burst to FLP burst
Clock/Data pulses per burst
8
12
–
24
17
33
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
68
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 38. MDIO Input Timing
MDC
t2
t1
MDIO
Figure 39. MDIO Output Timing
t4
MDC
t3
MDIO
Table 38. MDIO Timing Parameters
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
MDIO setup before MDC, sourced
by STA
t1
10
–
–
ns
–
MDIO hold after MDC, sourced
by STA
t2
5
–
–
ns
–
MDC to MDIO output delay,
source by PHY
t3
t4
–
–
–
150
–
ns
ns
–
MDC period
125
MDC = 8 MHz
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
Datasheet
69
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 40. Power-Up Timing
v1
t1
VCC
MDIO,etc
Table 39. Power-Up Timing Parameters
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Voltage threshold
Power Up delay2
v1
t1
–
–
2.9
–
–
V
–
–
300
µs
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
2. Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance -
the PHY comes out of reset after a delay of No MORE Than 300 µs. System designers should consider this
as a minimum value - After threshold v1 is reached, the MAC should delay No LESS Than 300 µs before
accessing the MDIO port.
Figure 41. RESET Pulse Width and Recovery Timing
t1
RESET
t2
MDIO,etc
Table 40. RESET Pulse Width and Recovery Timing Parameters
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
RESET pulse width
RESET recovery delay2
t1
t2
10
–
–
–
ns
–
–
300
µs
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
performance - the PHY comes out of reset after a delay of No MORE Than 300 µs. System designers
should consider this as a minimum value - After de-asserting RESET*, the MAC should delay No LESS
Than 300 µs before accessing the MDIO port.
70
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
6.0
Register Definitions
The LXT971A register set includes multiple 16-bit registers. Table 41 presents a complete register
listing. Table 42 is a complete memory map of all registers and Tables 43 through 58 provide
individual register definitions.
Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and
Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-
Negotiation” sections of the IEEE 802.3 standard.
Additional registers are defined in accordance with the IEEE 802.3 standard for adding unique chip
functions.
Table 41. Register Set
Address
Register Name
Bit Assignments
0
1
Control Register
Refer to Table 43 on page 74
Refer to Table 44 on page 75
Refer to Table 45 on page 76
Refer to Table 46 on page 76
Refer to Table 47 on page 77
Refer to Table 48 on page 78
Refer to Table 49 on page 79
Refer to Table 50 on page 79
Refer to Table 51 on page 80
Not Implemented
Status Register #1
2
PHY Identification Register 1
PHY Identification Register 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Base Page Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page Transmit Register
Auto-Negotiation Link Partner Received Next Page Register
1000BASE-T/100BASE-T2 Control Register
1000BASE-T/100BASE-T2 Status Register
Extended Status Register
3
4
5
6
7
8
9
10
15
16
17
18
19
20
21-25
26
27-29
30
Not Implemented
Not Implemented
Port Configuration Register
Refer to Table 52 on page 81
Refer to Table 53 on page 82
Refer to Table 54 on page 83
Refer to Table 55 on page 84
Refer to Table 56 on page 85
–
Status Register #2
Interrupt Enable Register
Interrupt Status Register
LED Configuration Register
Reserved
Digital Config Register
Refer to Table 57 on page 86
–
Reserved
Transmit Control Register
Refer to Table 58 on page 87
Datasheet
71
Document #: 249414
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
72
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Datasheet
73
Document #: 249414
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 43. Control Register (Address 0)
Bit
Name
Description
Type 1
Default
1 = PHY reset
0 = Normal operation
R/W
SC
0.15
Reset
0
1 = Enable loopback mode
0 = Disable loopback mode
0.14
Loopback
R/W
0
0.6
0.13
Speed Selected
1
1
0
0
1
0
1
0
Reserved
0.13
Speed Selection
R/W
Note 2
1000 Mbps (not supported)
100 Mbps
10 Mbps
Auto-Negotiation
Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
0.12
0.11
0.10
R/W
R/W
R/W
Note 2
1 = Power-down
Power-Down
Isolate
0
0
0 = Normal operation
1 = Electrically isolate PHY from MII
0 = Normal operation
Restart
Auto-Negotiation
R/W
SC
1 = Restart auto-negotiation process
0 = Normal operation
0.9
0
1 = Full-duplex
0 = Half-duplex
0.8
0.7
Duplex Mode
Collision Test
R/W
R/W
Note 2
0
1 = Enable COL signal test
0 = Disable COL signal test
0.6
0.13
Speed Selected
1
1
0
0
1
0
1
0
Reserved
0.6
Speed Selection
Reserved
R/W
R/W
0
1000 Mbps (not supported)
100 Mbps
10 Mbps
0.5:0
Write as 0, ignore on Read
00000
1. R/W = Read/Write
RO = Read Only
SC = Self Clearing
2. Default value of Register bits 0.12, 0.13 and 0.8 are determined by the LED/CFGn pins (refer to Table 9 on
page 30).
74
Datasheet
Document #: 249414
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 44. MII Status Register #1 (Address 1)
Bit
Name
100BASE-T4
Not Supported
Description
Type 1
Default
1 = PHY able to perform 100BASE-T4
0 = PHY not able to perform 100BASE-T4
1.15
RO
0
1 = PHY able to perform full-duplex 100BASE-X
0 = PHY not able to perform full-duplex 100BASE-X
1.14 100BASE-X Full-Duplex
1.13 100BASE-X Half-Duplex
RO
RO
1
1
1 = PHY able to perform half-duplex 100BASE-X
0 = PHY not able to perform half-duplex 100BASE-X
1 = PHY able to operate at 10 Mbps in full-duplex
mode
1.12 10 Mbps Full-Duplex
RO
RO
1
1
0 = PHY not able to operate at 10 Mbps full-duplex
mode
1 = PHY able to operate at 10 Mbps in half-duplex
mode
1.11 10 Mbps Half-Duplex
100BASE-T2 Full-
0 = PHY not able to operate at 10 Mbps in half-
duplex
1 = PHY able to perform full-duplex 100BASE-T2
0 = PHY not able to perform full-duplex 100BASE-T2
Duplex
Not Supported
1.10
RO
RO
0
0
100BASE-T2 Half-
Duplex
1 = PHY able to perform half-duplex 100BASE-T2
1.9
0 = PHY not able to perform half-duplex 100BASE-
T2
Not Supported
Extended Status
Reserved
1 = Extended status information in register 15
0 = No extended status information in register 15
1.8
1.7
RO
RO
0
0
1 = ignore when read
1 = PHY accepts management frames with
preamble suppressed
MF Preamble
Suppression
1.6
RO
0
0 = PHY will not accept management frames with
preamble suppressed
Auto-Negotiation
complete
1 = Auto-negotiation complete
1.5
1.4
1.3
1.2
1.1
1.0
RO
RO/LH
RO
0
0
1
0
0
1
0 = Auto-negotiation not complete
1 = Remote fault condition detected
0 = No remote fault condition detected
Remote Fault
1 = PHY is able to perform auto-negotiation
0 = PHY is not able to perform auto-negotiation
Auto-Negotiation Ability
Link Status
1 = Link is up
RO/LL
RO/LH
RO
0 = Link is down
1 = Jabber condition detected
Jabber Detect
0 = Jabber condition not detected
1 = Extended register capabilities
0 = Basic register capabilities
Extended Capability
1. RO = Read Only
LL = Latching Low
LH = Latching High
Datasheet
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Document #: 249414
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 45. PHY Identification Register 1 (Address 2)
Bit
Name
Description
Type 1
Default
The PHY identifier composed of bits 3 through 18 of
the OUI.
2.15:0
PHY ID Number
RO
0013 hex
1. RO = Read Only
Table 46. PHY Identification Register 2 (Address 3)
Bit
Name
Description
Type 1
Default
The PHY identifier composed of bits 19
through 24 of the OUI.
3.15:10 PHY ID number
RO
RO
011110
Manufacturer’s
3.9:4
6 bits containing manufacturer’s part number.
001110
model number
xxxx
(See the
Manufacturer’s
3.3:0
4 bits containing manufacturer’s revision
number.
RO
LXT971A/972A
Specification
Update)
revision number
1. RO = Read Only
Figure 42. PHY Identifier Bit Mapping
a
b
c
Organizationally Unique Identifier
r
s
x
PHY ID Register #2 (Address 3)
PHY ID Register #1 (address 2) = 0013
15
0
0
1
15
0
10
0
9
0
4
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
1
1
1
0 0
00
20
7B
5
0
3
0
The Intel OUI is 00207B hex
Manufacturer’s
Model Number
Revision
Number
76
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 47. Auto-Negotiation Advertisement Register (Address 4)
Bit
Name
Description
Type 1
Default
1 = Port has ability to send multiple pages.
0 = Port has no ability to send multiple pages.
4.15
4.14
4.13
4.12
4.11
Next Page
Reserved
R/W
RO
0
0
0
0
0
Ignore.
1 = Remote fault.
Remote Fault
R/W
R/W
R/W
0 = No remote fault.
Reserved
Ignore.
Asymmetric
Pause
Pause operation defined in Clause 40 and 27.
1 = Pause operation enabled for full-duplex links.
0 = Pause operation disabled.
4.10
Pause
R/W
Note 2
1 = 100BASE-T4 capability is available.
0 = 100BASE-T4 capability is not available.
(The LXT971A does not support 100BASE-T4 but
allows this bit to be set to advertise in the auto-
negotiation sequence for 100BASE-T4 operation. An
external 100BASE-T4 transceiver could be switched in
if this capability is desired.)
4.9
100BASE-T4
R/W
0
100BASE-TX
full-duplex
1 = Port is 100BASE-TX full-duplex capable.
0 = Port is not 100BASE-TX full-duplex capable.
4.8
4.7
R/W
R/W
Note 3
Note 3
1 = Port is 100BASE-TX capable.
100BASE-TX
0 = Port is not 100BASE-TX capable.
1 = Port is 10BASE-T full-duplex capable.
0 = Port is not 10BASE-T full-duplex capable.
Note 3
Note 3
10BASE-T
full-duplex
4.6
4.5
R/W
R/W
1 = Port is 10BASE-T capable.
0 = Port is not 10BASE-T capable.
10BASE-T
<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future auto-negotiation
development.
Selector Field,
S<4:0>
4.4:0
R/W
00001
<11111> = Reserved for future auto-negotiation
development.
Unspecified or reserved combinations should not be
transmitted.
1. R/W = Read/Write
RO = Read Only
2. The default setting of Register bit 4.10 (PAUSE) is determined by pin 33/H8 at reset.
3. Default values of Register bits 4.5, 4.6, 4.7, and 4.8 are determined by LED/CFGn pins at reset. Refer to
Table 9 for details.
Datasheet
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 48. Auto-Negotiation Link Partner Base Page Ability Register (Address 5)
Bit
Name
Description
Type 1
Default
1 = Link Partner has ability to send multiple pages.
0 = Link Partner has no ability to send multiple pages.
5.15
Next Page
RO
N/A
1 = Link Partner has received Link Code Word from
LXT971A.
5.14
Acknowledge
0 = Link Partner has not received Link Code Word from
RO
N/A
the
LXT971A.
1 = Remote fault.
5.13
5.12
Remote Fault
Reserved
RO
RO
N/A
N/A
0 = No remote fault.
Ignore.
Pause operation defined in Clause 40 and 27.
Asymmetric
Pause
5.11
RO
N/A
1 = Link Partner is Pause capable.
0 = Link Partner is not Pause capable.
1 = Link Partner is Pause capable.
5.10
5.9
Pause
RO
RO
N/A
N/A
0 = Link Partner is not Pause capable.
1 = Link Partner is 100BASE-T4 capable.
0 = Link Partner is not 100BASE-T4 capable.
100BASE-T4
1 = Link Partner is 100BASE-TX full-duplex capable.
0 = Link Partner is not 100BASE-TX full-duplex
capable.
100BASE-TX
full-duplex
5.8
RO
N/A
1 = Link Partner is 100BASE-TX capable.
0 = Link Partner is not 100BASE-TX capable.
5.7
5.6
5.5
100BASE-TX
RO
RO
RO
N/A
N/A
N/A
10BASE-T
full-duplex
1 = Link Partner is 10BASE-T full-duplex capable.
0 = Link Partner is not 10BASE-T full-duplex capable.
1 = Link Partner is 10BASE-T capable.
0 = Link Partner is not 10BASE-T capable.
10BASE-T
<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future auto-negotiation
development.
Selector Field
S<4:0>
5.4:0
RO
N/A
<11111> = Reserved for future auto-negotiation
development.
Unspecified or reserved combinations shall not be
transmitted.
1. RO = Read Only
78
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Document #: 249414
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 49. Auto-Negotiation Expansion (Address 6)
Bit
Name
Reserved
Description
Type 1
Default
6.15:6
Ignore on read.
RO
0
This bit indicates the status of the auto-negotiation
variable base page. It flags synchronization with the
auto-negotiation state diagram, allowing detection of
interrupted links. This bit is only used if Register bit
16.1 (Alternate NP feature) is set.
RO/
LH
6.5
Base Page
0
1 = Base page = true
0 = Base page = false
RO/
LH
Parallel
1 = Parallel detection fault has occurred.
0 = Parallel detection fault has not occurred.
6.4
0
Detection Fault
Link Partner
1 = Link partner is next page able.
6.3
6.2
RO
RO
0
1
Next Page Able
0 = Link partner is not next page able.
1 = Local device is next page able.
Next Page Able
Page Received
0 = Local device is not next page able.
1 = Indicates that a new page has been received and
the received code word has been loaded into Register
5 (Base Pages) or Register 8 (Next Pages) as specified
in Clause 28 of IEEE 802.3. This bit is cleared on Read.
If Register bit 16.1 is set, the Page Received bit is also
cleared when mr_page_rx = false or transmit_disable =
true.
RO
LH
6.1
0
0
Link Partner A/N 1 = Link partner is auto-negotiation able.
Able 0 = Link partner is not auto-negotiation able.
6.0
RO
1. RO = Read Only LH = Latching High
Table 50. Auto-Negotiation Next Page Transmit Register (Address 7)
Bit
Name
Description
Type 1
Default
Next Page
(NP)
1 = Additional next pages follow
0 = Last page
7.15
7.14
7.13
R/W
RO
0
0
1
Reserved
Write as 0, ignore on read
Message Page
(MP)
1 = Message page
0 = Unformatted page
R/W
Acknowledge 2
(ACK2)
1 = Complies with message
0 = Cannot comply with message
7.12
R/W
0
0
1 = Previous value of the transmitted Link Code
Word equalled logic zero
Toggle
(T)
7.11
R/W
R/W
0 = Previous value of the transmitted Link Code
Word equalled logic one
Message/Unformatted
Code Field
00000000
001
7.10:0
1. RO = Read Only. R/W = Read/Write
Datasheet
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Document #: 249414
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 51. Auto-Negotiation Link Partner Next Page Receive Register (Address 8)
Bit
Name
Description
Type 1
Default
1 = Link Partner has additional next pages to send
Next Page
(NP)
8.15
RO
0
0 = Link Partner has no additional next pages to
send
1 = Link Partner has received Link Code Word from
LXT971A
Acknowledge
(ACK)
8.14
RO
0
0 = Link Partner has not received Link Code Word
from LXT971A
1 = Page sent by the Link Partner is a Message
Page
Message Page
(MP)
8.13
8.12
RO
RO
0
0
0 = Page sent by the Link Partner is an Unformatted
Page
Acknowledge 2
(ACK2)
1 = Link Partner complies with the message
0 = Link Partner cannot comply with the message
1 = Previous value of the transmitted Link Code
Word equalled logic zero
Toggle
(T)
8.11
RO
RO
0
0
0 = Previous value of the transmitted Link Code
Word equalled logic one
Message/Unformatted
Code Field
User definable
8.10:0
1. RO = Read Only.
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Datasheet
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 52. Configuration Register (Address 16, Hex 10)
Bit
Name
Description
Type 1
Default
16.15 Reserved
Write as zero, ignore on read.
R/W
0
Force Link Pass
1 = Force Link pass
0 = Normal operation
16.14
R/W
R/W
0
0
1 = Disable Twisted Pair transmitter
0 = Normal Operation
16.13 Transmit Disable
Bypass Scrambler
16.12
1 = Bypass Scrambler and Descrambler
0 = Normal Operation
R/W
R/W
R/W
0
0
0
(100BASE-TX)
16.11 Reserved
Ignore
Jabber
16.10
1 = Disable Jabber Correction
0 = Normal operation
(10BASE-T)
SQE
16.9
1 = Enable Heart Beat
0 = Disable Heart Beat
R/W
R/W
0
0
(10BASE-T)
1 = Disable TP loopback during half-duplex
operation
TP Loopback
16.8
(10BASE-T)
0 = Normal Operation
CRS Select
16.7
1 = CRS deassert extends to RX_DV deassert
0 = Normal Operation
R/W
R/W
1
(10BASE-T)
1 = Enable Sleep Mode
0 = Disable Sleep Mode
16.6
16.5
Sleep Mode
Note 2
Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when
CRS is asserted.
PRE_EN
R/W
0
00 = 3.04 seconds
01 = 2.00 seconds
10 = 1.04 seconds
16.4:3
Sleep Timer
R/W
R/W
00
1
Fault Code
Enable
1 = Enable FEFI transmission
0 = Disable FEFI transmission
16.2
16.1
16.0
1 = Enable alternate auto negotiate next page
Alternate NP
feature
feature.
R/W
R/W
0
0 = Disable alternate auto negotiate next page
feature
1 = Select fiber mode.
0 = Select TP mode.
Fiber Select
Note 3
1. R/W = Read /Write
LHR = Latches High on Reset
2. The default value of Register bit 16.6 is determined by the state of the SLEEP pin 32/H7.
3. The default value of Register bit 16.0 is determined by pin 26/G2 (SD/TP).
Datasheet
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Document #: 249414
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 53. Status Register #2 (Address 17)
Bit
Name
Reserved
Description
Type 1
Default
17.15
Always 0.
RO
0
1 = LXT971A is operating in 100BASE-TX mode.
0 = LXT971A is not operating 100BASE-TX mode.
17.14
17.13
17.12
17.11
17.10
17.9
10/100 Mode
Transmit Status
Receive Status
Collision Status
Link
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
1 = LXT971A is transmitting a packet.
0 = LXT971A is not transmitting a packet.
1 = LXT971A is receiving a packet.
0 = LXT971A is not receiving a packet.
1 = Collision is occurring.
0 = No collision.
1 = Link is up.
0 = Link is down.
1 = Full-duplex.
0 = Half-duplex.
Duplex Mode
Auto-Negotiation
1 = LXT971A is in auto-negotiation mode.
0 = LXT971A is in manual mode.
17.8
1 = Auto-negotiation process completed.
0 = Auto-negotiation process not completed.
Auto-Negotiation
Complete
17.7
RO
0
This bit is only valid when auto negotiate is
enabled, and is equivalent to Register bit 1.5.
17.6
17.5
Reserved
Polarity
Always 0.
RO
RO
0
0
1 = Polarity is reversed.
0 = Polarity is not reversed.
1 = Device Pause capable.
17.4
17:3
Pause
Error
RO
RO
0
0
0 = Device Not Pause capable.
1 = Error Occurred (Remote Fault, X,Y, Z).
0 = No error occurred.
17:2
17:1
17.0
Reserved
Reserved
Reserved
Always 0.
Always 0.
Always 0.
RO
RO
RO
0
0
0
1. RO = Read Only. R/W = Read/Write
82
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 54. Interrupt Enable Register (Address 18)
Bit
Name
Reserved
Description
Write as 0; ignore on read.
Type 1
Default
18.15:9
18.8
R/W
R/W
N/A
0
Reserved
Write as 0; ignore on read.
Mask for Auto Negotiate Complete
18.7
18.6
18.5
18.4
ANMSK
R/W
R/W
R/W
R/W
0
0
0
0
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
Mask for Speed Interrupt
SPEEDMSK
DUPLEXMSK
LINKMSK
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
Mask for Duplex Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
Mask for Link Status Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
18.3
18.2
Reserved
Reserved
Write as 0, ignore on read.
Write as 0, ignore on read.
R/W
R/W
0
0
1 = Enable interrupts.
0 = Disable interrupts.
18.1
18.0
INTEN
TINT
R/W
0
1 = Force interrupt on MDINT.
0 = Normal operation.
R/W
0
1. R/W = Read /Write
Datasheet
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 55. Interrupt Status Register (Address 19, Hex 13)
Bit
Name
Reserved
Description
Type 1
Default
19.15:9
Ignore
Ignore
RO
N/A
0
19.8
Reserved
RO
Auto-negotiation Status
19.7
ANDONE
RO/SC
N/A
0
1= Auto-negotiation has completed.
0= Auto-negotiation has not completed.
Speed Change Status
1 = A Speed Change has occurred since last reading
19.6
19.5
19.4
SPEEDCHG
DUPLEXCHG
LINKCHG
this register.
RO/SC
RO/SC
RO/SC
0 = A Speed Change has not occurred since last
reading this register.
Duplex Change Status
1 = A Duplex Change has occurred since last
reading this register.
0
0 = A Duplex Change has not occurred since last
reading this register.
Link Status Change Status
1 = A Link Change has occurred since last reading
this register.
0
0
0 = A Link Change has not occurred since last
reading this register.
19.3
19.2
Reserved
MDINT
Ignore.
RO
RO
1 = MII interrupt pending.
0 = No MII interrupt pending.
19.1
19.0
Reserved
Reserved
Ignore.
Ignore
RO
RO
N/A
0
1. R/W = Read/Write, RO = Read Only, SC = Self Clearing.
84
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 56. LED Configuration Register (Address 20, Hex 14)
Bit
Name
Description
Type 1
Default
0000 = Display Speed Status (Continuous, Default)
0001 = Display Transmit Status (Stretched)
0010 = Display Receive Status (Stretched)
0011 = Display Collision Status (Stretched)
0100 = Display Link Status (Continuous)
0101 = Display Duplex Status (Continuous)
0110 = Unused
0111 = Display Receive or Transmit Activity (Stretched)
1000 = Test mode- turn LED on (Continuous)
1001 = Test mode- turn LED off (Continuous)
1010 = Test mode- blink LED fast (Continuous)
1011 = Test mode- blink LED slow (Continuous)
1100 = Display Link and Receive Status combined 2
(Stretched)3
LED1
20.15:12
R/W
0000
Programming
bits
1101 = Display Link and Activity Status combined 2
(Stretched)3
1110 = Display Duplex and Collision Status combined 4
(Stretched)3
1111 = Unused
0000 = Display Speed Status
0001 = Display Transmit Status
0010 = Display Receive Status
0011 = Display Collision Status
0100 = Display Link Status (Default)
0101 = Display Duplex Status
0110 = Unused
0111 = Display Receive or Transmit Activity
1000 = Test mode- turn LED on
1001 = Test mode- turn LED off
1010 = Test mode- blink LED fast
1011 = Test mode- blink LED slow
1100 = Display Link and Receive Status combined 2
(Stretched)3
LED2
20.11:8
R/W
0100
Programming
bits
1101 = Display Link and Activity Status combined 2
(Stretched)3
1110 = Display Duplex and Collision Status combined 4
(Stretched)3
1111 = Unused
1. R/W = Read /Write
RO = Read Only
LH = Latching High
2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive or Activity) causes the LED to change state (blink).
3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings
are stretched regardless of the value of 20.1.
4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
5. Values are relative approximations. Not guaranteed or production tested.
Datasheet
85
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 56. LED Configuration Register (Address 20, Hex 14) (Continued)
Bit
Name
Description
Type 1
Default
0000 = Display Speed Status
0001 = Display Transmit Status
0010 = Display Receive Status (Default)
0011 = Display Collision Status
0100 = Display Link Status
0101 = Display Duplex Status
0110 = Unused
0111 = Display Receive or Transmit Activity
1000 = Test mode- turn LED on
1001 = Test mode- turn LED off
1010 = Test mode- blink LED fast
1011 = Test mode- blink LED slow
1100 = Display Link and Receive Status combined 2
(Stretched)3
LED3
20.7:4
R/W
0010
Programming
bits
1101 = Display Link and Activity Status combined 2
(Stretched)3
1110 = Display Duplex and Collision Status combined 4
(Stretched)3
1111 = Unused
00 = Stretch LED events to 30 ms.
01 = Stretch LED events to 60 ms.
10 = Stretch LED events to 100 ms.
11 = Reserved.
20.3:2
LEDFREQ5
R/W
00
PULSE-
0 = Disable pulse stretching of all LEDs.
1 = Enable pulse stretching of all LEDs.
20.1
20.0
R/W
R/W
1
STRETCH
Reserved
Ignore.
N/A
1. R/W = Read /Write
RO = Read Only
LH = Latching High
2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive or Activity) causes the LED to change state (blink).
3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings
are stretched regardless of the value of 20.1.
4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
5. Values are relative approximations. Not guaranteed or production tested.
Table 57. Digital Config Register (Address 26)
Bit
Name
Reserved
Description
Type 1
RO
Default
26.15:12
Reserved
0
0
0
0
0
1 = Increased MII drive strength
0 = Normal MII drive strength
26.11
26.10
26.9
MII Drive Strength
Reserved
R/W
RO
Reserved
1 = Map Symbol Error Signal To RXER
0 = Normal RXER
Show Symbol Error
Reserved
R/W
RO
26.8:0
Reserved
1. R/W = Read /Write, RO = Read Only, LH = Latching High
86
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 58. Transmit Control Register (Address 30)
Bit
Name
Description
Type2
Default
30.15:11 Reserved
Ignore
R/W
0
1 = Forces the transmitter into low power mode.
Also forces a zero-differential transmission.
0 = Normal transmission.
30.12
Transmit Low Power
R/W
0
00 = 3.0 ns (default = TXSLEW<1:0> pins)
01 = 3.4 ns
10 = 3.9 ns
11 = 4.4 ns
30.11:10 Port Rise Time Control1
R/W
R/W
00
0
30.9:0
Reserved
Ignore
1. Values are relative approximations. Not guaranteed or production tested.
2. R/W = Read/Write
Datasheet
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
7.0
Package Specifications
Figure 43. PBGA Package Specification
64-Ball Plastic Ball Grid Array Package
• Part Number - LXT971ABC Commercial Temperature Range (0ºC to +70ºC)
• Part Number - LXT971ABE Extended Temperature Range (-40ºC to +85ºC)
(4X)
0.20
7.00 ± 0.20
2.00 REF.
B
6.30
0.70 REF.
0.80
OPTION:
PIN A1 IDENTIFIER
1.00 ± 0.10
A
B
INK OR LASER MARKING
C
D
E
F
G
H
TOP VIEW
1.26 ± 0.10
0.70 ± 0.025
4
3
2
1
8
7
6
5
0.26 ± 0.04
0.28 ± 0.10
0.30
0.15
C
C
B
A
0.40 ± 0.15
2
BOTTOM VIEW
C
SEATING PLANE
3
SIDE VIEW
NOTES:
1. All dimensions and tolerances conform to ASME Y 14.5 M - 1994.
2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
3. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
4. Maximum mold to substrate offset shall be 0.127.
5. The surface finish of the package shall be EDM Charmille #18 - #21.
6. Unless otherwise specified tolerance: Decimal ± 0.05 Angular ±2°.
88
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Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 44. LXT971A LQFP Package Specifications
64-Pin Low Profile Quad Flat Pack
• Part Number - LXT971ALC Commercial Temperature Range (0ºC to +70ºC)
• Part Number - LXT971ALE Extended Temperature Range (-40ºC to +85ºC)
D
D1
Millimeters
Dim
Min
Max
A
–
1.60
0.15
1.45
0.27
12.15
10.1
12.15
10.1
A
A
0.05
1.35
0.17
11.85
9.9
1
E1
2
E
B
D
D
1
E
11.85
9.9
E
1
e
0.50 BSC1
L
0.45
0.75
e
e
/
2
L
1.00 REF
11o
0o
1
θ3
θ
13o
7o
1. Basic Spacing between Centers
θ3
L1
A2
A
θ
A1
B
θ3
L
Datasheet
89
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
8.0
Product Ordering Information
Table 59. Product Information
Number
Revision
Qualification
Tray MM
Tape & Reel MM
DJLXT971ALC.A4
DJLXT971ALE.A4
FLLXT971ABC.A4
FLLXT971ABE.A4
A4
A4
A4
A4
S
S
S
S
834105
835676
834103
834104
834916
835791
834926
835080
Figure 45. Ordering Information - Sample
DJ
LXT
971A
L
C
A4
S
E001
Build Format
= Tray
E000
E001
= Tape and reel
Qualification
= Pre-production material
= Production material
Q
S
Product Revision
= 2 Alphanumeric characters
xn
Temperature Range
= Ambient (0 - 55° C)
A
C
E
= Commercial (0 - 70° C)
= Extended (-40 - +85° C)
Internal Package Designator
= LQFP
L
= PLCC
P
N
Q
H
T
= DIP
= PQFP
= QFP with heat spreader
= TQFP
= BGA
B
C
E
K
= CBGA
= TBGA
= HSBGA (BGA with heat slug)
xxxx
= 3-5 Digit Alphanumeric Product Code
IXA Product Prefix
= PHY layer device
LXT
IXE
IXF
IXP
= Switching engine
= Formatting device (MAC)
= Network processor
Intel Package Designator
DJ
FA
FL
FW
HB
HD
HF
HG
S
= LQFP
= TQFP
= PBGA (<1.0 mm pitch)
= PBGA (1.27 mm pitch)
= QFP with heat spreader
= QFP with heat slug
= CBGA
= SOIC
= QFP
GC
N
= TBGA
= PLCC
90
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
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