LXT971LC [LevelOne]
Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP64,;
| 型号： | LXT971LC |
| 厂家： | 
LEVEL ONE |
| 描述： | Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP64, 以太网：16GBASE-T 电信 电信集成电路 |
| 文件： | 总76页 (文件大小：796K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
FEBRUARY 2000
Revision1.1
LXT971
3.3V Dual-Speed Fast Ethernet Transceiver
General Description
Features
The LXT971 is an IEEE compliant Fast Ethernet PHY
Transceiver that directly supports both 100BASE-TX and
10BASE-T applications. It provides a Media Independent
Interface (MII) for easy attachment to 10/100 Media
Access Controllers (MACs). The LXT971 also provides a
pseudo-ECL (PECL) interface for use with 100BASE-FX
fiber networks.
• 3.3V Operation.
• Low power consumption (300 mW typical).
• Low-power “Sleep” mode.
• 10BASE-T and 100BASE-TX using a single RJ-45
connection.
• Supports auto-negotiation and parallel detection.
• MII interface with extended register capability.
• Robust baseline wander correction performance.
• 100BASE-FX fiber optic capable.
The LXT971 supports full-duplex operation at 10 Mbps
and 100 Mbps. Its operating condition can be set using
auto-negotiation, parallel detection, or manual control.
The LXT971 is fabricated with an advanced CMOS
process and requires only a single 3.3V power supply.
• Standard CSMA/CD or full-duplex operation.
• Configurable via MDIO serial port or hardware
control pins.
Applications
• Integrated, programmable LED drivers.
• Combination 10BASE-T/100BASE-TX or
100BASE-FX Network Interface Cards (NICs)
• 64-pin Plastic Ball Grid Array (PBGA).
• LXT971BC - Commercial (0° to 70°C ambient).
• LXT971BE - Extended (-40° to 85°C ambient).
• 64-pin Low-profile Quad Flat Package (LQFP).
• LXT971LC - Commercial (0° to 70°C ambient).
• LXT971LE - Extended (-40° to 85°C ambient).
• 10/100 PCMCIA Cards
• Cable Modems and Set-Top Boxes
LXT971
Block Diagram
RESET
VCC
Pwr Supply
GND
P W R D W N
Management
Mode Select
Logic
/
ADDR<4:0>
MDIO
Register Set
REFCLK
Clock
Generator
MDC
MDINT
MDDIS
TxSLEW<1:0>
+
Manchester
Encoder
10
TX_EN
TXD <3:0>
TX_ER
TP
Driver
OSP
™
Pulse
TPFOP
TPFON
-
Parallel/Serial
Converter
Scrambler
100
TP
/
Fiber
Shaper
&
Encoder
Out
+
TX_CLK
ECL
Driver
Auto
Negotiation
-
TDIO,
TMS,
TCK,
TRST
Register
Set
5
LED/CFG <3:1>
COL
JTAG
OSP
™
Adaptive EQ with
Baseline Wander
Cancellation
+
Collision
Detect
Media
Select
Clock
Generator
100TX
100FX
10BT
-
+
RX_CLK
RXD <3:0>
RXDV
TPFIP
TPFIN
SD/TP
Manchester
Decoder
TP
/
Fiber
In
Serial-to-
Parallel
Converter
10
OSP
™
-
+
Slicer
Decoder
Descrambler
&
Carrier Sense
Data Valid
Error Detect
100
CRS
RX_ER
-
Refer to www.level1.com for most current information.
)
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
TABLE OF CONTENTS
Pin Assignments ................................................... 4
Signal Descriptions ............................................... 7
Functional Description ........................................ 11
MII Operation......................................................19
MII Clocks .........................................................19
Transmit Enable ................................................19
Receive Data Valid............................................19
Carrier Sense....................................................19
Error Signals .....................................................19
Collision.............................................................19
Loopback...........................................................21
Operational Loopback..................................21
Test Loopback..............................................21
Introduction ....................................................... 11
OSP™ Architecture .......................................... 11
Comprehensive Functionality............................ 12
Network Media/Protocol Support..................... 12
10/100 Network Interface.................................. 12
Twisted-Pair Interface.................................. 12
Fiber Interface.............................................. 12
Fault Detection and Reporting..................... 12
Remote Fault.......................................... 12
Far-End Fault.......................................... 12
MII Data Interface ............................................. 13
Configuration Management Interface................ 13
MDIO Management Interface ...................... 13
MDIO Addressing ................................... 13
MDIO Frame Structure ........................... 13
MII Interrupts .......................................... 14
Hardware Control Interface.......................... 14
Operating Requirements................................... 15
Power Requirements ........................................ 15
Clock Requirements.......................................... 15
External Crystal Oscillator ........................... 15
100 Mbps Operation ..........................................22
100BASE-X Network Operation........................22
Collision Indication ............................................25
100BASE-X Protocol Sublayer Operations.......26
PCS Sublayer ..............................................26
Preamble Handling .................................26
Dribble Bits .............................................26
4B/5B Coding Table .....................................27
PMA Sublayer..............................................28
Link .........................................................28
Link Failure Override ..............................28
Carrier Sense..........................................28
Receive Data Valid .................................28
Twisted-Pair PMD Sublayer.........................29
Scrambler/Descrambler..........................29
Baseline Wander Correction...................29
Polarity Correction ..................................29
Programmable Slew Rate Control ..........29
Fiber PMD Sublayer.....................................29
Initialization........................................................ 15
MDIO Control Mode.......................................... 15
Hardware Control Mode.................................... 15
Reduced Power Modes .................................... 16
Hardware Power Down................................ 16
Software Power Down ................................. 16
Sleep Mode.................................................. 16
Reset ................................................................ 16
Hardware Configuration Settings...................... 17
10 Mbps Operation ............................................30
10T Preamble Handling ....................................30
10T Carrier Sense.............................................30
10T Dribble Bits.................................................30
10T Link Integrity Test.......................................30
Link Failure ..................................................30
10T SQE (Heartbeat) ........................................30
10T Jabber........................................................30
10T Polarity Correction .....................................30
Establishing Link............................................... 18
Auto-Negotiation ............................................... 18
Base Page Exchange .................................. 18
Next Page Exchange................................... 18
Controlling Auto-Negotiation........................ 18
Parallel Detection.............................................. 18
2
ꢀ
LXT971 Table of Contents
Monitoring Operations ......................................31
Monitoring Auto-Negotiation..............................31
Monitoring Next Page Exchange..................31
LED Functions...................................................31
LED Pulse Stretching...................................32
PHY Identification Register 1 (Address 2) ........ 58
PHY Identification Register 2 (Address 3) ........ 58
A/N Advertisement Register (Address 4).......... 59
A/N Link Partner Ability Register (Address 5)... 60
A/N Expansion Register (Address 6)................ 61
A/N Next Page Transmit Register (Address 7). 62
Boundary Scan (JTAG) Functions....................33
Boundary Scan Interface...................................33
State Machine ...................................................33
Instruction Register ...........................................33
Boundary Scan Register (BSR).........................33
A/N Link Partner Next Page Receive Register
(Address 8) ....................................................... 62
Port Configuration Register (Address 16)......... 63
Quick Status Register (Address 17) ................. 64
Interrupt Enable Register (Address 18) ............ 65
Interrupt Status Register (Address 19) ............. 66
LED Configuration Register (Address 20) ........ 67
Transmit Control Register (Address 30) ........... 69
Application Information .......................................34
Magnetics Information.......................................34
Typical Twisted-Pair Interface ...........................36
Typical MII Interface ..........................................37
Typical Fiber Interface.......................................38
Package Specifications....................................... 70
Revision History................................................... 72
Preliminary Test Specifications ..........................39
Electrical Parameters ........................................39
Absolute Maximum Ratings...............................39
Operating Conditions.........................................39
Digital I/O Characteristics..................................40
Digital I/O Characteristics - MII Pins..................40
I/O Characteristics - REFCLK/XI and XO Pins..40
I/O Characteristics - LED/CFG Pins..................41
100BASE-TX Transceiver Characteristics.........41
100BASE-FX Transceiver Characteristics.........41
10BASE-T Transceiver Characteristics.............42
10BASE-T Link Integrity Timing Characteristics42
Timing Diagrams................................................43
100BASE-TX Receive Timing - 4B Mode .........43
100BASE-TX Transmit Timing - 4B Mode ........44
100BASE-FX Receive Timing ...........................45
100BASE-FX Transmit Timing ..........................46
10BASE-T Receive Timing................................47
10BASE-T Transmit Timing...............................48
10BASE-T Jab and Unjab Timing......................49
Auto Negotiation and Fast Link Pulse Timing....50
MDIO Timing .....................................................51
Power-Up Timing...............................................52
RESET Pulse Width and Recovery Timing .......52
Register Definitions..............................................53
Control Register (Address 0).............................56
Status Register (Address 1) ..............................57
3
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
PIN ASSIGNMENTS
Figure 1: 64-Pin PBGA Pin Assignments
1
2
3
4
5
6
7
8
M D I N T
C R S
T X D 3
T X D 0
R X _ E R
V C C D
R X _ D V
R X D 0
A
B
C
D
E
C O L
T X D 2
G N D
T X _ E N T X _ E R R X _ C L K
N/C
N/C
N/C
R X D 1
R X D 2
M D I O
REFCLK/XI
X O
R E S E T
T X D 1 T X _ C L K
G N D
M D D I S
G N D
G N D
G N D
V C C I O
V C C I O
TDI
R X D 3
T x S L E W 0 T x S L E W 1
A D D R 0 A D D R 1
M D C P W R D W N
L E D / C F G 1
A D D R 3
A D D R 4
R B I A S
A D D R 2
SD/TP
G N D
G N D
T M S
T C K
L E D / C F G 2 L E D / C F G 3
F
V C C A
T P F O N
V C C A
TPFIP
T D O
T E S T 1
S L E E P
T E S T 0
P A U S E
G
H
T P F O P
TPFIN
T R S T
)
Bottom Mark
LXT971
4
ꢀ
LXT971 Pin Assignments
PIN ASSIGNMENTS
Figure 2: 64-Pin LQFP Pin Assignments
48
47
RXD0
RXD1
1
REFCLK/XI
XO
2
46 RXD2
45 RXD3
3
MDDIS
RESET
TXSLEW0
TXSLEW1
GND
4
N/C
44
5
43 MDC
42 MDIO
6
7
GND
41
)
8
VCCIO
N/C
40 VCCIO
9
LXT971
39 PWRDWN
10
11
12
13
14
15
16
N/C
LED/CFG1
38
GND
37 LED/CFG2
36 LED/CFG3
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
TEST1
35
34 TEST0
33 PAUSE
5
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Table 1: LQFP Numeric Pin List – continued
Reference for
Full
Description
Table 1: LQFP Numeric Pin List
Reference for
Pin
Symbol
Type
Pin
Symbol
Type
Full
Description
34.
TEST0
Input
Input
I/O
Table 4 on page 9
Table 4 on page 9
Table 7 on page 10
Table 7 on page 10
Table 7 on page 10
Table 4 on page 9
Table 5 on page 10
Table 5 on page 10
Table 2 on page 7
Table 2 on page 7
Table 4 on page 9
Table 2 on page 7
Table 2 on page 7
Table 2 on page 7
Table 2 on page 7
Table 2 on page 7
Table 5 on page 10
Table 5 on page 10
Table 2 on page 7
Table 2 on page 7
Table 2 on page 7
Table 2 on page 7
Table 2 on page 7
Table 2 on page 7
Table 2 on page 7
Table 2 on page 7
Table 2 on page 7
Table 5 on page 10
Table 2 on page 7
Table 2 on page 7
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
TEST1
LED/CFG3
LED/CFG2
LED/CFG1
PWRDWN
VCCIO
GND
1.
REFCLK/XI
XO
Input
Output
Input
Input
Input
Input
–
Table 4 on page 9
Table 4 on page 9
Table 2 on page 7
Table 4 on page 9
Table 4 on page 9
Table 4 on page 9
Table 5 on page 10
Table 5 on page 10
Table 4 on page 9
Table 4 on page 9
Table 5 on page 10
Table 4 on page 9
Table 4 on page 9
Table 4 on page 9
Table 4 on page 9
Table 4 on page 9
Table 4 on page 9
2.
I/O
3.
MDDIS
RESET
TxSLEW0
TxSLEW1
GND
I/O
4.
Input
–
5.
6.
–
7.
MDIO
I/O
8.
VCCIO
N/C
–
MDC
Input
–
9.
–
N/C
10.
11.
12.
13.
14.
15.
16.
N/C
–
RXD3
Output
Output
Output
Output
Output
–
GND
–
RXD2
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
RBIAS
Input
Input
Input
Input
Input
RXD1
RXD0
RX_DV
GND
VCCD
RX_CLK
RX_ER
TX_ER
TX_CLK
TX_EN
TXD0
–
Analog
Input
17.
Output
Output
Input
Output
Input
Input
Input
Input
Input
–
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
GND
–
Table 5 on page 10
Table 3 on page 8
Table 3 on page 8
Table 5 on page 10
Table 5 on page 10
Table 3 on page 8
Table 3 on page 8
Table 5 on page 10
Table 3 on page 8
Table 6 on page 10
Table 6 on page 10
Table 6 on page 10
Table 6 on page 10
Table 6 on page 10
Table 4 on page 9
Table 4 on page 9
TPFOP
TPFON
VCCA
VCCA
TPFIP
TPFIN
GND
Output
Output
–
–
Input
Input
–
TXD1
TXD2
TXD3
SD/TP
TDI
Input
Input
Output
Input
Input
Input
Input
Input
GND
COL
Output
Output
TDO
CRS
TMS
MDINT
Open Drain Table 2 on page 7
TCK
TRST
SLEEP
PAUSE
6
ꢀ
LXT971 Signal Descriptions
SIGNAL DESCRIPTIONS
Table 2: LXT971 MII Signal Descriptions
PBGA LQFP
Type1
Symbol
Signal Description
Pin#
Pin#
Data Interface Pins
A3
B3
C4
A4
B4
60
59
58
57
56
TXD3
I
Transmit Data. TXD is a bundle of parallel data signals that are driven
by the MAC. TXD<3:0> shall transition synchronously with respect to the
TX_CLK. TXD<0> is the least significant bit.
TXD2
TXD1
TXD0
TX_EN
I
Transmit Enable. The MAC asserts this signal when it drives valid data
on TXD. This signal must be synchronized to TX_CLK.
C5
55
TX_CLK
O
Transmit Clock. TX_CLK is sourced by the PHY in both 10 and 100
Mbps operations. 2.5 MHz for 10 Mbps operation, 25 MHz for 100 Mbps
operation.
D6
C8
B8
A8
A7
45
46
47
48
49
RXD3
RXD2
RXD1
RXD0
RX_DV
O
Receive Data. RXD is a bundle of parallel signals that transition
synchronously with respect to the RX_CLK. RXD<0> is the least
significant bit.
O
O
I
Receive Data Valid. The LXT971 asserts this signal when it drives valid
data on RXD. This output is synchronous to RX_CLK.
A5
B5
B6
53
54
52
RX_ER
TX_ER
RX_CLK
Receive Error. Signals a receive error condition has occurred. This
output is synchronous to RX_CLK.
Transmit Error. Signals a transmit error condition. This signal must be
synchronized to TX_CLK.
O
Receive Clock. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps
operation. Refer to “Clock Requirements” on page 15 in the Functional
Description section.
B2
A2
62
63
COL
CRS
O
O
Collision Detected. The LXT971 asserts this output when a collision is
detected. This output remains High for the duration of the collision. This
signal is asynchronous and is inactive during full duplex operation.
Carrier Sense. During half-duplex operation (bit 0.8 = 0), the LXT971
asserts this output when either transmitting or receiving data packets.
During full-duplex operation (bit 0.8 = 1), CRS is asserted only during
receive. CRS assertion is asynchronous with respect to RX_CLK. CRS is
de-asserted on loss of carrier, synchronous to RX_CLK.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
7
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Table 2: LXT971 MII Signal Descriptions – continued
PBGA LQFP
Type1
Symbol
Signal Description
Pin#
Pin#
MII Control Interface Pins
D3
3
MDDIS
I
Management Disable. When MDDIS is High, the MDIO is disabled from
read and write operations.
When MDDIS is Low at power up or reset, the Hardware Control Inter-
face pins control only the initial or “default” values of their respective reg-
ister bits. After the power-up/reset cycle is complete, bit control reverts to
the MDIO serial channel.
E7
D8
A1
43
42
64
MDC
I
Management Data Clock. Clock for the MDIO serial data channel. Max-
imum frequency is 8 MHz.
MDIO
MDINT
I/O
OD
Management Data Input/Output. Bidirectional serial data channel for
PHY/STA communication.
Management Data Interrupt. When bit 18.1 = 1, an active Low output
on this pin indicates status change. Interrupt is cleared by reading Regis-
ter 19.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
Table 3: LXT971 Network Interface Signal Descriptions
PBGA LQFP
Type1
Symbol
Signal Description
Pin#
Pin#
H2
H3
19
20
TPFOP
TPFON
O
Twisted-Pair/Fiber Outputs, Positive & Negative.
During 100BASE-TX or 10BASE-T operation, TPFOP/N pins drive
802.3 compliant pulses onto the line.
During 100BASE-FX operation, TPFOP/N pins produce differential
PECL outputs for fiber transceivers.
H4
H5
23
24
TPFIP
TPFIN
I
Twisted-Pair/Fiber Inputs, Positive & Negative.
During 100BASE-TX or 10BASE-T operation, TPFIP/N pins receive
differential 100BASE-TX or 10BASE-T signals from the line.
During 100BASE-FX operation, TPFIP/N pins receive differential
PECL inputs from fiber transceivers.
G2
26
SD/TP
I
Signal Detect. Tying the SD/TP pin High or to a PECL input sets bit
16.0 = 1 and the port is forced to FX mode.
Tie the SD/TP pin High for Fx Loopback.
The SD/TP pin has an internal pull-down. When not using FX mode,
the SD/TP pin should be tied to GND.
TP Select. Tying the SD/TP pin Low sets bit 16.0 = 0 and forces the
port to TP mode.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
8
ꢀ
LXT971 Signal Descriptions
Table 4: LXT971 Miscellaneous Signal Descriptions
PBGA
Pin#
LQFP
Pin#
Type1
Signal Description
Symbol
D1
D2
5
6
TxSLEW0
TxSLEW1
I
Tx Output Slew Controls 0 and 1. These pins select the TX out-
put slew rate (rise and fall time) as follows:
TxSLEW1 TxSLEW0 Slew Rate (Rise and Fall Time)
0
0
1
1
0
1
0
1
2.5 ns
3.1 ns
3.7 ns
4.3 ns
C2
4
RESET
I
Reset. This active Low input is OR’ed with the control register
Reset bit (0.15). The LXT971 reset cycle is extended to 258 µs
(nominal) after reset is deasserted.
G1
F1
F2
E2
E1
16
15
14
13
12
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
I
I
I
I
I
Address <4:0>. Sets device address.
H1
17
RBIAS
AI
Bias. This pin provides bias current for the internal circuitry. Must
be tied to ground through a 22.1 kΩ, 1% resistor.
H8
H7
33
32
PAUSE
SLEEP
I
I
Pause. When set High, the LXT971 advertises Pause capabilities
during auto negotiation.
Sleep. When set High, this pin enables the LXT971 to go into a
low-power sleep mode. The value of this pin can be overridden by
register bit 16.6 when in managed mode.
G8
G7
E8
34
35
39
TEST0
I
I
I
Test. Tie Low.
Test. Tie Low.
TEST1
PWRDWN
Power Down. When set High, this pin puts the LXT971 in a
power-down mode.
B1
C1
1
2
REFCLK/XI
XO
I
Crystal Input and Output. A 25 MHz crystal oscillator circuit can
be connected across XI and XO. A clock can also be used at XI.
Refer to “Clock Requirements” on page 15 in the Functional
Description section.
O
B7, C7
D7
9, 10
44
N/C
-
No Connection. These pins are not used and should not be termi-
nated.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
9
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Table 5: LXT971 Power Supply Signal Descriptions
PBGA
Pin#
LQFP
Pin#
Symbol
Type
Signal Description
A6
51
VCCD
-
-
Digital Power. Requires a 3.3V power supply.
D4, E3 7, 11, 18, GND
Ground.
E4, F3
F4, C6,
C3
25, 41,
50, 61
E5, D5
8, 40
VCCIO
-
-
MII Power. Requires either a 3.3V or a 2.5V supply. Must be sup-
plied from the same source used to power the MAC on the other side
of the MII.
G3, G4
21, 22 VCCA
Analog Power. Requires a 3.3V power supply.
Table 6: LXT971 JTAG Test Signal Descriptions
PBGA LQFP
Type1
Symbol
Signal Description
Pin#
Pin#
TDI2
F5
I
Test Data Input. Test data sampled with respect to the rising edge of
TCK.
27
TDO2
G5
O
Test Data Output. Test data driven with respect to the falling edge of
TCK.
28
TMS2
TCK2
TRST2
F6
G6
H6
I
I
I
Test Mode Select.
29
30
31
Test Clock. Test clock input sourced by ATE.
Test Reset. Test reset input sourced by ATE.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
2. If JTAG port is not used, these pins do not need to be terminated.
Table 7: LXT971 LED Signal Descriptions
PBGA
Pin#
LQFP
Pin#
Type1
Symbol
Signal Description
E6
F7
F8
38
37
36
LED/CFG1
LED/CFG2
LED/CFG3
I/O
LED Drivers 1 -3. These pins drive LED indicators. Each LED can
display one of several available status conditions as selected by the
LED Configuration Register (refer to Table 53 on page 67 for
details).
Configuration Inputs 1-3. These pins also provide initial configu-
ration settings (refer to Table 8 on page 17 for details).
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
10
ꢀ
LXT971 Functional Description
FUNCTIONAL DESCRIPTION
OSP™ Architecture
Introduction
Level One's LXT971 incorporates high-efficiency Optimal
Signal Processing™ design techniques, combining the best
properties of digital and analog signal processing to
produce a truly optimal device.
The LXT971 is a single-port Fast Ethernet 10/100
Transceiver that supports 10 Mbps and 100 Mbps
networks. It complies with all applicable requirements of
IEEE 802.3. The LXT971 can directly drive either a
100BASE-TX line (up to 140 meters) or a 10BASE-T line
(up to 185 meters). The LXT971 also supports 100BASE-
FX operation via a Pseudo-ECL (PECL) interface.
The receiver utilizes decision feedback equalization to
increase noise and cross-talk immunity by as much as 3 dB
over an ideal all-analog equalizer. Using OSP mixed-signal
processing techniques in the receive equalizer avoids the
quantization noise and calculation truncation errors found
in traditional DSP-based receivers (typically complex DSP
engines with A/D converters). This results in improved
receiver noise and cross-talk performance.
Comprehensive Functionality
The LXT971 provides a standard Media Independent
Interface (MII) for 10/100 MACs. The LXT971 performs
all functions of the Physical Coding Sublayer (PCS) and
Physical Media Attachment (PMA) sublayer as defined in
the IEEE 802.3 100BASE-X standard. This device also
performs all functions of the Physical Media Dependent
(PMD) sublayer for 100BASE-TX connections.
The OSP signal processing scheme also requires
substantially less computational logic than traditional DSP-
based designs. This lowers power consumption and also
reduces the logic switching noise generated by DSP
engines. This logic switching noise can be a considerable
source of EMI generated on the device’s power supplies.
On power-up, the LXT971 reads its configuration pins to
check for forced operation settings. If not configured for
forced operation, it uses auto-negotiation/parallel detection
to automatically determine line operating conditions. If the
PHY device on the other side of the link supports auto-
negotiation, the LXT971 will auto-negotiate with it using
Fast Link Pulse (FLP) Bursts. If the PHY partner does not
support auto-negotiation, the LXT971 will automatically
detect the presence of either link pulses (10 Mbps PHY) or
Idle symbols (100 Mbps PHY) and set its operating
conditions accordingly.
The OSP-based LXT971 provides improved data recovery,
EMI performance and low power consumption.
The LXT971 provides half-duplex and full-duplex
operation at 100 Mbps and 10 Mbps.
11
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Fiber Interface
Network Media / Protocol
Support
The LXT971 fiber port is designed to interface with
common industry-standard fiber modules. It
incorporates a PECL interface that complies with the
ANSI X3.166 standard for seamless integration.
The LXT971 supports both 10BASE-T and 100BASE-TX
Ethernet over twisted-pair, or 100 Mbps Ethernet over fiber
media (100BASE-FX).
Fiber mode is selected by putting a PECL level on the
signal detect pin (SD/TP). If the device SD/TP pin is
grounded, twisted-pair configuration settings are
used. This will only be sensed upon completion of
reset.
10/100 Network Interface
The network interface port consists of five external pins
(two differential signal pairs and a signal detect pin). The I/
O pins are shared between twisted-pair (TP) and fiber.
Refer to Figure 2 for specific pin assignments.
Fault Detection and Reporting
The LXT971 supports two fault detection and
reporting mechanisms. “Remote Fault” refers to a
MAC-to-MAC communication function that is
essentially transparent to PHY layer devices. It is
used only during Auto-Negotiation, and therefore is
applicable only to twisted-pair links. “Far-End Fault”,
on the other hand, is an optional PMA-layer function
that may be embedded within PHY devices. The
LXT971 supports both functions. Both are further
explained in the sections that follow.
The LXT971 output drivers generate either 100BASE-TX,
10BASE-T, or 100BASE-FX output. When not
transmitting data, the LXT971 generates 802.3-compliant
link pulses or idle code. Input signals are decoded either as
a 100BASE-TX, 100BASE-FX, or 10BASE-T input,
depending on the mode selected. Auto-negotiation/parallel
detection or manual control is used to determine the speed
of this interface.
Twisted-Pair Interface
Remote Fault
The LXT971 supports either 100BASE-TX or
10BASE-T connections over 100Ω, Category 5,
Unshielded Twisted Pair (UTP) cable. When operating
at 100 Mbps, the LXT971 continuously transmits and
receives MLT3 symbols. When not transmitting data,
the LXT971 generates “IDLE” symbols.
Bit 4.13 in the Auto-Negotiation Advertisement
Register is reserved for Remote Fault indications. It
is typically used when re-starting the auto-negotiation
sequence to indicate to the link partner that the link is
down because the advertising device detected a fault.
When the LXT971 receives a Remote Fault indication
from its partner during auto-negotiation it:
During 10 Mbps operation, Manchester-encoded data
is exchanged. When no data is being exchanged, the
line is left in an idle state. Link pulses are transmitted
periodically to keep the link up.
• sets bit 5.13 in the Link Partner Base Page
Ability Register, and
• sets the Remote Fault bit 1.4 in the MII Status
Register to pass this information to the local con-
troller.
Only a transformer, RJ-45 connector, load resistor,
and bypass capacitors are required to complete this
interface. On the transmit side, the LXT971 has an
active internal termination and does not require exter-
nal termination resistors. Level One's patented wave-
shaping technology shapes the outgoing signal to help
reduce the need for external EMI filters. Four slew rate
settings (refer to Table 4 on page 9) allow the designer
to match the output waveform to the magnetic charac-
teristics. On the receive side, the internal impedance is
high enough that it has no practical effect on the exter-
nal termination circuit.
Far-End Fault
In fiber mode, the SD/TP pin monitors signal quality.
If the signal quality degrades beyond the fault
threshold, the fiber transceiver reports a signal quality
fault condition via the SD/TP pin. Loss of signal
quality blocks any fiber data from being received and
cause a loss of link.
If the LXT971 detects a signal fault condition, it can
transmit the Far-End Fault Indication (FEFI) over the
fiber link. The FEFI consists of 84 consecutive 1s
followed by a single 0. This pattern must be repeated
at least 3 times. The LXT971 transmits the far-end
fault code a minimum of 3 times if all the following
conditions are true:
12
ꢀ
LXT971 Functional Description
• Fiber mode is selected.
interface consists of a physical connection, a specific
protocol that runs across the connection, and an
internal set of addressable registers.
• Fault Code transmission is enabled (bit 16.2 = 1).
• Either Signal Detect indicates no signal or the
receive PLL cannot lock.
Some registers are required and their functions are
defined by the IEEE 802.3 standard. The LXT971
also supports additional registers for expanded
functionality. The LXT971 supports multiple internal
registers, each of which is 16 bits wide. Specific
register bits are referenced using an “X.Y” notation,
where X is the register number (0-31) and Y is the bit
number (0-15).
• Loopback is not enabled.
MII Data Interface
The LXT971 supports a standard Media Independent
Interface (MII). The MII consists of a data interface and a
management interface. The MII Data Interface passes data
between the LXT971 and a Media Access Controller
(MAC). Separate parallel buses are provided for transmit
and receive. This interface operates at either 10 Mbps or
100 Mbps. The speed is set automatically, once the
operating conditions of the network link have been
determined. Refer to “MII Operation” on page 19 for
additional details.
The physical interface consists of a data line (MDIO)
and clock line (MDC). Operation of this interface is
controlled by the MDDIS input pin. When MDDIS is
High, the MDIO read and write operations are
disabled and the Hardware Control Interface provides
primary configuration control. When MDDIS is Low,
the MDIO port is enabled for both read and write
operations and the Hardware Control Interface is not
used.
Configuration Management
Interface
MDIO Addressing
The LXT971 provides both an MDIO interface and a
Hardware Control Interface for device configuration and
management.
The protocol allows one controller to communicate
with multiple LXT971 chips. Pins ADDR<4:0>
determine the chip address.
MDIO Frame Structure
MDIO Management Interface
The physical interface consists of a data line (MDIO)
and clock line (MDC). The frame structure is shown
in Figures 3 and 4 (read and write). MDIO Interface
timing is shown in Table 35 on page 51.
The LXT971 supports the IEEE 802.3 MII
Management Interface also known as the
Management Data Input/Output (MDIO) Interface.
This interface allows upper-layer devices to monitor
and control the state of the LXT971. The MDIO
Figure 3: Management Interface Read Frame Structure
MDC
MDIO
(Read)
A4
A3
A0
R4
R3
R0
D14
D1
D15
D0
Z
0
32 "1"s
0
1
1
0
Turn
Around
Data
Read
Idle
Preamble
ST
Op Code
PHY Address
Register Address
High
Z
Write
Figure 4: Management Interface Write Frame Structure
MDC
MDIO
(Write)
A4
A3
A0
R4
R3
R0
D15
D14
D1
D0
32 "1"s
0
1
0
1
0
1
Turn
Around
Idle
Preamble
ST
Op Code
PHY Address
Register Address
Data
Idle
Write
13
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
MII Interrupts
Hardware Control Interface
The LXT971 provides a single interrupt pin (MDINT).
Interrupt logic is shown in Figure 5. The LXT971 also
provides two dedicated interrupt registers. Register 18
provides interrupt enable and mask functions and Reg-
ister 19 provides interrupt status. Setting bit 18.1 = 1,
enables the device to request interrupt via the MDINT
pin. An active Low on this pin indicates a status
change on the LXT971. Interrupts may be caused by
four conditions:
The LXT971 provides a Hardware Control Interface
for applications where the MDIO is not desired. The
Hardware Control Interface uses the three LED driver
pins to set device configuration. Refer to the
Hardware Configuration Settings section on page 17
for additional details.
• Auto-negotiation complete
• Speed status change
• Duplex status change
• Link status change
Figure 5: Interrupt Logic
Event X Mask Reg
AND
Event X Status Reg
OR
Interrupt Pin (MDINT)
NAND
.
.
.
Per Event
Force Interrupt
Interrupt Enable
1. Interrupt (Event) Status Register is cleared on read.
14
ꢀ
LXT971 Functional Description
values of the MDIO registers. Once the initial values are
set, bit control reverts to the MDIO interface.
Operating Requirements
Power Requirements
Hardware Control Mode
The LXT971 requires three power supply inputs (VCCD,
VCCA, and VCCIO). The digital and analog circuits
require 3.3V supplies (VCCD and VCCA). These inputs
may be supplied from a single source. Each supply input
must be decoupled to ground.
In the Hardware Control Mode, LXT971 disables direct
write operations to the MDIO registers via the MDIO
Interface. On power-up or hardware reset the LXT971
reads the Hardware Control Interface pins and sets the
MDIO registers accordingly.
An additional supply may be used for the MII (VCCIO).
The supply may be either +2.5V or +3.3V. Also, the inputs
on the MII interface are tolerant to 5V signals from the
controller on the other side of the MII interface. Refer to
Table 19 on page 40 for MII I/O characteristics.
The following modes are available using either Hardware
Control or MDIO Control:
• Force network link to 100FX (Fiber).
• Force network link operation to:
100TX, Full-Duplex.
100TX, Half-Duplex.
10BASE-T, Full-Duplex.
As a matter of good practice, these supplies should be as
clean as possible.
10BASE-T, Half-Duplex.
Clock Requirements
• Allow auto-negotiation / parallel-detection.
When the network link is forced to a specific configuration,
the LXT971 immediately begins operating the network
interface as commanded. When auto-negotiation is
enabled, the LXT971 begins the auto-negotiation / parallel-
detection operation.
External Crystal/Oscillator
The LXT971 requires a reference clock input. It may
be provided by either of two methods: by connecting
a crystal across the oscillator pins (XI and XO), or by
connecting an external clock source to pin XI. When a
clock is supplied to XI, XO is left open.
Figure 6: Initialization Sequence
A crystal is typically used in NIC applications. An
external 25 MHz clock source, rather than a crystal, is
frequently used in switch applications. Refer to
Preliminary Test Specifications, Table 20 on page 40,
for clock timing requirements.
Power-up or Reset
Read H/W Control
Interface
Initialize MDIO Registers
MDIO Clock
The MII management channel (MDIO) also requires
an external clock. The managed data clock (MDC)
speed is a maximum of 8 MHz. Refer to Table 35 on
page 51 for details.
MDIO Control
Mode
Hardware Control
Mode
MDDIS Voltage
Level?
Low
High
MDIO Controlled Operation
(MDIO Writes Enabled)
Disable MDIO Read and
Write Operations
Initialization
No
Software
Reset?
When the LXT971 is first powered on, reset, or encounters
a link failure state, it checks the MDIO register
configuration bits to determine the line speed and operating
conditions to use for the network link. The configuration
bits may be set by the Hardware Control or MDIO interface
as shown in Figure 6.
Yes
Reset MDIO Registers to
values read at H/W
Control Interface at last
Hardware Reset
MDIO Control Mode
In the MDIO Control mode, the LXT971 reads the
Hardware Control Interface pins to set the initial (default)
15
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Reduced Power Modes
Reset
The LXT971 offers two power-down modes and a sleep
mode.
The LXT971 provides both hardware and software resets.
Configuration control of Auto-Negotiation, speed and
duplex mode selection is handled differently for each.
During a hardware reset, Auto-Negotiation and Speed
configuration settings are read in from pins (refer to
Table 8 on page 17 for pin settings and to Table 40 on
page 56 for register bit definitions).
Hardware Power Down
The hardware power-down mode is controlled by the
PWRDWN pin. When PWRDWN is High, the follow-
ing conditions are true:
• The LXT971 network port and clock are shut
down.
During a software reset (0.15 = 1), these bit settings are not
re-read from the pins. They revert back to the values that
were read in during the last hardware reset. Therefore, any
changes to pin values made since the last hardware reset
will not be detected during a software reset.
• All outputs are tri-stated.
• All weak pad pull-up and pull-down resistors are
disabled.
• The MDIO registers are not accessible.
During
a hardware reset, register information is
unavailable for 1 ms after de-assertion of the reset. During
a software reset (0.15 = 1) the registers are available for
reading. The reset bit should be polled to see when the part
has completed reset (0.15 = 0).
Software Power Down
Software power-down control is provided by bit 0.11
in the Control Register (refer to Table 40 on page 56).
During soft power-down, the following conditions are
true:
• The network port is shut down.
• The MDIO registers remain accessible.
Sleep Mode
The LXT971 supports a power-saving sleep mode.
Sleep mode is enabled when SLEEP is asserted via
pin 32(LQFP)/H7(PBGA). The value of pin 32/H7
can be overridden by register bit 16.6 when in
managed mode as shown in Table 4 on page 9. The
LXT971 enters into sleep mode when SLEEP is
enabled and no energy is detected on the twisted-pair
input for 1-3 seconds (the time is controlled by bits
16.4:3 in the Configuration Register, with a default of
3.04 seconds).
During this mode the LXT971 will still respond to
management transactions (MDC/MDIO). In this
mode the power consumption is minimized, and the
supply current is reduced below the maximum value
given in Table 17 on page 39. If the LXT971 detects
activity on the twisted-pair inputs, it will come out of
the sleep state and check for link. If no link is
detected in 1-3 seconds (programmable) it will revert
back to the low power sleep state.
NOTE
Sleep Mode is not functional in fiber network
applications.
16
ꢀ
LXT971 Functional Description
Figure 7: Hardware Configuration Settings
Hardware Configuration Settings
The LXT971 provides a hardware option to set the initial
device configuration. The hardware option uses the three
LED driver pins. This provides three control bits, as listed
in Table 8. The LED drivers can operate as either open-
drain or open-source circuits as shown in Figure 7.
3.3V
Configuration Bit = 1
LED/CFG Pin
.
LED/CFG Pin
Configuration Bit = 0
1. The
LED/CFG
pins
will
automatically adjust their polarity
upon power-up or reset.
Table 8: Hardware Configuration Settings
Resulting Register Bit Values
LED/CFGn
Desired Mode
Pin Settings1
Control Register
AN Advertisement Registers
Auto-
Neg
Speed
(Mbps)
AutoNeg Speed
FD
0.8
100FD 100TX
4.8 4.7
10FD
4.6
10T
4.5
Duplex
1
2
3
0.12
0.13
Disabled
10
Half
Full
Half
Full
Half
Full
Low Low Low
Low Low High
Low High Low
Low High High
High Low Low
High Low High
High High Low
0
0
0
1
0
1
0
1
0
N/A
Auto-Negotiation Advertisement
100
1
1
Enabled 100 Only
10/100
1
0
1
0
1
1
1
0
0
0
0
0
1
Half
Only
Full or
Half
High High High
1
1
1
1
1
1. Refer to Table 7 on page 10 for LED/CFG pin assignments.
17
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Next Page Exchange
Establishing Link
Additional information, above that required by base
page exchange is also sent via “Next Pages’. The
LXT971 fully supports the IEEE 802.3ab method of
negotiation via Next Page exchange.
See Figure 8 for an overview of link establishment.
Auto-Negotiation
If not configured for forced operation, the LXT971
attempts to auto-negotiate with its link partner by sending
Fast Link Pulse (FLP) bursts. Each burst consists of up to
33 link pulses spaced 62.5 µs apart. Odd link pulses (clock
pulses) are always present. Even link pulses (data pulses)
may be present or absent to indicate a “1” or a “0”. Each
FLP burst exchanges 16 bits of data, which are referred to
as a “link code word”. All devices that support auto-
negotiation must implement the “Base Page” defined by
IEEE 802.3 (registers 4 and 5). LXT971 also supports the
optional “Next Page” function as described in Tables 47
and 48 on page 62 (registers 7 and 8).
Controlling Auto-Negotiation
When auto-negotiation is controlled by software, the
following steps are recommended:
• After power-up, power-down, or reset, the
power-down recovery time, as specified in
Table 37 on page 52, must be exhausted before
proceeding.
• Set the auto-negotiation advertisement register
bits.
• Enable auto-negotiation (set MDIO bit 0.12 = 1).
Parallel Detection
Base Page Exchange
By exchanging Base Pages, the LXT971 and its link
partner communicate their capabilities to each other.
Both sides must receive at least three identical base
pages for negotiation to continue. Each side identifies
the highest common capabilities that both sides
support and configures itself accordingly.
For the parallel detection feature of auto-negotiation, the
LXT971 also monitors for 10BASE-T Normal Link Pulses
(NLP) and 100BASE-TX Idle symbols. If either is
detected, the device automatically reverts to the
corresponding operating mode. Parallel detection allows
the LXT971 to communicate with devices that do not
support auto-negotiation.
Figure 8: Link Establishment Overview
Power-Up, Reset,
waking up from
Sleep mode, or
Link Failure
Start
Disable
Auto-Negotiation
Enable
0.12 = 0
0.12 = 1
Auto-Neg/Parallel Detection
Check Value
0.12
Go To Forced
Settings
Attempt Auto-
Negotiation
Listen for 100TX
Idle Symbols
Listen for 10T
Link Pulses
YES
NO
Done
Link Up?
18
ꢀ
LXT971 Functional Description
MII Operation
The LXT971 device implements the Media Independent
Interface (MII) as defined in the IEEE 802.3 standard.
Separate channels are provided for transmitting data from
the MAC to the LXT971 (TXD), and for passing data
received from the line (RXD) to the MAC. Each channel
has its own clock, data bus, and control signals. Nine
signals are used to pass received data to the MAC:
RXD<3:0>, RX_CLK, RX_DV, RX_ER, COL, and CRS.
Seven signals are used to transmit data from the MAC:
TXD<3:0>, TX_CLK, TX_EN, and TX_ER.
Receive Data Valid
The LXT971 asserts RX_DV when it receives a valid
packet. Timing changes depend on line operating speed:
• For 100TX links, RX_DV is asserted from the first
nibble of preamble to the last nibble of the data
packet.
• For 10BT links, the entire preamble is truncated.
RX_DV is asserted with the first nibble of the Start of
Frame Delimiter (SFD) “5D” and remains asserted
until the end of the packet.
The LXT971 supplies both clock signals as well as separate
outputs for carrier sense and collision. Data transmission
across the MII is normally implemented in 4-bit-wide
nibbles.
Carrier Sense
Carrier Sense (CRS) is an asynchronous output. It is always
generated when a packet is received from the line and in
half-duplex mode when a packet is transmitted. Table 9
summarizes the conditions for assertion of carrier sense,
collision, and data loopback signals.
MII Clocks
The LXT971 is the master clock source for data
transmission and supplies both MII clocks (RX_CLK and
TX_CLK). It automatically sets the clock speeds to match
link conditions. When the link is operating at 100 Mbps,
the clocks are set to 25 MHz. When the link is operating at
10 Mbps, the clocks are set to 2.5 MHz. Figures 9 through
11 show the clock cycles for each mode. The transmit data
and control signals must always be synchronized to
TX_CLK by the MAC. The LXT971 samples these signals
on the rising edge of TX_CLK.
Carrier sense is not generated when a packet is transmitted
and in full-duplex mode.
Error Signals
When LXT971 is in 100 Mbps mode and receives an
invalid symbol from the network, it asserts RX_ER and
drives “1110” on the RXD pins.
When the MAC asserts TX_ER, the LXT971 will drive
“H” symbols out on the TPFOP/N pins.
Transmit Enable
The MAC must assert TX_EN the same time as the first
nibble of preamble, and de-assert TX_EN after the last bit
of the packet.
Collision
The LXT971 asserts its collision signal, asynchronously to
any clock, whenever the line state is half-duplex and the
transmitter and receiver are active at the same time. Table 9
summarizes the conditions for assertion of carrier sense,
collision, and data loopback signals.
19
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 9: 10BASE-T Clocking
2.5 MHz during Auto-Negotiation and 10BASE-T Data & Idle
TX_CLK
(Sourced by LXT971)
2.5 MHz during Auto-Negotiation and 10BASE-T Data & Idle
RX_CLK
(Sourced by LXT971)
Constant 25 MHz
XI
Figure 10:100BASE-X Clocking
25 MHz once 100BASE-X
Link Established
2.5 MHz during Auto-Negotiation
TX_CLK
(Sourced by LXT971)
25 MHz once 100BASE-X
Link Established
2.5 MHz during Auto-Negotiation
RX_CLK
(Sourced by LXT971)
Constant 25 MHz
XI
20
ꢀ
LXT971 Functional Description
Figure 11: Link Down Clock Transition
Link Down condition/Auto Negotiate Enabled
RX_CLK
TX_CLK
2.5 MHz Clock
Any Clock
Clock transition time will not exceed 2X the
nominal clock period: (10 Mbps = 2.5 MHz 100 Mbps = 25 MHz)
Test loopback is available for both 100TX and 10T
operation. Test loopback is enabled by setting bits as
follows:
Loopback
The LXT971 provides two loopback functions, operational
and test (see Table 9). Loopback paths are shown in
Figure 12.
• 0.14 = 1
• 0.8 = 1 (full-duplex)
Operational Loopback
• 0.12 = 0 (disable auto-negotiation).
Operational loopback is provided for 10 Mbps half-
duplex links when bit 16.8 = 0. Data transmitted by
the MAC (TXData) will be looped back on the receive
side of the MII (RXData). Operational loopback is not
provided for 100 Mbps links, full-duplex links, or
when 16.8 = 1.
Figure 12:Loopback Paths
LXT971
FX Driver
Test Loopback
10T
Loopback
Digital
Block
100X
Loopback
Analog
Block
MII
A test loopback function is provided for diagnostic
testing of the LXT971. During test loopback, twisted-
pair and fiber interfaces are disabled. Data transmitted
by the MAC is internally looped back by the LXT971
and returned to the MAC.
TX Driver
Table 9: Carrier Sense, Loopback, and Collision Conditions
Test1
Operational
Loopback
Speed
Duplex Condition
Carrier Sense
Collision
Loopback
100 Mbps
Full-Duplex
Receive Only
Transmit or Receive
Receive Only
Yes
No
No
No
No
Yes
No
None
Half-Duplex
Transmit and Receive
None
10 Mbps
Full-Duplex
Yes
Yes
No
Half-Duplex, 16.8 = 0
Half-Duplex, 16.8 = 1
Transmit or Receive
Transmit or Receive
Transmit and Receive
Transmit and Receive
1. Test Loopback is enabled when 0.14 = 1
21
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
In 100TX mode, the LXT971 scrambles and transmits the
100 Mbps Operation
data to the network using MLT-3 line code (Figure 14 on
page 23). MLT-3 signals received from the network are
descrambled, decoded, and sent across the MII to the
MAC.
100BASE-X Network Operations
During 100BASE-X operation, the LXT971 transmits and
receives 5-bit symbols across the network link. Figure 13
shows the structure of a standard frame packet. When the
MAC is not actively transmitting data, the LXT971 sends
out Idle symbols on the line.
In 100FX mode, the LXT971 transmits and receives NRZI
signals across the PECL interface. An external 100FX
transceiver module is required to complete the fiber
connection. To enable 100FX operation, auto-negotiation
must be disabled and FX selected.
Figure 13:100BASE-X Frame Format
64-Bit Preamble
(8 Octets)
Destination and Source
Address (6 Octets each)
Packet Length
(2 Octets)
Data Field
(Pad to minimum packet size)
Frame Check Field InterFrame Gap / Idle Code
(4 Octets)
(> 12 Octets)
CRC
IFG
SFD
P0
P1
P6
DA
DA
SA
SA
L1
L2
D0
D1
Dn
I0
Replaced by
/T/R/ code-groups
End-of-Stream Delimiter (ESD)
Replaced by
Start-of-Frame
Delimiter (SFD)
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
.
22
ꢀ
LXT971 Functional Description
Figure 14:100BASE-TX Data Path
Standard Data Flow
+1
Parallel
D0
to
0
0
0
Serial
Scramble
D1
-1
4B/5B
MLT3
D0 D1 D2 D3
S0 S1 S2 S3 S4
De-
Scramble
D2
Transition = 1.
No Transition = 0.
Serial
to
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
D3
Parallel
Scrambler Bypass Data Flow
S0
+1
Parallel
to
Serial
S1
0
0
0
-1
MLT3
S2
S0 S1 S2 S3 S4
Transition = 1.
No Transition = 0.
Serial
to
S3
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
Parallel
S4
23
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
As shown in Figure 13 on page 22, the MAC starts each
transmission with a preamble pattern. As soon as the
LXT971 detects the start of preamble, it transmits a Start-
of-Stream Delimiter (SSD, symbols J and K) to the
network. It then encodes and transmits the rest of the
packet, including the balance of the preamble, the SFD,
packet data, and CRC.
Once the packet ends, the LXT971 transmits the End-of-
Stream Delimiter (ESD, symbols T and R) and then returns
to transmitting Idle symbols. 4B/5B coding is shown in
Table 10 on page 27.
Figure 15 shows normal reception with no errors. When the
LXT971 receives invalid symbols from the line, it asserts
RX_ER as shown in Figure 16.
Figure 15:100BASE-TX Reception with no Errors
RX_CLK
RX_DV
preamble SFD SFD DA
DA
DA
DA
CRC
CRC
CRC
CRC
RXD<3:0>
RX_ER
Figure 16:100BASE-TX Reception with Invalid Symbol
RX_CLK
RX_DV
preamble SFD SFD DA
DA
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
RXD<3:0>
RX_ER
24
ꢀ
LXT971 Functional Description
Collision Indication
Figure 17 shows normal transmission. Upon detection of a
collision, the COL output is asserted and remains asserted
for the duration of the collision as shown in Figure 18.
Figure 17:100BASE-TX Transmission with no Errors
TX_CLK
TX_EN
TXD<3:0>
CRS
P
R
E
A
M
B
L
E
DA DA DA DA DA DA DA DA DA
COL
Figure 18:100BASE-TX Transmission with Collision
TX_CLK
TX_EN
TXD<3:0>
CRS
P
R
E
A
M
B
L
E
JAM
JAM
JAM
JAM
COL
25
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Preamble Handling
100BASE-X Protocol Sublayer
Operations
When the MAC asserts TX_EN, the PCS substitutes a
/J/K symbol pair, also known as the Start-of-Stream
Delimiter (SSD), for the first two nibbles received
across the MII. The PCS layer continues to encode
the remaining MII data, following the coding in
Table 10, until TX_EN is de-asserted. It then returns
to supplying IDLE symbols to the line driver.
With respect to the 7-layer communications model, the
LXT971 is a Physical Layer 1 (PHY) device. The LXT971
implements the Physical Coding Sublayer (PCS), Physical
Medium Attachment (PMA), and Physical Medium
Dependent (PMD) sublayers of the reference model
defined by the IEEE 802.3u standard. The following
paragraphs discuss LXT971 operation from the reference
model point of view.
In the receive direction, the PCS layer performs the
opposite function, substituting two preamble nibbles
for the SSD.
PCS Sublayer
Dribble Bits
The Physical Coding Sublayer (PCS) provides the
MII interface, as well as the 4B/5B encoding/
decoding function.
The LXT971 handles dribbles bits in all modes. If
between 1-4 dribble bits are received, the nibble will
be passed across the MII, padded with 1s if necessary.
If between 5-7 dribble bits are received, the second
nibble will not be sent onto the MII bus.
For 100TX and 100FX operation, the PCS layer
provides IDLE symbols to the PMD-layer line driver
as long as TX_EN is de-asserted.
Figure 19:Protocol Sublayers
MII Interface
LXT971
PCS
Sublayer
Encoder/Decoder
Serializer/De-serializer
PMA
Sublayer
Link/Carrier Detect
PECL Interface
PMD
Sublayer
Scrambler/
De-scrambler
Fiber Transceiver
100BASE-TX
100BASE-FX
26
ꢀ
LXT971 Functional Description
Table 10: 4B/5B Coding
4B Code
Code Type
5B Code
4 3 2 1 0
Name
Interpretation
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0
1
1 1 1 1 0
0 1 0 0 1
1 0 1 0 0
1 0 1 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 1 0
0 1 1 1 1
1 0 0 1 0
1 0 0 1 1
1 0 1 1 0
1 0 1 1 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 11
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
2
3
4
5
6
DATA
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
undefined
7
8
9
A
B
C
D
E
F
I 1
J 2
IDLE
Idle. Used as inter-stream fill code
0 1 0 1
0 1 0 1
1 1 0 0 0
1 0 0 0 1
0 1 1 0 1
0 0 1 1 1
0 0 1 0 0
Start-of-Stream Delimiter (SSD), part 1 of 2
Start-of-Stream Delimiter (SSD), part 2 of 2
End-of-Stream Delimiter (ESD), part 1 of 2
End-of-Stream Delimiter (ESD), part 2 of 2
Transmit Error. Used to force signaling errors
K 2
T 3
R 3
CONTROL
undefined
undefined
undefined
H 4
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 1 0 0 1
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
INVALID
1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
27
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
PMA Sublayer
Link
Carrier Sense
In 100 Mbps mode, the LXT971 establishes a link
whenever the scrambler becomes locked and remains
locked for approximately 50 ms. Whenever the
scrambler loses lock (receiving less than 12
consecutive idle symbols during a 2 ms window), the
link will be taken down. This provides a very robust
link, essentially filtering out any small noise hits that
may otherwise disrupt the link. Furthermore 100M
idle patterns will not bring up a 10M link.
For 100TX and 100FX links, a start-of-stream
delimiter (SSD) or /J/K symbol pair causes assertion
of carrier sense (CRS). An end-of-stream delimiter
(ESD) or /T/R symbol pair causes de-assertion of
CRS. The PMA layer will also de-assert CRS if IDLE
symbols are received without /T/R; however, in this
case RX_ER will be asserted for one clock cycle
when CRS is de-asserted.
Usage of CRS for Interframe Gap (IFG) timing is not
The LXT971 reports link failure via the MII status
bits (1.2 and 17.10) and interrupt functions. If auto-
negotiation is enabled, link failure causes the LXT971
to re-negotiate.
recommended for the following reasons:
• De-assertion time for CRS is slightly longer than
assertion time. This causes IFG intervals to
appear somewhat shorter to the MAC than it
actually is on the wire.
Link Failure Override
• CRS de-assertion is not aligned with TX_EN de-
assertion on transmit loopbacks in half-duplex
mode.
The LXT971 will normally transmit data packets only
if it detects the link is up. Setting bit 16.14 = 1
overrides this function, allowing the LXT971 to
transmit data packets even when the link is down.
This feature is provided as a diagnostic tool. Note that
auto-negotiation must be disabled to transmit data
packets in the absence of link. If auto-negotiation is
enabled, the LXT971 will automatically transmit FLP
bursts if the link is down.
Receive Data Valid
The LXT971 asserts RX_DV to indicate that the
received data maps to valid symbols. However, RXD
outputs zeros until the received data is decoded and
available for transfer to the controller.
28
ꢀ
LXT971 Functional Description
Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD)
layer provides the signal scrambling and
descrambling, line coding and decoding (MLT-3 for
100TX, Manchester for 10T), as well as receiving,
polarity correction, and baseline wander correction
functions.
Polarity Correction
The 100BASE-TX descrambler automatically detects
and corrects for the condition where the receive signal
at TPFIP and TPFIN is inverted.
Programmable Slew Rate Control
The LXT971 device supports a slew rate mechanism
whereby one of four pre-selected slew rates can be
used. This allows the designer to optimize the output
waveform to match the characteristics of the
magnetics. The slew rate is determined by the
TxSLEW pins as shown in Table 4 on page 9.
Scrambler/Descrambler
The purpose of the scrambler is to spread the signal
power spectrum and further reduce EMI using an
11-bit, data-independent polynomial. The receiver
automatically decodes the polynomial whenever
IDLE symbols are received.
Scrambler Seeding. Once the transmit data (or Idle
symbols) are properly encoded, they are scrambled to
further reduce EMI and to spread the power spectrum
using an 11-bit scrambler seed. Five seed bits are
determined by the PHY address, and the remaining
bits are hard coded in the design.
Fiber PMD Sublayer
The LXT971 provides
a PECL interface for
connection to an external fiber-optic transceiver. (The
external transceiver provides the PMD function for
fiber media.) The LXT971 uses an NRZI format for
the fiber interface. The fiber interface operates at 100
Mbps and does not support 10FL applications.
Scrambler Bypass. The scrambler/descrambler can
be bypassed by setting bit 16.12 = 1. The scrambler is
automatically bypassed when the fiber port is enabled.
Scrambler bypass is provided for diagnostic and test
support.
Baseline Wander Correction
The LXT971 provides a baseline wander correction
function which makes the device robust under all
network operating conditions. The MLT3 coding
scheme used in 100BASE-TX is by definition
“unbalanced”. This means that the average value of
the signal voltage can “wander” significantly over
short time intervals (tenths of seconds). This wander
can cause receiver errors at long-line lengths (100
meters) in less robust designs. Exact characteristics of
the wander are completely data dependent.
The
LXT971
baseline
wander
correction
characteristics allow the device to recover error-free
data while receiving worst-case “killer” packets over
all cable lengths.
29
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
10 Mbps Operation
The LXT971 will operate as a standard 10BASE-T
10T Link Integrity Test
transceiver. The LXT971 supports all the standard 10
Mbps functions. During 10BASE-T (10T) operation, the
LXT971 transmits and receives Manchester-encoded data
across the network link. When the MAC is not actively
transmitting data, the LXT971 drives link pulses onto the
line.
In 10T mode, the LXT971 always transmits link pulses.
When the Link Integrity Test function is enabled (the
normal configuration), it monitors the connection for link
pulses. Once link pulses are detected, data transmission
will be enabled and will remain enabled as long as either
the link pulses or data transmission continue. If the link
pulses stop, the data transmission will be disabled.
In 10T mode, the polynomial scrambler/descrambler is
inactive. Manchester-encoded signals received from the
network are decoded by the LXT971 and sent across the
MII to the MAC.
If the Link Integrity Test function is disabled, the LXT971
will transmit to the connection regardless of detected link
pulses. The Link Integrity Test function can be disabled by
setting bit 16.14 = 1.
The LXT971 does not support fiber connections at 10
Mbps.
Link Failure
Link failure occurs if Link Integrity Test is enabled
and link pulses or packets stop being received. If this
condition occurs, the LXT971 returns to the auto-
negotiation phase if auto-negotiation is enabled. If
the Link Integrity Test function is disabled by setting
16.14 = 1 in the Configuration Register, the LXT971
will transmit packets, regardless of link status.
10T Preamble Handling
The LXT971 offers two options for preamble handling,
selected by bit 16.5. In 10T Mode when 16.5 = 0, the
LXT971 strips the entire preamble off of received packets.
CRS is asserted coincident with SFD. RX_DV is held Low
for the duration of the preamble. When RX_DV is
asserted, the very first two nibbles driven by the LXT971
are the SFD “5D” hex followed by the body of the packet.
10T SQE (Heartbeat)
In 10T mode with 16.5 = 1, the LXT971 passes the
preamble through the MII and asserts RX_DV and CRS
simultaneously. In 10T loopback, the LXT971 loops back
whatever the MAC transmits to it, including the preamble.
By default, the Signal Quality Error (SQE) or heartbeat
function is disabled on the LXT971. To enable this
function, set bit 16.9 = 1. When this function is enabled, the
LXT971 will assert its COL output for 5-15 BT after each
packet. See Figure 32 on page 49 for SQE timing
parameters.
10T Carrier Sense
For 10T links, CRS assertion is based on reception of valid
preamble, and de-assertion on reception of an end-of-frame
(EOF) marker. Bit 16.7 allows CRS de-assertion to be
synchronized with RX_DV de-assertion. Refer to Table 49
on page 63.
10T Jabber
If a transmission exceeds the jabber timer, the LXT971 will
disable the transmit and loopback functions. See Figure 31
on page 49 for jabber timing parameters.
The LXT971 automatically exits jabber mode after the
unjabber time has expired. This function can be disabled by
setting bit 16.10 = 1.
10T Dribble Bits
The LXT971 device handles dribbles bits in all modes. If
between 1-4 dribble bits are received, the nibble will be
passed across the MII, padded with 1s if necessary. If
between 5-7 dribble bits are received, the second nibble
will not be sent onto the MII bus.
10T Polarity Correction
The LXT971 automatically detects and corrects for the
condition where the receive signal (TPFIP/N) is inverted.
Reversed polarity is detected if eight inverted link pulses,
or four inverted end-of-frame (EOF) markers, are received
consecutively. If link pulses or data are not received by the
maximum receive time-out period (96-128 ms), the
polarity state is reset to a non-inverted state.
30
ꢀ
LXT971 Functional Description
Monitoring Operations
Monitoring Auto-Negotiation
LED Functions
Auto-negotiation can be monitored as follows:
The LXT971 incorporates three direct LED drivers. On
power up all the drivers are asserted for approximately 1
second after reset de-asserts. Each LED driver can be
programmed using the LED Configuration Register (refer
to Table 53 on page 67) to indicate one of the following
conditions:
• Bit 17.7 is set to 1 once the Auto-Negotiation process
is completed.
• Bits 1.2 and 17.10 are set to 1 once the link is
established.
• Bits 17.14 and 17.9 can be used to determine the link
operating conditions (speed and duplex).
• Operating Speed
• Transmit Activity
• Receive Activity
• Collision Condition
• Link Status
Monitoring Next Page Exchange
The LXT971 offers an Alternate Next Page mode to
simplify the next page exchange process. Normally,
bit 6.1 (Page Received) remains set until read. When
Alternate Next Page mode is enabled (16.1 = 1), bit
• Duplex Mode
6.1 is automatically cleared whenever
a new
The LED drivers can also be programmed to display vari-
ous combined status conditions. For example, setting bits
20.15:12 = 1101 produces the following combination of
Link and Activity indications:
negotiation process takes place. This prevents the
user from reading an old value in 6.1 and assuming
that Registers 5 and 8 (Partner Ability) contain valid
information. Additionally, the LXT971 uses bit 6.5 to
indicate when the current received page is the base
page. This information is useful for recognizing when
next pages must be resent due to a new negotiation
process starting. Bits 6.1 and 6.5 are cleared when
read.
• If Link is down LED is off.
• If Link is up LED is on.
• If Link is up and activity is detected, the LED will
blink at the stretch interval selected by bits 20.3:2 and
will continue to blink as long as activity is present.
31
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
The LED driver pins also provide initial configuration
settings. The LED pins are sensitive to polarity and will
automatically pull up or pull down to configure for either
open drain or open collector circuits (10 mA Max current
rating) as required by the hardware configuration. Refer to
the discussion of “Hardware Configuration Settings” on
page 17 for details.
When an event such as receiving a packet occurs it will
be edge detected and it will start the stretch timer. The
LED driver will remain asserted until the stretch timer
expires. If another event occurs before the stretch
timer expires then the stretch timer will be reset and
the stretch time will be extended.
When a long event (such as duplex status) occurs it
will be edge detected and it will start the stretch timer.
When the stretch timer expires the edge detector will
be reset so that a long event will cause another pulse to
be generated from the edge detector which will reset
the stretch timer and cause the LED driver to remain
asserted. Figure 20 shows how the stretch operation
functions.
LED Pulse Stretching
The LED Configuration Register also provides
optional LED pulse stretching to 30, 60, or 100 ms. If
during this pulse stretch period, the event occurs again,
the pulse stretch time will be further extended.
Figure 20:LED Pulse Stretching
Event
LED
stretch
stretch
stretch
Note: The direct drive LED outputs in this diagram are shown as active Low.
32
ꢀ
LXT971 Functional Description
Instruction Register
Boundary Scan
After the state machine resets, the IDCODE instruction is
always invoked. The decode logic ensures the correct data
flow to the Data registers according to the current
instruction. Valid instructions are listed in Table 12.
(JTAG1149.1) Functions
LXT971 includes a IEEE 1149.1 boundary scan test port
for board level testing. All digital input, output, and input/
output pins are accessible. The BSDL file is available by
contacting your local sales office (see the back page) or by
accessing the Level One website (www.level1.com).
Boundary Scan Register (BSR)
Each Boundary Scan Register (BSR) cell has two stages. A
flip-flop and a latch are used for the serial shift stage and
the parallel output stage. There are four modes of operation
as listed in Table 11.
Boundary Scan Interface
This interface consists of five pins (TMS, TDI, TDO,
TRST, and TCK). It includes a state machine, data register
array, and instruction register. The TMS and TDI pins are
internally pulled up. TCK is internally pulled down. TDO
does not have an internal pull-up or pull-down.
Table 11: BSR Mode of Operation
Mode
Description
1
2
3
4
Capture
Shift
State Machine
The TAP controller is a 16 state machine driven by the
Update
TCK
and
TMS
pins.
Upon
reset
the
System Function
TEST_LOGIC_RESET state is entered. The state machine
is also reset when TMS and TDI are high for five TCK
periods.
Table 12: Supported JTAG Instructions
Name
EXTEST
Code
Description
External Test
Mode
Data Register
0000
0001
0010
0011
0100
1111
Test
BSR
IDCODE
SAMPLE
TRIBYP
SETBYP
BYPASS
ID Code Inspection
Sample Boundary
Force Float
Normal
Normal
Normal
Test
ID REG
BSR
Bypass
Bypass
Bypass
Control Boundary to 1/0
Bypass Scan
Normal
Table 13: Device ID Register
31:28
Version
0001
27:12
Part ID (hex)
03CB
11:8
7:1
0
Reserved
1
JEDEC ID1
Jedec Continuation Characters
1110
111 1110
1. The JEDEC IS is an 8-bit identifier. The MSB is for parity and is ignored. Level One’s JEDEC ID is FE (1111 1110) which becomes 111 1110
33
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
APPLICATION INFORMATION
Magnetics Information
The LXT971 requires a 1:1 ratio for both the receive
and transmit transformers. The transformer isolation
voltage should be rated at 2 kV to protect the circuitry
from static voltages across the connectors and cables.
Refer to Table 14 for transformer requirements.
A cross-reference list of magnetic manufacturers and
part numbers is available in Application Note 073,
Magnetic Manufacturers, which can be found on the
Level One web site (www.level1.com). Before
committing to a specific component, designers should
contact the manufacturer for current product
specifications, and validate the magnetics for the
specific application.
Table 14: Magnetics Requirements
Parameter
Min
Nom
Max
Units
Test Condition
Rx turns ratio
Tx turns ratio
Insertion loss
–
–
1 : 1
1 : 1
0.6
–
–
–
–
–
0.0
350
–
1.1
–
dB
µH
kV
dB
dB
dB
dB
Primary inductance
Transformer isolation
1.5
–
–
Differential to common mode rejection
40
35
-16
-10
–
.1 to 60 MHz
–
–
60 to 100 MHz
30 MHz
Return Loss
–
–
–
–
80 MHz
Typical Twisted-Pair Interface
Table 15 provides a comparison of the RJ-45
connections for NIC and Switch applications in a
typical twisted-pair interface setting.
Figure 21 on page 35 shows a typical twisted-pair
interface with the RJ-45 connections crossed over for
a Switch configuration. Figure 22 on page 36
provides a typical twisted-pair interface with the RJ-
45 connections configured for a NIC application.
Table 15: I/O Pin Comparison of NIC and
Switch RJ-45 Setups
RJ-45
Symbol
Switch
NIC
TPIP
TPIN
TPOP
TPON
1
2
3
6
3
6
1
2
34
ꢀ
LXT971 Application Information
Figure 21:Typical Twisted-Pair Interface - Switch
270 pF 5%
TPFIP
RJ-45
50Ω 1%
1:1
1
2
3
0.01
µ
F
3
50Ω 1%
TPFIN
50
Ω
50
50
Ω
Ω
4
5
6
7
8
270 pF 5%
TPFOP
1:1
2
LXT971
50
50
Ω
Ω
µ
0.1 F
50
Ω
TPFON
1
* = 0.001
µ
F / 2.0 kV
*
*
4
VCCA
GND
µ
.01 F
µ
0.1 F
SD/TP
1. Center-tap current may be supplied from 3.3V VCCA as shown. Additional power savings may be
realized by supplying the center-tap from a 2.5V current source. A separate ferrite bead (rated at 50 mA)
should be used to supply center-tap current.
2. The 100Ω transmit load termination resistor typically required is integrated in the LXT971.
3. Magnetics without a receive pair center-tap do not require a 2 kV termination.
4. RJ-45 connections shown are for a standard switch application. For a standard NIC RJ-45 setup, see
Figure 22.
35
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 22:Typical Twisted-Pair Interface - NIC
RJ-45
50
Ω
50
50
Ω
Ω
270 pF 5%
8
7
6
5
4
3
2
1
TPFIN
50Ω 1%
1:1
50
50
Ω
Ω
0.01
µF
3
50
Ω
50Ω 1%
TPFIP
270 pF 5%
TPFON
1:1
LXT971
2
0.1µF
4
TPFOP
1
* = 0.001
µF / 2.0 kV
*
*
VCCA
GND
.01µF
0.1µF
SD/TP
1. Center-tap current may be supplied from 3.3V VCCA as shown. Additional power savings may be realized by
supplying the center-tap from a 2.5V current source. A separate ferrite bead (rated at 50 mA) should be used to
supply center-tap current.
2. The 100Ω transmit load termination resistor typically required is integrated in the LXT971.
3. Magnetics without a receive pair center-tap do not require a 2 kV termination.
4. RJ-45 connections shown for standard NIC. Tx/Rx crossover may be required for repeater & switch
applications.
36
ꢀ
LXT971 Application Information
Figure 23:Typical MII Interface
TX_EN
TX_ER
TXD<3:0>
TX_CLK
RX_CLK
X
MAC
LXT971
F
RX_DV
RJ-45
RX_ER
M
R
RXD<3:0>
CRS
COL
37
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 24:Typical Fiber Interface
VCCD
+3.3V
16
Ω
Ω
0.1
µ
F
50
Ω
50
GND
TPFON
TPFOP
TD-
TD+
VCCD
+3.3V
LXT971
Fiber Txcvr
130
Ω
SD/TP
SD
VCCD
+3.3V
82
Ω
1
0.1
µ
F
GND 130
Ω
130
Ω
GND
TPFIN
TPFIP
RD-
RD+
82
Ω
82
Ω
GND
1. Refer to fiber transceiver manufacturer’s recommendations for termination circuitry.
Example shown above is suitable for HFBR5900-series devices.
38
ꢀ
LXT971 Preliminary Test Specifications
PRELIMINARY TEST SPECIFICATIONS
NOTE
Tables 16 through 37 and Figures 25 through Figure 38 represent the performance specifications of the LXT971.
These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values
listed in Tables 18 through 37 apply over the recommended operating conditions specified in Table 17.
Electrical Parameters
Table 16: Absolute Maximum Ratings
Parameter
Supply voltage
Sym
Min
Max
Units
VCC
-0.3
0
4.0
V
Operating temperature
LXT971_C
TOPA
+70
ºC
(Commercial)
LXT971_E
(Extended)
TOPA
-40
-65
+85
ºC
ºC
Storage temperature
TST
+150
CAUTION
Exceeding these values may cause permanent damage.
Functional operation under these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 17: Operating Conditions
Parameter
Typ1
Sym
Min
Max
Units
Recommended operating temperature
LXT971_C
(Commercial)
TOPA
0
–
70
ºC
ºC
LXT971_E
(Extended)
TOPA
-40
–
85
Recommended supply voltage2
VCC current
Analog & Digital
I/O
VCCA, VCCD
VCCIO
ICC
3.14
3.3
–
3.45
3.45
110
82
V
2.35
–
V
100BASE-TX
10BASE-T
–
mA
mA
mA
mA
mA
mA
ICC
–
–
100BASE-FX
Sleep Mode
Power Down
Auto-Negotiation
ICC
–
–
95
ICC
–
–
45
ICC
–
–
1
ICC
–
–
110
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Voltages with respect to ground unless otherwise specified.
39
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
1
Table 18: Digital I/O Characteristics
Typ2
Parameter
Symbol
Min
Max
Units
Test Conditions
VIL
VIH
–
–
–
0.8
–
V
V
–
–
Input Low voltage
2.0
Input High voltage
Input current
II
-10
–
–
–
–
10
0.4
–
µA
V
0.0 < VI < VCC
Output Low voltage
Output High voltage
VOL
VOH
IOL = 4 mA
IOH = -4 mA
2.4
V
1. Applies to all pins except MII , LED and XI/XO pins. Refer to Table 19 for MII I/O Characteristics, Table 20 for XI/XO and Table 21 for LED
Characteristics.
2. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 19: Digital I/O Characteristics - MII Pins
Typ1
Parameter
Symbol
Min
Max
Units
Test Conditions
Input Low voltage
VIL
VIH
II
–
2.0
-10
–
–
–
0.8
–
V
V
–
–
Input High voltage
Input current
–
10
0.4
–
µA
V
0.0 < VI < VCCIO
Output Low voltage
Output High voltage
VOL
VOH
VOH
–
IOL = 4 mA
2.4
2.0
–
–
V
IOH = -4 mA, VCCIO = 3.3V
IOH = -4 mA, VCCIO = 2.5V
VCCIO = 2.5V
–
–
V
2
Driver output resistance
(Line driver output enabled)
100
–
Ω
RO
2
–
100
–
VCCIO = 3.3V
Ω
RO
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Parameter is guaranteed by design; not subject to production testing.
Table 20: I/O Characteristics - REFCLK/XI and XO Pins
Typ1
Parameter
Sym Min
Max Units
Test Conditions
Input Low Voltage
VIL
VIH
–
2.0
–
–
–
–
0.8
–
V
V
Input High Voltage
Input Clock Frequency Tolerance2
f
∆
ppm
±100
Input Clock Duty Cycle2
Input Capacitance
TDC
CIN
40
–
–
60
–
%
3.0
pF
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Parameter is guaranteed by design; not subject to production testing.
40
ꢀ
LXT971 Preliminary Test Specifications
Table 21: I/O Characteristics - LED/CFG Pins
Parameter
Sym
Min
Max
Units
Test Conditions
IOL = 10 mA
Typ
Output Low Voltage
Output High Voltage
Input Current
VOL
VOH
II
–
–
–
–
0.4
–
V
V
2.4
-10
IOH = -10 mA
10
µA
0 < VI < VCCIO
Table 22: 100BASE-TX Transceiver Characteristics
Typ1
Parameter
Sym
Min
Max
Units
Test Conditions
Peak differential output voltage
Signal amplitude symmetry
Signal rise/fall time
VP
Vss
0.95
98
3.0
–
–
–
1.05
102
5.0
0.5
65
V
%
ns
ns
%
Note 2
Note 2
Note 2
Note 2
TRF
TRFS
DCD
–
Rise/fall time symmetry
Duty cycle distortion
–
35
50
Offset from 16ns pulse width at
50% of pulse peak
Overshoot/Undershoot
VOS
–
–
–
–
–
5
%
ns
–
–
Jitter (measured differentially)
1.4
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Measured at the line side of the transformer, line replaced by 100Ω(+/-1%) resistor.
Table 23: 100BASE-FX Transceiver Characteristics
Typ1
Parameter
Sym
Min
Max
Units
Test Conditions
Transmitter
Peak differential output voltage
(single ended)
VOP
0.6
–
1.5
V
–
Signal rise/fall time
TRF
–
–
–
–
–
1.9
1.3
ns
ns
10 <–> 90% 2.0 pF load
–
Jitter (measured differentially)
Receiver
Peak differential input voltage
Common mode input range
VIP
0.55
–
–
–
1.5
V
V
–
–
VCMIR
VCC - 0.7
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
41
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Table 24: 10BASE-T Transceiver Characteristics
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Transmitter
2.2
Peak differential output voltage
VOP
2.5
2.8
V
With transformer, line
replaced by 100 Ω
resistor
Transition timing jitter added by the
MAU and PLS sections
-
0
2
11
ns
After line model spec-
ified by IEEE 802.3
for 10BASE-T MAU
Receiver
IN
Receive Input Impedance
Z
-
-
22
k
Ω
DS
Differential Squelch Threshold
V
300
420
585
mV
Table 25: 10BASE-T Link Integrity Timing Characteristics
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Time Link Loss Receive
Link Pulse
TLL
TLP
50
2
–
–
–
–
–
–
150
7
ms
–
–
–
–
–
–
Link Pulses
Link Min Receive Timer
Link Max Receive Timer
Link Transmit Period
Link Pulse Width
TLR MIN
TLR MAX
TLT
2
7
ms
ms
ms
ns
50
8
150
24
150
TLPW
60
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
42
ꢀ
LXT971 Preliminary Test Specifications
Timing Diagrams
Figure 25:100BASE-TX Receive Timing - 4B Mode
0ns
250ns
TPFI
t4
t5
CRS
t3
RX_DV
t1
t2
RXD<3:0>
RX_CLK
t6
t7
COL
Table 26: 100BASE-TX Receive Timing Parameters - 4B Mode
Units2
Parameter
Sym Min Typ1 Max
Test Conditions
RXD<3:0>, RX_DV, RX_ER setup
to RX_CLK High
t1
t2
10
10
–
–
–
–
ns
–
RXD<3:0>, RX_DV, RX_ER hold
from RX_CLK High
ns
–
CRS asserted to RXD<3:0>, RX_DV
Receive start of “J” to CRS asserted
Receive start of “T” to CRS de-asserted
Receive start of “J” to COL asserted
Receive start of “T” to COL de-asserted
t3
t4
t5
t6
t7
3
–
–
–
–
–
5
BT
BT
BT
BT
BT
–
–
–
–
–
12
10
16
17
16
17
22
20
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10 s or 10 ns.
-8
43
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 26:100BASE-TX Transmit Timing - 4B Mode
0ns
250ns
t1
TXCLK
TX_EN
t2
TXD<3:0>
t5
TPFO
t4
t3
CRS
Table 27: 100BASE-TX Transmit Timing Parameters - 4B Mode
Test
Conditions
Units2
Parameter
Sym Min Typ1 Max
TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High
TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High
TX_EN sampled to CRS asserted
t1
t2
t3
t4
t5
12
0
–
–
–
–
–
–
ns
ns
–
–
–
–
–
–
20
24
5.3
24
28
5.7
BT
BT
BT
TX_EN sampled to CRS de-asserted
TX_EN sampled to TPFO out (Tx latency)
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10 s or 10 ns.
-8
44
ꢀ
LXT971 Preliminary Test Specifications
Figure 27:100BASE-FX Receive Timing
0ns
250ns
TPFI
t4
t5
CRS
t3
RX_DV
t1
t2
RXD<3:0>
RX_CLK
t6
t7
COL
Table 28: 100BASE-FX Receive Timing Parameters
Units2
Parameter
Sym Min Typ1 Max
Test Conditions
RXD<3:0>, RX_DV, RX_ER setup
to RX_CLK High
t1
t2
10
10
–
–
–
–
ns
ns
–
RXD<3:0>, RX_DV, RX_ER hold
from RX_CLK High
–
CRS asserted to RXD<3:0>, RX_DV
Receive start of “J” to CRS asserted
Receive start of “T” to CRS de-asserted
Receive start of “J” to COL asserted
Receive start of “T” to COL de-asserted
t3
t4
t5
t6
t7
3
–
–
–
–
–
5
BT
BT
BT
BT
BT
–
–
–
–
–
12
16
10
14
16
22
15
18
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10 s or 10 ns.
-8
45
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 28:100BASE-FX Transmit Timing
0ns
250ns
t1
TXCLK
TX_EN
t2
TXD<3:0>
t5
TPFO
t4
t3
CRS
Table 29: 100BASE-FX Transmit Timing Parameters
Test
Conditions
Units2
Parameter
Sym Min Typ1 Max
TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High
TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High
TX_EN sampled to CRS asserted
t1
t2
t3
t4
t5
12
0
–
–
–
–
–
–
ns
–
–
–
–
–
–
ns
17
22
5
20
24
5.3
BT
BT
BT
TX_EN sampled to CRS de-asserted
TX_EN sampled to TPFO out (Tx latency)
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10 s or 10 ns.
-8
46
ꢀ
LXT971 Preliminary Test Specifications
Figure 29:10BASE-T Receive Timing
RX_CLK
t
1
t
2
t
3
RXD,
RX_DV,
RX_ER
t
5
t
4
CRS
TPFI
t
6
t
t
7
9
t
8
COL
Table 30: 10BASE-T Receive Timing Parameters
Units2
Parameter
Sym Min Typ1 Max
Test Conditions
RXD, RX_DV, RX_ER Setup to RX_CLK
High
t1
t2
10
10
–
–
–
–
ns
–
RXD, RX_DV, RX_ER Hold from RX_CLK
High
ns
–
TPFIP/N in to RXD out (Rx latency)
t3
t4
5.8
5
–
–
6.0
32
–
–
BT
BT
CRS asserted to RXD, RX_DV, RX_ER
asserted
RXD, RX_DV, RX_ER de-asserted to CRS
de-asserted
t5
0.3
–
0.5
BT
–
TPFI in to CRS asserted
t6
t7
t8
t9
2
6
1
5
–
–
–
–
28
10
31
10
BT
BT
BT
BT
–
–
–
–
TPFI quiet to CRS de-asserted
TPFI in to COL asserted
TPFI quiet to COL de-asserted
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10 s or 100 ns.
-7
47
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 30:10BASE-T Transmit Timing
TX_CLK
t
1
t2
TXD,
TX_EN,
TX_ER
t
3
t4
CRS
t
5
TPFO
Table 31: 10BASE-T Transmit Timing Parameters
Units2
Parameter
Sym
Min
Typ1
Max
Test Conditions
TXD, TX_EN, TX_ER setup to TX_CLK High
TXD, TX_EN, TX_ER hold from TX_CLK High
TX_EN sampled to CRS asserted
t1
t2
t3
t4
t5
10
0
–
–
–
–
–
–
–
ns
ns
–
–
–
–
–
–
2
BT
BT
BT
TX_EN sampled to CRS de-asserted
–
1
TX_EN sampled to TPFO out (Tx latency)
–
72.5
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10 s or 100 ns.
-7
48
ꢀ
LXT971 Preliminary Test Specifications
Figure 31:10BASE-T Jabber and Unjabber Timing
TX_EN
t
1
TXD
COL
t
2
Table 32: 10BASE-T Jabber and Unjabber Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
Maximum transmit time
Unjab time
t1
t2
20
–
–
150
750
ms
ms
–
–
250
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Figure 32:10BASE-T SQE (Heartbeat) Timing
TX_CLK
TX_EN
t
1
t
2
COL
Table 33: 10BASE-T SQE Timing Parameters
Parameter
Sym Min Typ1 Max Units
Test Conditions
COL (SQE) Delay after TX_EN off
COL (SQE) Pulse duration
t1
t2
0.65
0.5
–
–
1.6
1.5
us
us
–
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
49
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 33:Auto Negotiation and Fast Link Pulse Timing
Clock Pulse
Data Pulse
Clock Pulse
TPFOP
t1
t1
t3
t2
Figure 34:Fast Link Pulse Timing
FLP Burst
FLP Burst
TPFOP
t4
t5
Table 34: Auto Negotiation and Fast Link Pulse Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
Clock/Data pulse width
Clock pulse to Data pulse
Clock pulse to Clock pulse
FLP burst width
t1
t2
t3
t4
t5
–
–
55.5
123
–
100
–
–
63.8
127
–
ns
µs
µs
ms
ms
ea
–
–
–
–
–
–
–
2
FLP burst to FLP burst
Clock/Data pulses per burst
8
12
–
24
17
33
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
50
ꢀ
LXT971 Preliminary Test Specifications
Figure 35:MDIO Input Timing
MDC
t2
t1
MDIO
Figure 36:MDIO Output Timing
t4
MDC
MDIO
t3
Table 35: MDIO Timing Parameters
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
MDIO setup before MDC,
sourced by STA
t1
10
–
–
–
–
–
ns
–
MDIO hold after MDC,
sourced by STA
t2
t3
t4
5
–
–
150
–
ns
ns
ns
–
MDC to MDIO output delay,
source by PHY
–
MDC period
125
MDC = 8 MHz
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
51
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 37:Power-Up Timing
v1
t1
VCC
MDIO,etc
Table 36: Power-Up Timing Parameters
Parameter
Voltage threshold
Power Up delay2
Sym
Min
Typ1
Max
Units
Test Conditions
v1
t1
–
–
2.9
–
–
V
–
–
300
µs
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. Power Up Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the PHY will come out of reset after
a delay of No MORE Than 300 µs. System designers should consider this as a minimum value - After threshold v1 is reached, the MAC should
delay No LESS Than 300 µs before accessing the MDIO port.
Figure 38:RESET Pulse Width and Recovery Timing
t1
RESET
t2
MDIO,etc
Table 37: RESET Pulse Width and Recovery Timing Parameters
Parameter
RESET pulse width
RESET recovery delay2
Sym
Min
Typ1
Max
Units
Test Conditions
t1
t2
10
–
–
–
ns
–
–
300
µs
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the PHY will come out of reset
after a delay of No MORE Than 300 µs. System designers should consider this as a minimum value - After de-asserting RESET*, the MAC
should delay No LESS Than 300 µs before accessing the MDIO port.
52
ꢀ
LXT971 Register Definitions
REGISTER DEFINITIONS
The LXT971 register set includes multiple 16-bit registers.
Table 38 presents a complete register listing. Table 39 is a
complete memory map of all registers and Tables 40
through 54 provide individual register definitions.
Additional registers are defined in accordance with the
IEEE 802.3 standard for adding unique chip functions.
Base registers (0 through 8) are defined in accordance with
the “Reconciliation Sublayer and Media Independent
Interface” and “Physical Layer Link Signaling for 10/100
Mbps Auto-Negotiation” sections of the IEEE 802.3
standard.
Table 38: Register Set
Address
Register Name
Bit Assignments
0
1
Control Register
Status Register #1
Refer to Table 40 on page 56
Refer to Table 41 on page 57
Refer to Table 42 on page 58
Refer to Table 43 on page 58
Refer to Table 44 on page 59
2
PHY Identification Register 1
3
PHY Identification Register 2
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Base Page Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page Transmit Register
Auto-Negotiation Link Partner Received Next Page Register
1000BASE-T/100BASE-T2 Control Register
1000BASE-T/100BASE-T2 Status Register
Extended Status Register
Refer to Table 45 on page 60
Refer to Table 46 on page 61
Refer to Table 47 on page 62
Refer to Table 48 on page 62
Not Implemented
6
7
8
9
10
15
16
17
18
19
20
21-29
30
Not Implemented
Not Implemented
Port Configuration Register
Refer to Table 49 on page 63
Refer to Table 50 on page 64
Refer to Table 51 on page 65
Refer to Table 52 on page 66
Refer to Table 53 on page 67
Status Register #2
Interrupt Enable Register
Interrupt Status Register
LED Configuration Register
Reserved
Transmit Control Register
Refer to Table 54 on page 69
53
ꢀ
L
T97
Table 39: Register Bit Map
Bit Fields
B8 B7
Control Register
Reg
Title
Addr
V
B15
B14
B13
B12
B11
B10
B9
B6
B5
B4
B3
B2
B1
B0
Speed
Select
A/N
Enable
Power
Down
Re-start Duplex
A/N Mode
Speed
Select
Control
Status
Reset Loopback
Isolate
COL Test
Reserved
0
1
S
pee
Status Register
100Base- 100Base- 10Mbps 10Mbps 100Base- 100Base-
MF
100Base-
T4
Extended
Status
A/N
Complete
Remote
Fault
A/N
Link
Jabber Extended
Detect Capability
X Full
Duplex
X Half
Duplex
Full
Duplex
Half
Duplex
T2 Full T2 Half
Reserved Preamble
Suppress
a
Ability
Status
Duplex
Duplex
stE
PHY ID Registers
PHY ID 1
PHY ID2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
3
e
PHY ID No
MFR Model No
MFR Rev No
n
Auto-Negotiation Advertisement Register
t
Tra
100Base-
TX Full
Duplex
10Base-T
Full
Duplex
A/N
Advertise
Remote
Fault
Asymm
Pause
100Base-
T4
100Base-
TX
Next Page Reserved
Reserved
Reserved
Pause
10Base-T
IEEE Selector Field
IEEE Selector Field
4
5
sce
Auto-Negotiation Link Partner Base Page Ability Register
100Base-
TX Full
Duplex
10Base-T
Full 10Base-T
Duplex
A/N Link
Ability
Remote
Fault
Asymm
Pause
100Base-
T4
100Base-
TX
Next Page
Ack
Pause
r
Auto-Negotiation Expansion Register
Link
Partner Next Page
Parallel
Base Page Detect
Fault
Link
Partner
A/N Able
A/N
Expansion
Page
Received
Reserved
6
NextPage
Able
Able
Auto-Negotiation Next Page Transmit Register
A/N Next
Page Txmit
Message
Page
Next Page Reserved
Ack 2
Ack 2
Toggle
Message / Unformatted Code Field
7
8
Auto-Negotiation Link Partner Next Page Receive Register
A/N Link
Next Page
Message
Page
Next Page
Ack
Toggle
Message / Unformatted Code Field
Configuration Register
Bypass
Scrambler
TP
Loopback
CRS
Select
(10T)
Fault
Code
Enable
Jabber
(10T)
SQE
Force
Link Pass Disable
Txmit
Sleep
Mode
Alternate
Next Page Select
Fiber
Port Config Reserved
Reserved
PRE_EN
Sleep Timer
16
(10T)
(100TX)
(10T)
Table 39: Register Bit Map – continued
Bit Fields
B8 B7
Reg
Title
Addr
B15
B14
B13
B12
B11
B10
B9
B6
B5
B4
B3
B2
B1
B0
Status Register #2
Status
Register #2
10/100 Transmit Receive Collision
Duplex
Mode
Auto-Neg
Auto-Neg
Reserved
Link
Reserved Polarity
Pause
Error
Reserved
Reserved
17
18
19
20
30
Mode
Status
Status
Status
Complete
Interrupt Enable Register
Interrupt
Enable
Auto-Neg Speed
Reserved
Duplex
Mask
Link
Mask
Interrupt
Test
Reserved
Reserved Reserved
Mask
Mask
Enable Interrupt
Interrupt Status Register
Interrupt
Status
Auto-Neg Speed
Reserved
Duplex
Link
MD
Reserved
Reserved
Reserved Reserved
Done
Change Change Change
Interrupt
LED Configuration Register
Pulse
LED Config
LED1
LED2
LED3
LED Freq
Reserved
Stretch
Transmit Control Register
Trans.
Control
Transmit
Low Pwr
Port Rise Time
Control
Reserved
Reserved
X
9
1
r
n
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Table 40: Control Register (Address 0)
Type 1
Bit
0.15
Name
Description
Default
Reset
1 = PHY reset
R/W
SC
0
0 = Normal operation
0.14
0.13
Loopback
1 = Enable loopback mode
0 = Disable loopback mode
R/W
0
Speed Selection
0.6
0.13
Speed Selected
R/W
Note 2
1
1
0
0
1
0
1
0
Reserved
1000 Mbps (not supported)
100 Mbps
10 Mbps
0.12
0.11
0.10
0.9
Auto-Negotiation 1 = Enable Auto-Negotiation Process
R/W
R/W
R/W
Note 2
Enable
0 = Disable Auto-Negotiation Process
Power-Down
1 = Power-down
0
0
0
0 = Normal operation
Isolate
1 = Electrically isolate PHY from MII
0 = Normal operation
Restart
1 = Restart Auto-Negotiation Process
0 = Normal operation
R/W
SC
Auto-Negotiation
Duplex Mode
0.8
0.7
0.6
1 = Full Duplex
0 = Half Duplex
R/W
Note 2
Collision Test
1 = Enable COL signal test
0 = Disable COL signal test
R/W
R/W
0
0
Speed Selection
0.6
0.13
Speed Selected
1
1
0
0
1
0
1
0
Reserved
1000 Mbps (not supported)
100 Mbps
10 Mbps
0.5:0
Reserved
Write as 0, ignore on Read
R/W
00000
1. R/W = Read/Write
RO = Read Only
SC = Self Clearing
2. Default value of bits 0.12, 0.13 and 0.8 are determined by the LED/CFGn pins (refer to Table 8 on page 17).
56
ꢀ
LXT971 Register Definitions
Table 41: MII Status Register #1 (Address 1)
Type 1
Bit
1.15
Name
Description
Default
100BASE-T4
1 = PHY able to perform 100BASE-T4
0 = PHY not able to perform 100BASE-T4
RO
0
Not Supported
1.14
1.13
1.12
1.11
1.10
100BASE-X Full-
Duplex
1 = PHY able to perform full-duplex 100BASE-X
0 = PHY not able to perform full-duplex 100BASE-X
RO
RO
RO
RO
RO
1
1
1
1
0
100BASE-X Half-
Duplex
1 = PHY able to perform half-duplex 100BASE-X
0 = PHY not able to perform half-duplex 100BASE-X
10 Mbps Full-Duplex 1 = PHY able to operate at 10 Mbps in full-duplex mode
0 = PHY not able to operate at 10 Mbps full-duplex mode
10 Mbps Half-Duplex 1 = PHY able to operate at 10 Mbps in half-duplex mode
0 = PHY not able to operate at 10 Mbps in half-duplex
100BASE-T2 Full-
Duplex
1 = PHY able to perform full-duplex 100BASE-T2
0 = PHY not able to perform full-duplex 100BASE-T2
Not Supported
1.9
100BASE-T2 Half-
Duplex
1 = PHY able to perform half duplex 100BASE-T2
0 = PHY not able to perform half-duplex 100BASE-T2
RO
0
Not Supported
1.8
Extended Status
1 = Extended status information in register 15
0 = No extended status information in register 15
RO
0
1.7
1.6
Reserved
1 = ignore when read
RO
RO
0
0
MF Preamble Sup-
pression
1 = PHY will accept management frames with preamble sup-
pressed
0 = PHY will not accept management frames with preamble
suppressed
1.5
1.4
1.3
1.2
1.1
1.0
Auto-Negotiation
complete
1 = Auto-negotiation complete
0 = Auto-negotiation not complete
RO
RO/LH
RO
0
0
1
0
0
1
Remote Fault
1 = Remote fault condition detected
0 = No remote fault condition detected
Auto-Negotiation
Ability
1 = PHY is able to perform Auto-Negotiation
0 = PHY is not able to perform Auto-Negotiation
Link Status
1 = Link is up
0 = Link is down
RO/LL
RO/LH
RO
Jabber Detect
1 = Jabber condition detected
0 = Jabber condition not detected
Extended Capability 1 = Extended register capabilities
0 = Basic register capabilities
1. RO = Read Only
LL = Latching Low
LH = Latching High
57
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Table 42: PHY Identification Register 1 (Address 2)
Type 1
Bit
Name
Description
Default
2.15:0
PHY ID
Number
The PHY identifier composed of bits 3 through 18 of the OUI.
RO
0013 hex
1. RO = Read Only
Table 43: PHY Identification Register 2 (Address 3)
Bit
Name
Description
Type 1
Default
3.15:10
PHY ID
number
The PHY identifier composed of bits 19 through 24
of the OUI.
RO
011110
001110
0001
3.9:4
3.3:0
Manufacturer’s 6 bits containing manufacturer’s part number.
model number
RO
RO
Manufacturer’s 4 bits containing manufacturer’s revision number.
revision
number
1. RO = Read Only
Figure 39:PHY Identifier Bit Mapping
a
b c
Organizationally Unique Identifier
r
s
x
PHY ID Register #2 (Address 3)
PHY ID Register #1 (address 2) = 0013
15
0 15
10 9
4
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
1
0
0
0
1
1
1
0 0
00
20
7B
5
0
3
0
The Level One OUI is 00207B hex
Manufacturer’s
Model Number
Revision
Number
58
ꢀ
LXT971 Register Definitions
Table 44: Auto Negotiation Advertisement Register (Address 4)
Type 1
Bit
4.15
Name
Description
Default
Next Page
1 = Port has ability to send multiple pages.
0 = Port has no ability to send multiple pages.
R/W
0
4.14
4.13
Reserved
Ignore.
RO
0
0
Remote Fault 1 = Remote fault.
0 = No remote fault.
R/W
4.12
4.11
Reserved
Ignore.
R/W
R/W
0
0
Asymmetric
Pause
Pause operation defined in Clause 40 and 27.
4.10
4.9
Pause
1 = Pause operation enabled for full-duplex links.
0 = Pause operation disabled.
R/W
R/W
Note 2
0
100BASE-T4 1 = 100BASE-T4 capability is available.
0 = 100BASE-T4 capability is not available.
(The LXT971 does not support 100BASE-T4 but allows this bit to be
set to advertise in the Auto-Negotiation sequence for 100BASE-T4
operation. An external 100BASE-T4 transceiver could be switched in
if this capability is desired.)
4.8
4.7
100BASE-TX 1 = Port is 100BASE-TX full-duplex capable.
full-duplex 0 = Port is not 100BASE-TX full-duplex capable.
R/W
R/W
Note 3
Note 3
100BASE-TX 1 = Port is 100BASE-TX capable.
0 = Port is not 100BASE-TX capable.
4.6
10BASE-T
full-duplex
1 = Port is 10BASE-T full-duplex capable.
0 = Port is not 10BASE-T full-duplex capable.
1 = Port is 10BASE-T capable.
R/W
R/W
R/W
Note 3
Note 3
00001
4.5
10BASE-T
0 = Port is not 10BASE-T capable.
4.4:0
Selector Field, <00001> = IEEE 802.3.
S<4:0> <00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future Auto-Negotiation development.
<11111> = Reserved for future Auto-Negotiation development.
Unspecified or reserved combinations should not be transmitted.
1. R/W = Read/Write
RO = Read Only
2. The default setting of bit 4.10 (PAUSE) is determined by pin 33/H8 at reset.
3. Default values of bits 4.5, 4.6, 4.7, and 4.8 are determined by LED/CFGn pins at reset. Refer to Table 8 for details.
59
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Table 45: Auto Negotiation Link Partner Base Page Ability Register (Address 5)
Type 1
Bit
5.15
Name
Description
Default
Next Page
1 = Link Partner has ability to send multiple pages.
0 = Link Partner has no ability to send multiple pages.
RO
N/A
5.14
5.13
Acknowledge 1 = Link Partner has received Link Code Word from LXT971.
0 = Link Partner has not received Link Code Word from the
LXT971.
RO
RO
N/A
N/A
Remote Fault 1 = Remote fault.
0 = No remote fault.
5.12
5.11
Reserved
Ignore.
RO
RO
N/A
N/A
Asymmetric
Pause
Pause operation defined in Clause 40 and 27.
1 = Link Partner is Pause capable.
0 = Link Partner is not Pause capable.
5.10
5.9
Pause
1 = Link Partner is Pause capable.
0 = Link Partner is not Pause capable.
RO
RO
RO
RO
RO
RO
RO
N/A
N/A
N/A
N/A
N/A
N/A
N/A
100BASE-T4 1 = Link Partner is 100BASE-T4 capable.
0 = Link Partner is not 100BASE-T4 capable.
5.8
100BASE-TX 1 = Link Partner is 100BASE-TX full-duplex capable.
full-duplex
0 = Link Partner is not 100BASE-TX full-duplex capable.
5.7
100BASE-TX 1 = Link Partner is 100BASE-TX capable.
0 = Link Partner is not 100BASE-TX capable.
5.6
10BASE-T
full-duplex
1 = Link Partner is 10BASE-T full-duplex capable.
0 = Link Partner is not 10BASE-T full-duplex capable.
5.5
10BASE-T
1 = Link Partner is 10BASE-T capable.
0 = Link Partner is not 10BASE-T capable.
5.4:0
Selector Field <00001> = IEEE 802.3.
S<4:0>
<00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future Auto-Negotiation development.
<11111> = Reserved for future Auto-Negotiation development.
Unspecified or reserved combinations shall not be transmitted.
1. RO = Read Only
60
ꢀ
LXT971 Register Definitions
Table 46: Auto Negotiation Expansion (Address 6)
Bit Name Description
Type 1
Default
6.15:6 Reserved
Ignore on read.
RO
0
0
6.5
Base Page
This bit indicates the status of the Auto-Negotiation variable, base
page. It flags synchronization with the Auto-Negotiation state dia-
gram allowing detection of interrupted links. This bit is only used if
bit 16.1 (Alternate NP feature) is set.
RO/
LH
1 = basepage = true
0 = basepage = false
6.4
6.3
Parallel
Detection
Fault
1 = Parallel detection fault has occurred.
0 = Parallel detection fault has not occurred.
RO/
LH
0
0
Link Partner
Next Page
Able
1 = Link partner is next page able.
0 = Link partner is not next page able.
RO
6.2
6.1
Next Page
Able
1 = Local device is next page able.
0 = Local device is not next page able.
RO
1
0
Page Received 1 = Indicates that a new page has been received and the received code
word has been loaded into register 5 (base pages) or register 8 (next
pages) as specified in clause 28 of 802.3. This bit will be cleared on
read. If bit 16.1 is set, the Page Received bit will also be cleared
when mr_page_rx = false or transmit_disable = true.
RO
LH
6.0
Link Partner
A/N Able
1 = Link partner is auto-negotiation able.
0 = Link partner is not auto-negotiation able.
RO
0
1. RO = Read Only LH = Latching High
61
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Table 47: Auto Negotiation Next Page Transmit Register (Address 7)
Type 1
Bit
7.15
Name
Description
Default
Next Page
1 = Additional next pages follow
R/W
0
(NP)
0 = Last page
7.14
7.13
Reserved
Message Page
(MP)
Write as 0, ignore on read
1 = Message page
RO
0
1
R/W
0 = Unformatted page
1 = Will comply with message
0 = Can not comply with message
7.12
7.11
Acknowledge 2
(ACK2)
Toggle
R/W
R/W
0
0
1 = Previous value of the transmitted Link Code Word equalled
logic zero
(T)
0 = Previous value of the transmitted Link Code Word equalled
logic one
7.10:0 Message/Unfor-
matted Code Field
R/W
0000000
0001
1. RO = Read Only. R/W = Read/Write
Table 48: Auto Negotiation Link Partner Next Page Receive Register (Address 8)
Type 1
Bit
8.15
Name
Description
Default
Next Page
1 = Link Partner has additional next pages to send
0 = Link Partner has no additional next pages to send
1 = Link Partner has received Link Code Word from LXT971
0 = Link Partner has not received Link Code Word from LXT971
1 = Page sent by the Link Partner is a Message Page
0 = Page sent by the Link Partner is an Unformatted Page
1 = Link Partner complies with the message
RO
0
(NP)
8.14
8.13
8.12
8.11
Acknowledge
(ACK)
RO
RO
RO
RO
0
0
0
0
Message Page
(MP)
Acknowledge 2
(ACK2)
Toggle
0 = Link Partner cannot comply with the message
1 = Previous value of the transmitted Link Code Word equalled
logic zero
(T)
0 = Previous value of the transmitted Link Code Word equalled
logic one
8.10:0 Message/Unfor-
matted Code Field
User definable
RO
0
1. RO = Read Only.
62
ꢀ
LXT971 Register Definitions
Table 49: Configuration Register (Address 16, Hex 10)
Bit Name Description
Type 1
Default
16.15 Reserved
Write as zero, ignore on read.
R/W
R/W
0
0
16.14 Force Link Pass
1 = Force Link pass
0 = Normal operation
16.13 Transmit Disable 1 = Disable Twisted Pair transmitter
0 = Normal Operation
R/W
R/W
0
0
16.12 Bypass Scrambler 1 = Bypass Scrambler and Descrambler
(100BASE-TX)
16.11 Reserved
16.10 Jabber
(10BASE-T)
SQE
0 = Normal Operation
Ignore
R/W
R/W
0
0
1 = Disable Jabber Correction
0 = Normal operation
16.9
16.8
16.7
16.6
16.5
1 = Enable Heart Beat
0 = Disable Heart Beat
R/W
R/W
R/W
R/W
R/W
0
(10BASE-T)
TP Loopback
(10BASE-T)
1 = Disable TP loopback during half-duplex operation
0 = Normal Operation
0
CRS Select
(10BASE-T)
1 = CRS deassert extends to RX_DV deassert
0 = Normal Operation
1
Note 2
0
Sleep Mode
PRE_EN
1 = Enable Sleep Mode
0 = Disable Sleep Mode
Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when CRS is asserted.
16.4:3 Sleep Timer
00 = 3.04 seconds
01 = 2.00 seconds
10 = 1.04 seconds
R/W
00
16.2
16.1
16.0
Fault Code
Enable
1 = Enable FEFI transmission
0 = Disable FEFI transmission
R/W
R/W
R/W
1
0
Alternate NP
feature
1 = Enable alternate auto negotiate next page feature.
0 = Disable alternate auto negotiate next page feature
Fiber Select
1 = Select fiber mode.
0 = Select TP mode.
Note 3
1. R/W = Read /Write
LHR = Latches High on Reset
2. The default value of bit 16.6 is determined by the state of the SLEEP pin 32/H7.
3. The default value of bit 16.0 is determined by pin 26/G2 (SD/TP).
63
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Table 50: Status Register #2 (Address 17)
Type 1
Bit
Name
Description
Default
17.15
17.14
Reserved
Always 0.
RO
RO
0
0
10/100 Mode
Transmit Status
Receive Status
Collision Status
Link
1 = LXT971 is operating in 100BASE-TX mode.
0 = LXT971 is not operating 100BASE-TX mode.
17.13
17.12
17.11
17.10
17.9
1 = LXT971 is transmitting a packet.
0 = LXT971 is not transmitting a packet.
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
1 = LXT971 is receiving a packet.
0 = LXT971 is not receiving a packet.
1 = Collision is occurring.
0 = No collision.
1 = Link is up.
0 = Link is down.
Duplex Mode
Auto-Negotiation
1 = Full-duplex.
0 = Half-duplex.
17.8
1 = LXT971 is in Auto-Negotiation Mode.
0 = LXT971 is in manual mode.
17.7
Auto-Negotiation
Complete
1 = Auto-negotiation process completed.
0 = Auto-negotiation process not completed.
This bit is only valid when auto negotiate is enabled, and is
equivalent to bit 1.5.
17.6
17.5
Reserved
Polarity
Always 0.
RO
RO
0
0
1 = Polarity is reversed.
0 = Polarity is not reversed.
17.4
17:3
Pause
Error
1 = Device Pause capable.
0 = Device Not Pause capable.
RO
RO
0
0
1 = Error Occurred (Remote Fault, X,Y, Z).
0 = No error occurred.
17:2
17:1
17.0
Reserved
Reserved
Reserved
Always 0.
Always 0.
Always 0.
RO
RO
RO
0
0
0
1. RO = Read Only. R/W = Read/Write
64
ꢀ
LXT971 Register Definitions
Table 51: Interrupt Enable Register (Address 18)
Bit Name Description
Type 1
Default
18.15:9 Reserved
Write as 0; ignore on read.
Write as 0; ignore on read.
R/W
R/W
R/W
N/A
0
18.8
18.7
Reserved
ANMSK
Mask for Auto Negotiate Complete
0
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
18.6
18.5
18.4
SPEEDMSK
DUPLEXMSK
LINKMSK
Mask for Speed Interrupt
R/W
R/W
R/W
0
0
0
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
Mask for Duplex Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
Mask for Link Status Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
18.3
18.2
18.1
Reserved
Reserved
INTEN
Write as 0, ignore on read.
Write as 0, ignore on read.
R/W
R/W
R/W
0
0
0
1 = Enable interrupts.
0 = Disable interrupts.
18.0
TINT
1 = Force interrupt on MDINT.
0 = Normal operation.
R/W
0
1. R/W = Read /Write
65
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Table 52: Interrupt Status Register (Address 19, Hex 13)
Type 1
Bit
Name
Description
Default
19.15:9 Reserved
Ignore
Ignore
RO
RO
N/A
0
19.8
19.7
Reserved
ANDONE
Auto Negotiation Status
RO/SC
RO/SC
N/A
0
1= Auto Negotiation has completed.
0= Auto Negotiation has not completed.
19.6
19.5
19.4
SPEEDCHG
Speed Change Status
1 = A Speed Change has occurred since last reading this register.
0 = A Speed Change has not occurred since last reading this register.
DUPLEXCHG Duplex Change Status
1 = A Duplex Change has occurred since last reading this register.
RO/SC
RO/SC
0
0
0
0 = A Duplex Change has not occurred since last reading this register.
LINKCHG
Link Status Change Status
1 = A Link Change has occurred since last reading this register.
0 = A Link Change has not occurred since last reading this register.
19.3
19.2
Reserved
MDINT
Ignore.
RO
RO
1 = MII interrupt pending.
0 = No MII interrupt pending.
Ignore.
19.1
19.0
Reserved
Reserved
RO
RO
N/A
0
Ignore
1. R/W = Read/Write, RO = Read Only, SC = Self Clearing.
66
ꢀ
LXT971 Register Definitions
Table 53: LED Configuration Register (Address 20, Hex 14)
Type 1
Bit
Name
Default
Description
20.15:12 LED1
Programming
0000 = Display Speed Status (Continuous, Default)
0001 = Display Transmit Status (Stretched)
0010 = Display Receive Status (Stretched)
0011 = Display Collision Status (Stretched)
0100 = Display Link Status (Continuous)
R/W
0000
bits
0101 = Display Duplex Status (Continuous)
0110 = Unused
0111 = Display Receive or Transmit Activity (Stretched)
1000 = Test mode- turn LED on (Continuous)
1001 = Test mode- turn LED off (Continuous)
1010 = Test mode- blink LED fast (Continuous)
1011 = Test mode- blink LED slow (Continuous)
1100 = Display Link and Receive Status combined 2 (Stretched)3
1101 = Display Link and Activity Status combined 2 (Stretched)3
1110 = Display Duplex and Collision Status combined 4 (Stretched)3
1111 = Unused
20.11:8 LED2
0000 = Display Speed Status
R/W
0100
0001 = Display Transmit Status
0010 = Display Receive Status
0011 = Display Collision Status
Programming
bits
0100 = Display Link Status (Default)
0101 = Display Duplex Status
0110 = Unused
0111 = Display Receive or Transmit Activity
1000 = Test mode- turn LED on
1001 = Test mode- turn LED off
1010 = Test mode- blink LED fast
1011 = Test mode- blink LED slow
1100 = Display Link and Receive Status combined 2 (Stretched)3
1101 = Display Link and Activity Status combined 2 (Stretched)3
1110 = Display Duplex and Collision Status combined 4 (Stretched)3
1111 = Unused
1. R/W = Read /Write
RO = Read Only
LH = Latching High
2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive or Activity) causes the LED to change state (blink).
3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched regardless of the value of 20.1.
4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
5. Values are relative approximations. Not guaranteed or production tested.
67
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
Table 53: LED Configuration Register (Address 20, Hex 14) – continued
Bit
Name
Default
Description
0000 = Display Speed Status
Type 1
20.7:4
LED3
R/W
0010
0001 = Display Transmit Status
0010 = Display Receive Status (Default)
0011 = Display Collision Status
Programming
bits
0100 = Display Link Status
0101 = Display Duplex Status
0110 = Unused
0111 = Display Receive or Transmit Activity
1000 = Test mode- turn LED on
1001 = Test mode- turn LED off
1010 = Test mode- blink LED fast
1011 = Test mode- blink LED slow
1100 = Display Link and Receive Status combined 2 (Stretched)3
1101 = Display Link and Activity Status combined 2 (Stretched)3
1110 = Display Duplex and Collision Status combined 4 (Stretched)3
1111 = Unused
LEDFREQ5
20.3:2
00 = Stretch LED events to 30 ms.
01 = Stretch LED events to 60 ms.
10 = Stretch LED events to 100 ms.
11 = Reserved.
R/W
00
20.1
20.0
PULSE-
STRETCH
0 = Disable pulse stretching of all LEDs.
1 = Enable pulse stretching of all LEDs.
R/W
R/W
1
Reserved
Ignore.
N/A
1. R/W = Read /Write
RO = Read Only
LH = Latching High
2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive or Activity) causes the LED to change state (blink).
3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched regardless of the value of 20.1.
4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
5. Values are relative approximations. Not guaranteed or production tested.
68
ꢀ
LXT971 Register Definitions
Table 54: Transmit Control Register (Address 30)
Type2
Bit
Name
Default
Description
30.15:11
30.12
Reserved
Ignore
R/W
R/W
0
0
Transmit Low Power 1 = Forces the transmitter into low power mode. Also
forces a zero-differential transmission.
0 = Normal transmission.
30.11:10
Port Rise Time
Control1
00 = 2.7 ns (default is pins TXSLEW<1:0>)
R/W
R/W
00
0
01 = 3.5 ns
10 = 2.3 ns
11 = 2.0 ns
30.9:0
Reserved
Ignore
1. Values are relative approximations. Not guaranteed or production tested.
2. R/W = Read/Write
69
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
PACKAGE SPECIFICATIONS
Figure 40:Preliminary PBGA Package Specification
64-Pin Plastic Ball Grid Array Package
• Part Number - LXT971BC Commercial Temperature Range (0ºC to +70ºC)
• Part Number - LXT971BE Extended Temperature Range (-40ºC to +85ºC)
(4X)
0.20
7.00
2.00 REF.
± 0.20
B
6.30
0.70 REF.
0.80
OPTION:
PIN A1 IDENTIFIER
1.00 0.10
INK OR LASER MARKING
±
A
B
C
D
E
F
G
H
TOP VIEW
1.26
± 0.10
0.70
± 0.025
4
3
2
1
8
7
6
5
0.26
±
0.04
0.28
0.30
0.15
C
C
B
A
±
0.10
0.40
± 0.15
2
BOTTOM VIEW
C
SEATING PLANE
3
SIDE VIEW
NOTES:
1. All dimensions and tolerances conform to ASME
2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
3. Primary datum and seating plane are defined by the spherical crowns of the solder balls.
Y
14.5 M - 1994.
C
4. Maximum mold to substrate offset shall be 0.127.
5. The surface finish of the package shall be EDM Charmille #18
PRELIMINARY
- #21.
6. Unless otherwise specified tolerance: Decimal
± 0.05 Angular ±2°.
70
ꢀ
LXT971 Package Specifications
Figure 41:LXT971 LQFP Package Specifications
64-Pin Low Profile Quad Flat Pack
• Part Number - LXT971LC Commercial Temperature Range (0ºC to +70ºC)
• Part Number - LXT971LE Extended Temperature Range (-40ºC to +85ºC)
D
D1
Millimeters
Dim
Min
Max
A
A1
A2
B
–
1.60
0.15
1.45
0.27
12.15
10.1
12.15
10.1
0.05
1.35
0.17
11.85
9.9
E1
E
D
D1
E
11.85
9.9
E1
e
0.50 BSC1
L
0.45
0.75
e
e
/
2
L1
θ3
θ
1.00 REF
11o
0o
13o
7o
1. Basic Spacing between Centers
θ3
L1
A2
A
θ
A1
B
θ3
L
71
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
REVISION HISTORY
Table 55: Changes from Rev 1.0 to Rev 1.1 (02/00)
Section
Front page
Page
Type
Description
Change TXD<4:0> to TXD<3:0>.
1
Modify
LXT971 Block Dia-
gram
Change RXD<3:0> to RXD<3:0>.
Figure 1 (PBGA)
Figure 2 (LQFP)
Pin Assignments
Table 2
4
5
Modify
Remove “Preliminary” from heading.
7
Modify
Add
Replace with new text for MDDIS Signal Description.
LXT971 MII Signal
Description
Table 6
10
Add footnote 2: “If JTAG port is not used, these pins do not
need to be terminated.”
LXT971 JTAG Test
Signal Descriptions
Place footnote 2 after TDI, TDO, TMS, TCK, TRST.
Modify first and third paragraphs for greater clarity.
Twisted-Pair Interface
12
13
Modify
Add
MDIO Management
Interface
Add third paragraph regarding MDIO and MDDIS operation in
Hardware Control Mode.
Figure 6
15
Modify
Modify figure to reflect change in MDIO operation in the Hard-
ware Control Mode when MDDIS is set High.
Initialization Sequence
Figure 21, Typical TP
Interface - Switch
35
36
39
Modify
Modify
Modify
Added bypass cap to output transformer center tap.
Added bypass cap to output transformer center tap.
Figure 22, Typical TP
Interface - NIC
Table 17
Change Max values for 100BASE-TX, 100BASE-FX, and
Auto-Negotiation.
Operating Conditions
Table 26
43
44
45
45
Modify
Modify
Modify
Modify
Change Min, Typ, and Max values for t3 through t7.
Change Min, Typ, and Max values under t3 through t5.
Change Min, Typ, and Max values for t3 through t7.
Change Min, Typ, and Max values for t3 through t5.
100BASE-TX Receive
Timing Parameters
Table 27
100BASE-TX Transmit
Timing Parameters
Table 28
100BASE-FX Receive
Timing Parameters
Table 29
100BASE-FX Transmit
Timing Parameters
72
ꢀ
LXT971 Revision History
Table 55: Changes from Rev 1.0 to Rev 1.1 (02/00) – continued
Section
Table 30
Page
Type
Description
47
Modify
Change Min, Typ, and Max values for t3.
100BASE-T Receive
Timing Parameters
Change Min, Typ, and Max values for t4 through t9.
Table 31
48
50
Modify
Modify
Change Typ value for t5.
100BASE-T Transmit
Timing Parameters
Table 34
Change Typ and Max values for Clock pulse to Data pulse.
Auto-Negotiation and
Fast Link Pulse Timing
Parameters
Change Min, Typ, and Max values for Clock pulse to Clock
pulse.
Add footnote 2 to Power Up delay.
Table 36
52
52
Modify
Modify
Power-Up Timing
Parameters
Footnote 2: Change Xns to “300 µs”.
Add footnote 2 to RESET recovery delay.
Table 37
RESET Pulse Width
and Recovery Timing
Parameters
Footnote 2: Change Xns to “300 µs”.
Table 50
64
Add
Add Type and Default values to 17.4 (Pause).
Status Register #2
73
ꢀ
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
NOTES
74
ꢀ
LXT971 Note
NOTE
75
ꢀ
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Revision
Date
Status
Technical Update.
1.1
02/00
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Copyright © 2000 Level One Communications, Inc., an Intel Company. Specifications subject to change without notice. All rights reserved.
IS971PS-R1.1-0200
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