IRS2332JTRPBF [INFINEON]
3-PHASE-BRIDGE DRIVER; 3相桥式驱动器
| 型号： | IRS2332JTRPBF |
| 厂家： | 
Infineon |
| 描述： | 3-PHASE-BRIDGE DRIVER |
| 文件： | 总39页 (文件大小：1093K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRS233(0,2)(D)(S&J)PbF
June 1 2011
IRS233(0,2)(D)(S & J)PbF
3ꢀPHASEꢀBRIDGE DRIVER
Product Summary
Features
•
Floating channel designed for bootstrap operation
Fully operational to +600 V
VOFFSET
600V max.
•
•
•
•
•
•
•
•
•
•
•
•
Tolerant to negative transient voltage – dV/dt immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for all channels
Overꢀcurrent shutdown turns off all six drivers
Independent halfꢀbridge drivers
Matched propagation delay for all channels
3.3 V logic compatible
Outputs out of phase with inputs
Crossꢀconduction prevention logic
Integrated Operational Amplifier
Integrated Bootstrap Diode function (IRS233(0,2)D)
RoHS Compliant
IO+/ꢀ
200 mA / 420 mA
10 V – 20 V (233(0,2)(D))
500 ns
VOUT
ton/off (typ.)
Deadtime (typ.)
2.0 us (IRS2330(D))
0.7 us (IRS2332(D))
Applications:
*Motor Control
*Air Conditioners/ Washing Machines
*General Purpose Inverters
*Micro/Mini Inverter Drives
Description
Packages
The IRS233(0,2)(D)(S & J) is a high voltage, high speed
power MOSFET and IGBT driver with three independent high
and low side referenced output channels. Proprietary HVIC
technology enables ruggedized monolithic construction.
Logic inputs are compatible with CMOS or LSTTL outputs,
down to 3.3 V logic. A groundꢀreferenced operational
amplifier provides analog feedback of bridge current via an
external current sense resistor. A current trip function which
terminates all six outputs is also derived from this resistor.
An open drain FAULT signal indicates if an overꢀcurrent or
undervoltage shutdown has occurred. The output drivers
feature a high pulse current buffer stage designed for
minimum driver crossꢀconduction. Propagation delays are
matched to simplify use at high frequencies. The floating
channel can be used to drive Nꢀchannel power MOSFET
or IGBT in the high side configuration which operates up
to 600 volts.
28ꢀLead SOIC
44-Lead PLCC w/o 12 Leads
Typical Connection
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IRS233(0,2)(D)(S&J)PbF
Qualification Information†
Industrial††
Qualification Level
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification level is
granted by extension of the higher Industrial level.
MSL3†††, 260°C
SOIC28W
(per IPC/JEDEC JꢀSTDꢀ020)
Moisture Sensitivity Level
MSL3†††, 245°C
PLCC44
(per IPC/JEDEC JꢀSTDꢀ020)
Class 2
Human Body Model
(per JEDEC standard JESD22ꢀA114)
ESD
Class B
Machine Model
(per EIA/JEDEC standard EIA/JESD22ꢀA115)
Class I, Level A
(per JESD78)
Yes
IC LatchꢀUp Test
RoHS Compliant
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
†† Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
†††
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
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IRS233(0,2)(D)(S&J)PbF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to VSO. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
VB1,2,3
Highꢀside floating supply voltage
ꢀ0.3
620
VS1,2,3
VHO1,2,3
VCC
Highꢀside floating offset voltage
Highꢀside floating output Voltage
Lowꢀside and logic fixed supply voltage
Logic ground
VB1,2,3 ꢀ 20
VS1,2,3 ꢀ 0.3
ꢀ0.3
VB1,2,3 + 0.3
VB1,2,3 + 0.3
20
VSS
VCC ꢀ 20
ꢀ0.3
VCC + 0.3
VCC + 0.3
VLO1,2,3
Lowꢀside output voltage
V
(VSS + 15) or
(VCC + 0.3)
Whichever is
lower
_______ ______
Logic input voltage ( HIN1,2,3, LIN1,2,3 & ITRIP)
VSS ꢀ0.3
VIN
VFLT
VCAO
VCAꢀ
FAULT output voltage
VSS ꢀ0.3
VSS ꢀ0.3
VSS ꢀ0.3
—
VCC +0.3
VCC +0.3
VCC +0.3
50
Operational amplifier output voltage
Operational amplifier inverting input voltage
Allowable offset supply voltage transient
dVS/dt
V/ns
W
(28 lead SOIC)
—
—
1.6
2.0
78
PD
Package power dissipation @ TA ≤ +25 °C
Thermal resistance, junction to ambient
(44 lead PLCC)
(28 lead SOIC)
(44 lead PLCC)
—
RthJA
°C/W
°C
—
63
TJ
TS
TL
Junction temperature
—
150
150
Storage temperature
ꢀ55
Lead temperature (soldering, 10 seconds)
—
300
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IRS233(0,2)(D)(S&J)PbF
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute voltage referenced to VSO. The VS offset rating is
tested with all supplies biased at 15 V differential.
Symbol
Definition
Min.
Max.
Units
VB1,2,3
Highꢀside floating supply voltage
VS1,2,3 +10
VS1,2,3 +20
Static highꢀside floating offset voltage
Transient highꢀside floating offset voltage
Highꢀside floating output voltage
Lowꢀside and Logic fixed supply voltage
Logic ground
VS1,2,3
VSt1,2,3
VHO1,2,3
VSOꢀ8 (Note1)
ꢀ50 (Note2)
VS1,2,3
600
600
VB1,2,3
VCC
VSS
10
ꢀ5
20
5
V
VLO1,2,3
VIN
Lowꢀside output voltage
0
VCC
VSS + 5
VCC
Logic input voltage (HIN1,2,3, LIN1,2,3 & ITRIP)
FAULT output voltage
VSS
VSS
VSS
VSS
ꢀ40
VFLT
VCAO
VCAꢀ
TA
Operational amplifier output voltage
Operational amplifier inverting input voltage
Ambient temperature
VSS + 5
VSS + 5
125
°C
Note 1: Logic operational for VS of (VSO ꢀ8 V) to (VSO +600 V). Logic state held for VS of (VSO ꢀ8 V) to (VSO – VBS .
)
Note 2: Operational for transient negative VS of VSS ꢀ 50 V with a 50 ns pulse width. Guaranteed by design. Refer to
the Application Information section of this datasheet for more details.
Note 3: CAO input pin is internally clamped with a 5.2 V zener diode.
Dynamic Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified.
Symbol
Definition
Min Typ Max Units Test Conditions
ton
Turnꢀon propagation delay
400 500 700
V
S1,2,3 = 0 V to 600 V
VS1,2,3 = 0 V
toff
t r
Turnꢀoff propagation delay
Turnꢀon rise time
400 500 700
—
—
80
35
125
55
t f
Turnꢀoff fall time
titrip
tbl
ITRIP to output shutdown propagation delay
ITRIP blanking time
400 660
400
920
—
—
tflt
ITRIP to FAULT indication delay
Input filter time (all six inputs)
LIN1,2,3 to FAULT clear time (2330/2)
350 550 870
325
tflt, in
tfltclr
—
—
ns
5300 8500 13700
1300 2000 3100
500 700 1100
Deadtime:
(IRS2330(D))
DT
VIN = 0 V & 5 V
without
external deadtime
(IRS2332(D))
—
—
—
—
400
140
Deadtime matching: :
(IRS2330(D))
(IRS2332(D))
MDT
VIN = 0 V & 5 V
without
external deadtime
larger than DT
Delay matching time (t ON , t OFF
Pulse width distortion
)
MT
PM
—
—
—
—
50
75
PM input 10 ꢁs
NOTE: For high side PWM, HIN pulse width must be > 1.5 usec
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IRS233(0,2)(D)(S&J)PbF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified.
Symbol
Definition
Min Typ Max Units Test Conditions
SR+
SRꢀ
Operational amplifier slew rate (+)
Operational amplifier slew rate (ꢀ)
5
10
—
—
1 V input step
V/ꢁs
2.4
3.2
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IRS233(0,2)(D)(S&J)PbF
Static Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH and IIN parameters
are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters
are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Symbol
Definition
Min Typ Max Units Test Conditions
VIH
VIL
Logic “0” input voltage (OUT = LO)
Logic “1” input voltage (OUT = HI)
ITRIP input positive going threshold
—
—
—
2.2
—
V
0.8
VIT,TH+
400 490 580
VIN = 0 V, IO = 20 mA
VIN = 5 V, IO = 20 mA
VB = VS = 600 V
VIN = 0 V or 4 V
VIN = 4 V
mV
VOH
VOL
ILK
High level output voltage, VBIAS ꢀ VO
Low level output voltage, VO
Offset supply leakage current
Quiescent VBS supply current
Quiescent VCC supply current
—
—
—
—
—
—
—
1000
400
50
—
ꢁA
IQBS
IQCC
IIN+
IINꢀ
IITRIP+
IITRIPꢀ
30
4.0
50
6.2
mA
Logic “1” input bias current (OUT =HI)
Logic “0” input bias current (OUT = LO)
“High” ITRIP bias current
ꢀ400 ꢀ300 ꢀ100
ꢀ300 ꢀ220 ꢀ100
—
—
VIN = 0 V
VIN = 4 V
ITRIP = 4 V
ITRIP = 0 V
ꢁA
nA
5
—
10
30
“LOW” ITRIP bias current
VBS supply undervoltage
positive going threshold
VBSUV+
VBSUVꢀ
VCCUV+
VCCUVꢀ
7.5 8.35 9.2
7.1 7.95 8.8
VBS supply undervoltage
negative going threshold
V
CC supply undervoltage
8.3
8
9
9.7
9.4
V
positive going threshold
VCC supply undervoltage
negative going threshold
8.7
VCCUVH
VBSUVH
Ron, FLT
Hysteresis
—
—
—
0.3
0.4
55
—
—
75
Hysteresis
FAULT low onꢀresistance
ꢂ
VO = 0 V, VIN = 0 V
PW ≤ 10 us
VO = 15 V, VIN = 5 V
PW ≤ 10 us
IO+
IOꢀ
Output high short circuit pulsed current
Output low short circuit pulsed current
—
ꢀ250 ꢀ180
mA
420 500
—
RBS
VOS
ICAꢀ
Integrated bootstrap diode resistance
Operational amplifier input offset voltage
CAꢀ input bias current
—
—
—
200
—
—
—
20
100
ꢂ
mV
nA
VSO = 0.2 V
VCAꢀ = 1 V
Operational amplifier common mode
rejection ratio
Operational amplifier power supply
rejection ratio
Operational amplifier high level output
voltage
Operational amplifier low level output
voltage
CMRR
PSRR
—
—
80
75
5.2
—
—
—
VSO = 0.1 V & 5 V
dB
VSO = 0.2 V
VCC = 9.7 V & 20 V
VOH,AMP
VOL,AMP
4.8
—
5.6
40
V
VCAꢀ = 0 V, VSO =1 V
VCAꢀ = 1 V, VSO =0 V
mV
Note: The integrated bootstrap diode does not work well with the trapezoidal control.
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IRS233(0,2)(D)(S&J)PbF
Static Electrical Characteristicsꢀ Continued
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH and IIN parameters
are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters
are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Symbol
Definition
Min Typ Max Units Test Conditions
VCAꢀ = 0 V, VSO =1 V
ISRC,AMP
Operational amplifier output source current
—
1
ꢀ7
2.1
ꢀ10
4
ꢀ4
—
—
—
VCAO = 4 V
VCAꢀ = 1 V, VSO =0 V
VCAO = 2 V
VCAꢀ = 0 V, VSO =5 V
VCAO = 0 V
ISNK,AMP
IO+,AMP
IOꢀ,AMP
Operational amplifier output sink current
mA
Operational amplifier output high short circuit
current
Operational amplifier output low short circuit
current
ꢀ30
—
VCAꢀ = 5 V, VSO =0 V
VCAO = 5 V
Functional Block Diagram
Note: IRS2330 & IRS2332 are without integrated bootstrap diode.
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IRS233(0,2)(D)(S&J)PbF
Lead Definitions
Symbol
Description
HIN1,2,3
LIN1,2,3
FAULT
Logic input for highꢀside gate driver outputs (HO1,2,3), out of phase
Logic input for lowꢀside gate driver output (LO1,2,3), out of phase
Indicates overꢀcurrent or undervoltage lockout (lowꢀside) has occurred, negative logic
Lowꢀside and logic fixed supply
VCC
ITRIP
CAO
Input for overꢀcurrent shutdown
Output of current amplifier
CAꢀ
Negative input of current amplifier
Logic Ground
VSS
VB1,2,3
HO1,2,3
VS1,2,3
LO1,2,3
VSO
Highꢀside floating supply
Highꢀside gate drive output
Highꢀside floating supply return
Lowꢀside gate drive output
Lowꢀside return and positive input of current amplifier
Lead Assignments
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IRS233(0,2)(D)(S&J)PbF
Application Information and Additional Details
Information regarding the following topics are included as subsections within this section of the datasheet.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IGBT/MOSFET Gate Drive
Switching and Timing Relationships
Deadtime
Matched Propagation Delays
Input Logic Compatibility
Undervoltage Lockout Protection
ShootꢀThrough Protection
Fault Reporting
OverꢀCurrent Protection
OverꢀTemperature Shutdown Protection
Truth Table: Undervoltage lockout, ITRIP
Advanced Input Filter
ShortꢀPulse / Noise Rejection
Integrated Bootstrap Functionality
Bootstrap Power Supply Design
Separate Logic and Power Grounds
Negative VS Transient SOA
DCꢀ bus Current Sensing
PCB Layout Tips
Integrated Bootstrap FET limitation
Additional Documentation
IGBT/MOSFET Gate Drive
The IRS233(2,0)(D) HVICs are designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate several
parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of
the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the highꢀ
side power switch and VLO for the lowꢀside power switch; this parameter is sometimes generically called VOUT and in this case
does not differentiate between the highꢀside or lowꢀside output voltage.
VB
VB
(or VCC
)
(or VCC)
IO+
HO
HO
(or LO)
(or LO)
+
IOꢀ
VHO (or VLO)
ꢀ
VS
VS
(or COM)
(or COM)
Figure 1: HVIC sourcing current
Figure 2: HVIC sinking current
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IRS233(0,2)(D)(S&J)PbF
Switching and Timing Relationships
The relationship between the input and output signals of the IRS233(0,2)(D) are illustrated below in Figures 3. From these
figures, we can see the definitions of several timing parameters (i.e., PWIN, PWOUT, tON, tOFF, tR, and tF) associated with this
device.
LINx
(or HINx)
50%
50%
PWIN
tOFF tF
tON tR
PWOUT
90%
10%
90%
10%
LOx
(or HOx)
Figure 3: Switching time waveforms
The following two figures illustrate the timing relationships of some of the functionality of the IRS233(0,2)(D); this functionality
is described in further detail later in this document.
During interval A of Figure 4, the HVIC has received the command to turnꢀon both the highꢀ and lowꢀside switches at the same
time; as a result, the shootꢀthrough protection of the HVIC has prevented this condition and both the highꢀ and lowꢀside output
are held in the off state.
Interval B of Figures 4 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of the
gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also held low) and a fault is
reported by the FAULT output transitioning to the low state. Once the ITRIP input has returned to the low state, the fault
condition is latched until the all LINx become high.
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IRS233(0,2)(D)(S&J)PbF
A
B
HIN1,2,3
LIN1,2,3
ITRIP
FAULT
HO1,2,3
LO1,2,3
Figure 4: Input/output timing diagram
Deadtime
This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within
IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a
minimum deadtime) in which both the highꢀ and lowꢀside power switches are held off; this is done to ensure that the power
switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is
automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified
by the gate driver. Figure 5 illustrates the deadtime period and the relationship between the output gate signals.
The deadtime circuitry of the IRS233(0,2)(D) is matched with respect to the highꢀ and lowꢀside outputs of a given channel;
additionally, the deadtimes of each of the three channels are matched.
Figure 5: Illustration of deadtime
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IRS233(0,2)(D)(S&J)PbF
Matched Propagation Delays
The IRS233(0,2)(D) family of HVICs is designed with propagation delay matching circuitry. With this feature, the IC’s
response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the lowꢀ
side channels and the highꢀside channels. Additionally, the propagation delay for each lowꢀside channel is matched when
compared to the other lowꢀside channels and the propagation delays of the highꢀside channels are matched with each other.
The propagation turnꢀon delay (tON) of the IRS233(0,2)(D) is matched to the propagation turnꢀon delay (tOFF).
Input Logic Compatibility
The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS233(0,2)(D) family has been designed to
be compatible with 3.3 V and 5 V logicꢀlevel signals. The IRS233(0,2)(D) features an integrated 5.2 V Zener clamp on the
HIN, LIN, and ITRIP pins. Figure 6 illustrates an input signal to the IRS233(0,2)(D), its input threshold values, and the logic
state of the IC as a result of the input signal.
Figure 6: HIN & LIN input thresholds
Undervoltage Lockout Protection
This family of ICs provides undervoltage lockout protection on both the VCC (logic and lowꢀside circuitry) power supply and the
VBS (highꢀside circuitry) power supply. Figure 7 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the
waveform crosses the UVLO threshold (VCCUV+/ꢀ or VBSUV+/ꢀ) the undervoltage protection is enabled or disabled.
Upon powerꢀup, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turnꢀon. Additionally, if the VCC
voltage decreases below the VCCUVꢀ threshold during operation, the undervoltage lockout circuitry will recognize a fault
condition and shutdown the highꢀ and lowꢀside gate drive outputs, and the FAULT pin will transition to the low state to inform
the controller of the fault condition.
Upon powerꢀup, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turnꢀon. Additionally, if the VBS voltage
decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and
shutdown the highꢀside gate drive outputs of the IC.
The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to
fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low
voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high
conduction losses within the power device and could lead to power device failure.
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IRS233(0,2)(D)(S&J)PbF
Figure 7: UVLO protection
ShootꢀThrough Protection
The IRS233(0,2)(D) family of highꢀvoltage ICs is equipped with shootꢀthrough protection circuitry (also known as crossꢀ
conduction prevention circuitry). Figure 8 shows how this protection circuitry prevents both the highꢀ and lowꢀside switches
from conducting at the same time. Table 1 illustrates the input/output relationship of the devices in the form of a truth table.
Note that the IRS233(0,2)(D) has inverting inputs (the output is outꢀofꢀphase with its respective input).
Figure 8: Illustration of shootꢀthrough protection circuitry
IRS233(0,2)(D)
HIN
0
LIN
0
HO
0
LO
0
0
1
1
0
1
0
0
1
1
1
0
0
Table 1: Input/output truth table
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IRS233(0,2)(D)(S&J)PbF
Fault Reporting
The IRS233(0,2)(D) family provides an integrated fault reporting output. There are two situations that would cause the HVIC
to report a fault via the FAULT pin. The first is an undervoltage condition of VCC and the second is if the ITRIP pin recognizes
a fault. Once the fault condition occurs, the FAULT pin is internally pulled to VSS and the fault condition is latched. The fault
output stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed,
the voltage on the FAULT pin will return to VCC
.
OverꢀCurrent Protection
The IRS233(0,2)(D) HVICs are equipped with an ITRIP input pin. This functionality can be used to detect overꢀcurrent events
in the DCꢀ bus. Once the HVIC detects an overꢀcurrent event through the ITRIP pin, the outputs are shutdown, a fault is
reported through the FAULT pin.
The level of current at which the overꢀcurrent protection is initiated is determined by the resistor network (i.e., R0, R1, and R2)
connected to ITRIP as shown in Figure 9, and the ITRIP threshold (VIT,TH+). The circuit designer will need to determine the
maximum allowable level of current in the DCꢀ bus and select R0, R1, and R2 such that the voltage at node VX reaches the
overꢀcurrent threshold (VIT,TH+) at that current level.
VIT,TH+ = R0IDCꢀ(R1/(R1+R2))
Figure 9: Programming the overꢀcurrent protection
For example, a typical value for resistor R0 could be 50 mꢂ. The voltage of the ITRIP pin should not be allowed to exceed 5
V; if necessary, an external voltage clamp may be used.
OverꢀTemperature Shutdown Protection
The ITRIP input of the IRS233(0,2)(D) can also be used to detect overꢀtemperature events in the system and initiate a
shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will need to
design the resistor network as shown in Figure 10 and select the maximum allowable temperature.
This network consists of a thermistor and two standard resistors R3 and R4. As the temperature changes, the resistance of the
thermistor will change; this will result in a change of voltage at node VX. The resistor values should be selected such the
voltage VX should reach the threshold voltage (VIT,TH+) of the ITRIP functionality by the time that the maximum allowable
temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V.
When using both the overꢀcurrent protection and overꢀtemperature protection with the ITRIP input, ORꢀing diodes (e.g.,
DL4148) can be used. This network is shown in Figure 11; the ORꢀing diodes have been labeled D1 and D2.
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IRS233(0,2)(D)(S&J)PbF
Figure 10: Programming overꢀtemperature protection Figure 11: Using overꢀcurrent protection and overꢀtemperature
protection
Truth Table: Undervoltage lockout and ITRIP
Table 2 provides the truth table for the IRS233(0,2)(D). The first line shows that the UVLO for VCC has been tripped; the
FAULT output has gone low and the gate drive outputs have been disabled.
is not latched in this case and when VCC is
VCCUV
greater than
, the FAULT output returns to the high impedance state.
VCCUV
The second case shows that the UVLO for VBS has been tripped and that the highꢀside gate drive outputs have been disabled.
After VBS exceeds the , HO will stay low until the HVIC input receives a new falling transition of HIN. The third
VBSUV threshold
case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and
that the gate drive outputs have been disabled and a fault has been reported through the fault pin. The fault output stays in the
low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the voltage on the
FAULT pin will return to VCC
.
VCC
VBS
ꢀꢀꢀ
ITRIP
ꢀꢀꢀ
0 V
0 V
>VITRIP
FAULT
LO
0
LIN
LIN
0
HO
0
0
HIN
0
<
UVLO VCC
UVLO VBS
Normal operation
ITRIP fault
0
VCCUV
15 V
15 V
15 V
<
High impedance
High impedance
0
VBSUV
15 V
15 V
Table 2: IRS233(0,2)(D) UVLO, ITRIP & FAULT truth table
Advanced Input Filter
The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject noise
spikes and short pulses. This input filter has been applied to the HIN and LIN. The working principle of the new filter is shown
in Figures 12 and 13.
Figure 12 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms (Example 1)
show an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the difference between the
input signal and tFIL,IN
.
The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer then
tFIL,IN; the resulting output is approximately the difference between the input signal and tFIL,IN
.
Figure 13 shows the advanced input filter and the symmetry between the input and output. The upper pair of waveforms
(Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the same
duration as the input signal. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer
then tFIL,IN; the resulting output is approximately the same duration as the input signal.
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15
IRS233(0,2)(D)(S&J)PbF
Figure 12: Typical input filter
Figure 13: Advanced input filter
ShortꢀPulse / Noise Rejection
This device’s input filter provides protection against shortꢀpulses (e.g., noise) on the input lines. If the duration of the input
signal is less than tFIL,IN, the output will not change states. Example 1 of Figure 14 shows the input and output in the low state
with positive noise spikes of durations less than tFIL,IN; the output does not change states. Example 2 of Figure 19 shows the
input and output in the high state with negative noise spikes of durations less than tFIL,IN; the output does not change states.
Figure 14: Noise rejecting input filters
Figures 15 and 16 present lab data that illustrates the characteristics of the input filters while receiving ON and OFF pulses.
The input filter characteristic is shown in Figure 15; the left side illustrates the narrow pulse ON (short positive pulse)
characteristic while the left shows the narrow pulse OFF (short negative pulse) characteristic. The xꢀaxis of Figure 20 shows
the duration of PWIN, while the yꢀaxis shows the resulting PWOUT duration. It can be seen that for a PWIN duration less than
tFIL,IN, that the resulting PWOUT duration is zero (e.g., the filter rejects the input signal/noise). We also see that once the PWIN
duration exceed tFIL,IN, that the PWOUT durations mimic the PWIN durations very well over this interval with the symmetry
improving as the duration increases. To ensure proper operation of the HVIC, it is suggested that the input pulse width for the
highꢀside inputs be ≥ 500 ns.
The difference between the PWOUT and PWIN signals of both the narrow ON and narrow OFF cases is shown in Figure 16; the
careful reader will note the scale of the yꢀaxis. The xꢀaxis of Figure 21 shows the duration of PWIN, while the yꢀaxis shows the
resulting PWOUT–PWIN duration. This data illustrates the performance and near symmetry of this input filter.
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IRS233(0,2)(D)(S&J)PbF
Figure 15: IRS233(0,2)(D) input filter characteristic
Figure 16: Difference between the input pulse and the output pulse
Integrated Bootstrap Functionality
The new IRS233(0,2)D family features integrated highꢀvoltage bootstrap MOSFETs that eliminate the need of the external
bootstrap diodes and resistors in many applications.
There is one bootstrap MOSFET for each highꢀside output channel and it is connected between the VCC supply and its
respective floating supply (i.e., VB1, VB2, VB3); see Figure 17 for an illustration of this internal connection.
The integrated bootstrap MOSFET is turned on only during the time when LO is ‘high’, and it has a limited source current due
to RBS. The VBS voltage will be charged each cycle depending on the onꢀtime of LO and the value of the CBS capacitor, the
drainꢀsource (collectorꢀemitter) drop of the external IGBT (or MOSFET), and the lowꢀside freeꢀwheeling diode drop.
The bootstrap MOSFET of each channel follows the state of the respective lowꢀside output stage (i.e., the bootstrap MOSFET
is ON when LO is high, it is OFF when LO is low), unless the VB voltage is higher than approximately 110% of VCC. In that
case, the bootstrap MOSFET is designed to remain off until VB returns below that threshold; this concept is illustrated in Figure
18.
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IRS233(0,2)(D)(S&J)PbF
VB1
VCC
VB2
VB3
Figure 17: Internal bootstrap MOSFET connection
Figure 18: Bootstrap MOSFET state diagram
A bootstrap MOSFET is suitable for most of the PWM modulation schemes and can be used either in parallel with the external
bootstrap network (i.e., diode and resistor) or as a replacement of it. The use of the integrated bootstrap as a replacement of
the external bootstrap network may have some limitations. An example of this limitation may arise when this functionality is
used in nonꢀcomplementary PWM schemes (typically 6ꢀstep modulations) and at very high PWM duty cycle. In these cases,
superior performances can be achieved by using an external bootstrap diode in parallel with the internal bootstrap network.
Bootstrap Power Supply Design
For information related to the design of the bootstrap power supply while using the integrated bootstrap functionality of the
IRS233(0,2)D family, please refer to Application Note 1123 (ANꢀ1123) entitled “Bootstrap Network Analysis: Focusing on the
Integrated Bootstrap Functionality.” This application note is available at www.irf.com.
For information related to the design of a standard bootstrap power supply (i.e., using an external discrete diode) please refer
to Design Tip 04ꢀ4 (DT04ꢀ4) entitled “Using Monolithic High Voltage Gate Drivers.” This design tip is available at www.irf.com.
Separate Logic and Power Grounds
The IRS233(0,2)(D) has separate logic and power ground pin (VSS and VSO respectively) to eliminate some of the noise
problems that can occur in power conversion applications. Current sensing shunts are commonly used in many applications
for power inverter protection (i.e., overꢀcurrent protection), and in the case of motor drive applications, for motor current
measurements. In these situations, it is often beneficial to separate the logic and power grounds.
Figure 19 shows a HVIC with separate VSS and VSO pins and how these two grounds are used in the system. The VSS is
used as the reference point for the logic and overꢀcurrent circuitry; VX in the figure is the voltage between the ITRIP pin and
the VSS pin. Alternatively, the VSO pin is the reference point for the lowꢀside gate drive circuitry. The output voltage used to
drive the lowꢀside gate is VLOꢀVSO; the gateꢀemitter voltage (VGE) of the lowꢀside switch is the output voltage of the driver
minus the drop across RG,LO
.
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IRS233(0,2)(D)(S&J)PbF
DC+ BUS
DBS
VB
(x3)
VCC
CBS
HO
RG,HO
(x3)
VS
(x3)
VS1
VS2
VS3
LO
(x3)
RG,LO
ITRIP
+
+
+
VGE1
VGE2
VGE3
ꢀ
ꢀ
ꢀ
VSS
COM
R2
R0
+
R1
VX
ꢀ
DCꢀ BUS
Figure 19: Separate VSS and VSO pins
Negative VS Transient SOA
A common problem in today’s highꢀpower switching converters is the transient response of the switch node’s voltage as the
power switches transition on and off quickly while carrying a large current. A typical 3ꢀphase inverter circuit is shown in Figure
20; here we define the power switches and diodes of the inverter.
If the highꢀside switch (e.g., the IGBT Q1 in Figures 21 and 22) switches off, while the U phase current is flowing to an
inductive load, a current commutation occurs from highꢀside switch (Q1) to the diode (D2) in parallel with the lowꢀside switch
of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus voltage to the negative
DC bus voltage.
Figure 20: Three phase inverter
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IRS233(0,2)(D)(S&J)PbF
DC+ BUS
Q1
ON
IU
VS1
D2
Q2
OFF
DCꢀ BUS
Figure 21: Q1 conducting
Figure 22: D2 conducting
Also when the V phase current flows from the inductive load back to the inverter (see Figures 23 and 24), and Q4 IGBT
switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2, swings from the
positive DC bus voltage to the negative DC bus voltage.
Figure 23: D3 conducting
Figure 24: Q4 conducting
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it swings
below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”.
The circuit shown in Figure 25 depicts one leg of the three phase inverter; Figures 26 and 27 show a simplified illustration of
the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the
PCB tracks are lumped together in LC and LE for each IGBT. When the highꢀside switch is on, VS1 is below the DC+ voltage
by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the highꢀside power
switch turns off, the load current momentarily flows in the lowꢀside freewheeling diode due to the inductive load connected to
VS1 (the load is not shown in these figures). This current flows from the DCꢀ bus (which is connected to the VSO pin of the
HVIC) to the load and a negative voltage between VS1 and the DCꢀ Bus is induced (i.e., the VSO pin of the HVIC is at a higher
potential than the VS pin).
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IRS233(0,2)(D)(S&J)PbF
Figure 25: Parasitic Elements
Figure 26: VS positive
Figure 27: VS negative
In a typical motor drive system, dV/dt is typically designed to be in the range of 3ꢀ5 V/ns. The negative VS transient voltage
can exceed this range during some events such as short circuit and overꢀcurrent shutdown, when di/dt is greater than in
normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding applications. An
indication of the IRS233(0,2)(D)’s robustness can be seen in Figure 28, where there is represented the IRS233(0,2)(D) Safe
Operating Area at VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area
(outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC
do not appear if negative Vs transients fall inside SOA.
At VBS=15V in case of ꢀVS transients greater than ꢀ16.5 V for a period of time greater than 50 ns; the HVIC will hold by design
the highꢀside outputs in the off state for 4.5 ꢃs.
Figure 28: Negative VS transient SOA for IRS233(0,2)(D)
Even though the IRS233(0,2)(D) has been shown able to handle these large negative VS transient conditions, it is highly
recommended that the circuit designer always limit the negative VS transients as much as possible by careful PCB layout and
component use.
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21
IRS233(0,2)(D)(S&J)PbF
DCꢀ bus Current Sensing
A ground referenced current signal amplifier has been included so that the current in the return leg of the DC bus may be
monitored. A typical circuit configuration is provided in Fig.29. The signal coming from the shunt resistor is amplified by the
ratio (R1+R2)/R2. Additional details can be found on Design Tip DT 92ꢀ6. This design tip is available at www.irf.com.
Figure 29: Current amplifier typical configuration
In the following Figures 30, 31, 32, 33 the configurations used to measure the operational amplifier characteristics are shown.
15V
VCC
15V
1V
CA-
CAO
CC
V
VSO
0V
50pF
VSS
SO
V
CAO
-
CA
SS
V
+
20K
0.2V
T1
T2
1V
0V
1K
90%
SO
V
V
0.2V
ꢀ
SO
V
21
10%
V
T1
V
T2
SR
ꢀ
+
SR
Figure 30: Operational Amplifier Slew rate measurement
Figure 31: Operational Amplifier Input Offset Voltage
measurement
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22
IRS233(0,2)(D)(S&J)PbF
15V
V
CC
-
CA
CAO
VSO
V
SS
at V
CAO2 at V
0.1V
=1.1V
Measure V
=
SO
SO
CAO1
V
(VCAO1 –0.1V)–(VCAO2–1.1V)
1V
(dB)
CMRR ꢀ20 LOG
=
*
Figure 32: Operational Amplifier Common mode rejection
measurement
Figure 33: Operational Amplifier Power supply rejection
measurement
PCB Layout Tips
Distance between high and low voltage components: It’s strongly recommended to place the components tied to the floating
voltage pins (VB and VS) near the respective high voltage portions of the device. The IRS233(0,2)(D) in the PLCC44 package
has had some unused pins removed in order to maximize the distance between the high voltage and low voltage pins.
Please see the Case Outline PLCC44 information in this datasheet for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage
floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 34). In order
to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as
much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collectorꢀtoꢀgate parasitic
capacitance. The parasitic autoꢀinductance of the gate loop contributes to developing a voltage across the gateꢀemitter, thus
increasing the possibility of a self turnꢀon effect.
Figure 34: Antenna Loops
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IRS233(0,2)(D)(S&J)PbF
Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and VSS pins. This connection is
shown in Figure 35. A ceramic 1 ꢃF ceramic capacitor is suitable for most applications. This component should be placed as
close as possible to the pins in order to reduce parasitic elements.
Figure 35: Supply capacitor
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch
node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended
to 1) minimize the highꢀside emitter to lowꢀside collector distance, and 2) minimize the lowꢀside emitter to negative bus rail
stray inductance. However, where negative VS spikes remain excessive, further steps may be taken to reduce the spike. This
includes placing a resistor (5 ꢂ or less) between the VS pin and the switch node (see Figure 36), and in some cases using a
clamping diode between VSS and VS (see Figure 37). See DT04ꢀ4 at www.irf.com for more detailed information.
Figure 36: VS resistor
Figure 37: VS clamping diode
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IRS233(0,2)(D)(S&J)PbF
Integrated Bootstrap FET limitation
The integrated Bootstrap FET functionality has an operational limitation under the following bias conditions applied to the
HVIC:
•
•
VCC pin voltage = 0V
VS or VB pin voltage > 0
AND
In the absence of a VCC bias, the integrated bootstrap FET voltage blocking capability is compromised and a current
conduction path is created between VCC & VB pins, as illustrated in Fig.38 below, resulting in power loss and possible
damage to the HVIC.
Figure 38: Current conduction path between VCC and VB pin
Relevant Application Situations:
The above mentioned bias condition may be encountered under the following situations:
•
In a motor control application, a permanent magnet motor naturally rotating while VCC power is OFF. In this
condition, Back EMF is generated at a motor terminal which causes high voltage bias on VS nodes resulting
unwanted current flow to VCC.
•
Potential situations in other applications where VS/VB node voltage potential increases before the VCC
voltage is available (for example due to sequencing delays in SMPS supplying VCC bias)
Application Workaround:
Insertion of a standard pꢀn junction diode between VCC pin of IC and positive terminal of VCC capacitors (as illustrated in
Fig.39) prevents current conduction “outꢀof” VCC pin of gate driver IC. It is important not to connect the VCC capacitor
directly to pin of IC. Diode selection is based on 25V rating or above & current capability aligned to ICC consumption of IC
ꢀ 100mA should cover most application situations. As an example, Part number # LL4154 from Diodes Inc (25V/150mA
standard diode) can be used.
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IRS233(0,2)(D)(S&J)PbF
VCC
VB
VCC
Capacitor
VSS
(or COM)
Figure 39: Diode insertion between VCC pin and VCC capacitor
Note that the forward voltage drop on the diode (VF) must be taken into account when biasing the VCC pin of the IC to
meet UVLO requirements. VCC pin Bias = VCC Supply Voltage – VF of Diode.
Additional Documentation
Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and
the document number to quickly locate them. Below is a short list of some of these documents.
DT97ꢀ3: Managing Transients in Control IC Driven Power Stages
ANꢀ1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality
DT04ꢀ4: Using Monolithic High Voltage Gate Drivers
ANꢀ978: HV Floating MOSꢀGate Driver ICs
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IRS233(0,2)(D)(S&J)PbF
Parameter Temperature Trends
Figures 40ꢀ78 provide information on the experimental performance of the IRS233(0,2)(D)(S&J) HVIC. The line plotted in each
figure is generated from actual lab data. A small number of individual samples were tested at three temperatures (ꢀ40 ºC, 25 ºC,
and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data points (one data point
at each of the tested temperatures) that have been connected together to illustrate the understood temperature trend. The
individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given
temperature).
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
Exp.
Exp.
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 40. Turnꢀon Propagation Delay vs.
Temperature
Fig. 41. Turnꢀon Propagation Delay vs.
Temperature
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
Exp.
Exp.
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 42. Turnꢀoff Propagation Delay vs.
Temperature
Fig. 43. Turnꢀoff Propagation Delay vs.
Temperature
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IRS233(0,2)(D)(S&J)PbF
200
180
160
140
120
100
80
60
50
40
30
20
10
0
Exp.
Exp.
60
40
20
0
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 44. Turnꢀon Rise Time vs. Temperature
Fig.45. Turnꢀoff Fall Time vs. Temperature
1000
900
1000
900
800
700
600
500
400
300
200
100
0
800
Exp.
700
Exp.
600
500
400
300
200
100
0
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 46. ITRIP to Output Shutdown Propagation
Delay vs. Temperature
Fig. 47. ITRIP to FAULT Indication Delay vs.
Temperature
16000
14000
1200
1000
12000
Exp.
Exp.
800
10000
8000
6000
4000
2000
0
600
400
200
0
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig.48. FAULT Clear Time vs. Temperature
Fig. 49. Dead Time vs. Temperature
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IRS233(0,2)(D)(S&J)PbF
60
50
40
30
20
10
0
6
5
4
3
2
1
0
Exp.
Exp.
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 51. Operational Amplifier Slew Rate (ꢀ) vs.
Temperature
Fig. 50. Operational Amplifier Slew Rate (+) vs.
Temperature
2.5
2.5
Exp.
Exp.
2.0
2.0
1.5
1.0
0.5
0.0
1.5
1.0
0.5
0.0
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 52. Input Positive Going Threshold vs.
Temperature
Fig. 53. Input Negative Going Threshold vs.
Temperature
800
800
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
EXP.
Exp.
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 54. ITRIP Input Positive Going Threshold
vs. Temperature
Fig. 55. ITRIP Input Negative Going Threshold
vs. Temperature
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IRS233(0,2)(D)(S&J)PbF
450
400
350
300
250
200
150
100
50
60
50
40
30
20
10
0
Exp.
Exp.
0
ꢀ50
ꢀ25
0
25
50
75
100
125
125
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 56. Low Level Output Voltage vs.
Temperature
Fig. 57. Offset Supply Leakage Current vs.
Temperature
12
10
8
7
6
5
4
3
2
1
0
Exp.
Exp.
6
4
2
0
ꢀ50
ꢀ25
0
25
50
75
100
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 58. Quiescent VCC Supply Current vs.
Temperature
Fig. 59. Quiescent VCC Supply Current vs.
Temperature
80
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
Exp.
Exp.
ꢀ50
ꢀ25
0
25
50
75
100
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 60. Quiescent VBS Supply Current vs.
Temperature
Fig. 61. Quiescent VBS Supply Current vs.
Temperature
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IRS233(0,2)(D)(S&J)PbF
9.8
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.2
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
7.8
Exp.
Exp.
ꢀ50
ꢀ25
0
25
50
75
100
125
125
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 62. VCC Supply Undervoltage Negative
Going Threshold vs. Temperature
Fig. 63. VCC Supply Undervoltage Positive
Going Threshold vs. Temperature
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
9.0
8.5
8.0
7.5
7.0
6.5
6.0
Exp.
Exp.
ꢀ50
ꢀ25
0
25
50
75
100
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 64. VBS Supply Undervoltage Negative
Going Threshold vs. Temperature
Fig. 65. VBS Supply Undervoltage Positive
Going Threshold vs. Temperature
0
90
80
70
60
50
40
30
20
10
0
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ100
ꢀ150
ꢀ200
ꢀ250
ꢀ300
ꢀ350
ꢀ400
ꢀ450
Exp.
Exp.
ꢀ50
ꢀ25
0
25
50
75
100
Temperature (oC)
Temperature (oC)
Fig. 66. FAULT Low OnꢀResistance vs.
Temperature
Fig. 67. Output High Short Circuit Pulsed
Current vs. Temperature
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IRS233(0,2)(D)(S&J)PbF
706
606
506
406
306
206
106
6
20
15
10
5
Exp.
Exp.
0
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ5
ꢀ10
ꢀ15
ꢀ20
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 68. Output Low Short Circuit Pulsed
Current vs. Temperature
Fig. 69. Offset Opamp vs. Temperature
200
200
180
160
140
120
100
80
180
160
140
120
100
80
Exp.
Exp.
60
60
40
40
20
20
0
0
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 70. Operational Amplifier Power Supply
Rejection Ratio vs. Temperature
Fig. 71. Operational Amplifier Common Mode
Rejection Ratio vs. Temperature
5.6
35
30
25
20
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
Exp.
15
Exp.
10
5
0
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 72. Operational Amplifier High Level Output
Voltage vs. Temperature
Fig. 73. Operational Amplifier Low Level
Output Voltage vs. Temperature
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32
IRS233(0,2)(D)(S&J)PbF
6
5
4
3
2
1
0
16
14
12
10
8
Exp.
Exp.
6
4
2
0
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 74. Operational Amplifier Output Sink
Current vs. Temperature
Fig. 75. Operational Amplifier Output Low
Short Circuit Current vs. Temperature
0
0
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ2
ꢀ4
ꢀ5
ꢀ10
ꢀ15
ꢀ20
ꢀ25
ꢀ30
ꢀ35
ꢀ6
Exp.
ꢀ8
Exp.
ꢀ10
ꢀ12
ꢀ14
ꢀ16
Temperature (oC)
Temperature (oC)
Fig. 76. Operational Amplifier Output Source
Current vs. Temperature
Fig. 77. Operational Amplifier Output High
Short Circuit Current vs. Temperature
0
ꢀ50
ꢀ25
0
25
50
75
100
125
ꢀ2
ꢀ4
ꢀ6
ꢀ8
Exp.
ꢀ10
ꢀ12
ꢀ14
Temperature (oC)
Fig. 78. Max –Vs vs. Temperature
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33
IRS233(0,2)(D)(S&J)PbF
Case Outlines
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34
IRS233(0,2)(D)(S&J)PbF
Case Outlines
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35
IRS233(0,2)(D)(S&J)PbF
Tape and Reel Details: SOIC28W
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 28SOICW
Metric
Imperial
Code
A
B
C
D
E
F
G
H
Min
11.90
3.90
23.70
11.40
10.80
18.20
1.50
Max
12.10
4.10
24.30
11.60
11.00
18.40
n/a
Min
Max
0.476
0.161
0.956
0.456
0.433
0.724
n/a
0.468
0.153
0.933
0.448
0.425
0.716
0.059
0.059
1.50
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 28SOICW
Metric
Imperial
Min
Code
A
B
C
D
Min
329.60
20.95
12.80
1.95
Max
330.25
21.45
13.20
2.45
102.00
30.40
29.10
26.40
Max
13.001
0.844
0.519
0.096
4.015
1.196
1.145
1.039
12.976
0.824
0.503
0.767
3.858
n/a
E
F
98.00
n/a
G
H
26.50
24.40
1.04
0.96
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36
IRS233(0,2)(D)(S&J)PbF
Tape and Reel Details: PLCC44
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 44PLCC
Metric
Imperial
Code
A
B
C
D
E
F
G
H
Min
23.90
3.90
31.70
14.10
17.90
17.90
2.00
Max
24.10
4.10
32.30
14.30
18.10
18.10
n/a
Min
0.94
Max
0.948
0.161
1.271
0.562
0.712
0.712
n/a
0.153
1.248
0.555
0.704
0.704
0.078
0.059
1.50
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 44PLCC
Metric
Imperial
Max
Code
A
B
C
D
Min
329.60
20.95
12.80
1.95
Max
330.25
21.45
13.20
2.45
Min
12.976
0.824
0.503
0.767
3.858
n/a
13.001
0.844
0.519
0.096
4.015
1.511
1.409
1.303
E
F
98.00
n/a
102.00
38.4
G
34.7
35.8
1.366
1.283
H
32.6
33.1
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37
IRS233(0,2)(D)(S&J)PbF
Complete Part Number
Ordering Information
Standard Pack
Base Part Number Package Type
Form
Quantity
Tube/Bulk
Tape and Reel
Tube/Bulk
Tape and Reel
25
1000
27
IRS233(0,2)(D)SPbF
IRS233(0,2)(D)STRPbF
IRS233(0,2)(D)JPbF
IRS233(0,2)(D)JTRPbF
SOIC28W
IRS233(0,2)(D)
PLCC44
500
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other
rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or
patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document
supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technicalꢀinfo/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252ꢀ7105
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38
IRS233(0,2)(D)(S&J)PbF
Change History
Revision Date
Change comments
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
10/17/07
Initial data sheet converted from IRS2130xD data sheet
Initial Review
Included triꢀtemp plots
Updated test conditions
Updated limits using DR3 Limits table
Included application notes
Updated minor errors and completed review for DR3
Corrected reflow temperature for PLCC44 to 245°C
Added Integrated Operational Amplifier feature on front page
and RoHS compliant.
03/05/08
03/18/08
03/18/08
03/26/08
03/27/08
03/27/08
03/28/08
04/02/08
0.9
1.0
1.1
1.2
04/11/08
04/15/08
04/16/08
04/28/08
Corrected logic level compatible on Page1 from 2.5V to 3.3V
Added MDT parameter
Updated MDT spec. and changed latchꢀup level to A
Removed typical MDT spec.; MDT expected to be zero and
cannot be more than maximum spec.
Changed file format from “rev1.2” to May 8, 2008. Corrected
part number in Fig. 15
May 8, 08
July 8, 08
changed Iqcc test condition to Vin=4V from 0V.
June 1, 11 Add bootstrap fet limitation
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39
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