IRS2334STRPBF_技术文档

27 January 2011

IRS2334SPbF/IRS2334MPbF

3 PHASE GATE DRIVER HVIC

Product Summary

Features



Floating channel designed for bootstrap operation

Topology

3 phase

≤ 600 V

Fully operational to 600 V

Tolerant to negative transient voltage, dV/dt immune

Gate drive supply range from 10 V to 20 V

Integrated dead time protection

Shoot-through (cross-conduction) prevention logic

Under-Voltage lockout for both channels

Independent 3 half-bridge drivers

3.3 V input logic compatible

V_OFFSET

V_OUT

10 V – 20 V

200 mA & 350 mA

530 ns

I_o+& I _o-(typical)

t_ON& t_OFF(typical)

Advanced input filter

Package Options

Matched propagation delay for both channels

Lower di/dt gate driver for better noise immunity

Outputs in phase with inputs

RoHS compliant

Typical Applications

20 leads wide body SOIC



Motor Control

Low Power Fans

General Purpose Inverters

Micro/Mini Inverter Drivers

28 leads MLPQ 5x5 (32 leads without 4)

Typical Connection Diagram

Up to 600V

Vcc

HIN1,2,3

LIN1,2,3

V

1,2,3

B

HIN1,2,3

LIN1,2,3

HO1,2,3

V

1,2, 3

S

TO

LOAD

LO1,2,3

COM

IRS2334

GND

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02-Apr-10

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IRS2334SPbF/MPbF

Table of Contents

Page

3

Description

Simplified Block Diagram

Typical Application Diagram

Qualification Information

Absolute Maximum Ratings

Recommended Operating Conditions

Static Electrical Characteristics

Dynamic Electrical Characteristics

Functional Block Diagram

Input/Output Pin Equivalent Circuit Diagram

Lead Definitions

3

4

5

6

7

8

9

10

11

12

21

25

27

29

30

Lead Assignments

Application Information and Additional Details

Parameter Temperature Trends

Package Details

Tape and Reel Details

Part Marking Information

Ordering Information

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IRS2334SPbF/MPbF

Description

The IRS2334 is a high voltage, high speed power MOSFET and IGBT driver with three independent high side

and low side referenced output channels for 3-phase applications. Proprietary HVIC and latch immune CMOS

technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL

outputs, down to 3.3 V. The output drivers feature a high pulse current buffer stage designed for minimum

driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The

floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration up

to 600 V.

Simplified Block Diagram

HV floating well

Schmitt trigger, minimum dead time

and shoot-through protection

to high side

power switches

(x3)

HV Level

Shifters

Delay

to low side

power switches

(x3)

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IRS2334SPbF/MPbF

Typical Application Diagram

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IRS2334SPbF/MPbF

Qualification Information^†

Qualification Level

Industrial^††

Comments: This IC has passed JEDEC industrial

qualification. IR consumer qualification level is granted by

extension of the higher Industrial level.

MSL2 , 260C

(per IPC/JEDEC J-STD-020)

Moisture Sensitivity Level

Class 1C

(per JEDEC standard JESD22-A114)

Class B

Human Body Model

Machine Model

ESD

(per EIA/JEDEC standard EIA/JESD22-A115)

Class I, Level A

(per JESD78)

IC Latch-Up Test

RoHS Compliant

Yes

†

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

†† Higher qualification ratings may be available should the user have such requirements. Please contact your

International Rectifier sales representative for further information.

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IRS2334SPbF/MPbF

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM unless otherwise specified. The thermal resistance and

power dissipation ratings are measured under board mounted and still air conditions.

Symbol

Definition

Min.

Max.

Units

V_B

V_S

High side floating supply voltage

High side floating supply offset voltage

High side floating output voltage

Low side and logic fixed supply voltage

Low side output voltage

-0.3

625

V_B1,2,3- 25^†

V

_B1,2,3+ 0.3

V_HO1,2,3

V_CC

V_LO1,2,3

V_IN

PW_HIN

dV_S/dt

V_S1,2,3- 0.3

-0.3

500

—

V_B1,2,3+ 0.3

V

25^†

V_CC+ 0.3

—

Logic and analog input voltages

High-side input pulse width

ns

Allowable offset supply voltage slew rate

50

V/ns

20 lead SOIC

28 lead MLPQ

20 lead SOIC

28 lead MLPQ

—

1.14

3.363

65.8

P_D

W

Package power dissipation @ TA ≤ 25°C

Rth_JA

Thermal resistance, junction to ambient

°C/W

22.3

T_J

T_S

T_L

Junction temperature

Storage temperature

—

-55

150

°C

Lead temperature (soldering, 10 seconds)

—

300

†

All supplies are fully tested at 25 V. An internal 25 V clamp exists for each supply.

Recommended Operating Conditions

For proper operation, the device should be used within the recommended conditions. All voltage parameters are

absolute voltages referenced to COM unless otherwise specified. The V_S1,2,3offset ratings are tested with all

supplies biased at 15 V.

Symbol

Definition

Min.

Max.

Units

V_B1,2,3

V_S1,2,3

V_S1,2,3(t)

V_HO1,2,3

V_CC

High side floating supply voltage

Static high side floating supply offset voltage^†

Transient high side floating supply offset voltage^††

High side floating output voltage

Low side and logic fixed supply voltage

Low side output voltage

V_S1,2,3+10

V_S1,2,3+ 20

600

-8

-50

V_S1,2,3

10

600

V

V_B1,2,3

20

V_LO1,2,3

V_IN

0

V_CC

Logic input voltage

T_A

Ambient temperature

-40

125

°C

†

V

Logic operation for _Sof –8 V to 600 V. Logic state held for _Sof –8 V to –V_BS.

†† Operational for transient negative V_Sof -50 V with a 50 ns pulse width. Guaranteed by design. Refer to the

Application Information section of this datasheet for more details.

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IRS2334SPbF/MPbF

Static Electrical Characteristics

o

(V_CC-COM) = (V_B1,2,3-V_S1,2,3) = 15 V and T_A= 25 C unless otherwise specified. The V_INand I_INparameters are

referenced to COM. The V_Oand I_Oparameters are referenced to COM and V_S1,2,3and are applicable to the output

leads LO1,2,3 and HO1,2,3 respectively. The

and

parameters are referenced to COM and V_S

V_CCUV

V_BSUV

respectively.

Symbol

V_IH

Definition

Logic “1” input voltage

Min. Typ. Max. Units

Test Conditions

2.5

—

0.8

—

V_IL

Logic “0” input voltage

—

V_IN,_TH+

V_IN,_TH-

V_OH

Input positive going threshold

Input negative going threshold

High level output voltage

Low level output voltage

1.9

1

—

0.9

0.4

1.4

0.6

I_O= 20 mA

V

V_OL

V_CCUV+

V_BSUV+

V_CCUV-

V_BSUV-

V_CCUVH

V_BSUVH

V_CCand V_BSsupply under-voltage positive

going threshold

V_CCand V_BSsupply under-voltage negative

going threshold

10.4 11.1

10.2 10.9

11.6

11.4

—

V_CCand V_BSsupply under-voltage hysteresis

0.1

0.2

I_LK

I_QBS

I_QCC

I_IN+

I_IN-

Offset supply leakage current

Quiescent V_BSsupply current

Quiescent V_CCsupply current

Logic “1” input bias current

—

1

50

120

700

250

1

V_B=V_S= 600 V

V_IN= 0 V

µA

40

—

300

150

—

V_IN= 5 V

V_IN= 0 V

Logic “0” input bias current

—

I_o+

Output high short circuit pulsed current

Output low short circuit pulsed current

120

250

200

350

—

V_O= 0 V or 15 V

mA

PW ≤ 10 µs

I_o-

—

Dynamic Electrical Characteristics

V_CC= V_B1,2,3= 15 V, V_S1,2,3= COM, T_A= 25 ^oC and C_L= 1000 pF unless otherwise specified.

Symbol

Definition

Min. Typ. Max. Units

Test Conditions

t_on

t_off

t_r

Turn-on propagation delay

Turn-off propagation delay

Turn-on rise time

400

—

530

125

50

750

190

75

V_IN= 0V and 5V

t_f

Turn-off fall time

—

ns

t_FILIN

DT

MDT

MT

PM

Input filter time

200

190

—

350

290

—

510

420

60

Dead time

V_IN= 0V & 5V

External dead time

0s

Dead time matching

t_on, t_offpropagation delay matching time

PW pulse width distortion^†

—

50

—

75

PW input =10µs

†

PM is defined as PW_IN- PW_OUT.

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IRS2334SPbF/MPbF

Functional Block Diagram

VB1

Input

Noise

Filter

SET

Latch

HV

Level

Shifter

HIN1

LIN1

Deadtime &

Shoot-Through

Prevention

HO1

VS1

Driver

SD

UV

Detect

RESET

Input

Noise

Filter

Input

Noise

Filter

VB2

HO2

VS2

HIN2

LIN2

SET

Latch

HV

Level

Shifter

Deadtime &

Shoot-Through

Prevention

Driver

UV

Detect

Input

Noise

Filter

RESET

Input

Noise

Filter

VB3

HO3

VS3

HIN3

LIN3

SET

Latch

Deadtime &

Shoot-Through

Prevention

HV

Level

Shifter

SD

Driver

UV

Detect

Input

Noise

Filter

RESET

VCC

UV

Detect

LO1

Driver

Delay

LO2

Delay

LO3

Delay

COM

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IRS2334SPbF/MPbF

Input/Output Pin Equivalent Circuit Diagrams

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IRS2334SPbF/MPbF

Lead Definitions

Symbol

Description

VCC

VB1

VB2

VB3

VS1

VS2

VS3

HIN1

HIN2

HIN3

LIN1

LIN2

LIN3

HO1

HO2

HO3

LO1

LO2

LO3

COM

Low side and logic power supply

High side floating power supply (phase 1)

High side floating power supply (phase 2)

High side floating power supply (phase 3)

High side floating supply return (phase 1)

High side floating supply return (phase 2)

High side floating supply return (phase 3)

Logic input for high side gate driver output HO1, input is in-phase with output

Logic input for high side gate driver output HO2, input is in-phase with output

Logic input for high side gate driver output HO3, input is in-phase with output

Logic input for low side gate driver output LO1, input is in-phase with output

Logic input for low side gate driver output LO2, input is in-phase with output

Logic input for low side gate driver output LO3, input is in-phase with output

High side gate driver output (phase 1)

High side gate driver output (phase 2)

High side gate driver output (phase 3)

Low side gate driver output (phase 1)

Low side gate driver output (phase 2)

Low side gate driver output (phase 3)

Low side supply return

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IRS2334SPbF/MPbF

Lead Assignments

20 leads wide body SOIC

32 leads MLPQ 5x5 without 4 leads

VS1

HO1

VB1

1

2

3

24

23

22

21

20 VCC

HIN1

HIN2

HIN3

6

7

8

19

18

17

LO1

LO2

LO3

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IRS2334SPbF/MPbF

Application Information and Additional Details



IGBT/MOSFET Gate Drive

Switching and Timing Relationships

Deadtime

Matched Propagation Delays

Input Logic Compatibility

Shoot-Through Protection

Under-Voltage Lockout Protection

Truth Table: Under-Voltage lockout

Advanced Input Filter

Short-Pulse and Noise Rejection

Tolerant to Negative V_STransients

PCB Layout Tips

Additional Documentation

IGBT/MOSFET Gate Drive

The IRS2334 HVIC is designed to drive high side and low side MOSFET or IGBT power devices. Figures 1 and 2

show the definition of some of the relevant parameters associated with the gate driver output functionality. The

output current that drives the gate of the external power switches is defined as I_O. The output voltage that drives

the gate of the external power switches is defined as V_HOfor the high side and V_LOfor the low side; this

parameter is sometimes generically called V_OUTand in this case the high side and low side output voltages are

not differentiated.

V_B

(or V_CC)

I_O+

H

(or LO)

+

I_O-

V_H(or V_L)

-

V_S

(or

)

(or

)

Figure 1: HVIC sourcing current

Figure 2: HVIC sinking current

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IRS2334SPbF/MPbF

Switching and Timing Relationships

The relationship between the input and output signals of the IRS2334 HVIC is shown in Figure 3. The definitions

of some of the relevant parameters associated with the gate driver input to output transmission are given.

LIN

or HIN

50%

PW

IN

t_OFF

t_F

t_ONt_R

PW

OUT

90%

10%

90%

LO

or HO

10%

Figure 3: Switching time waveforms

During interval A of Figure 4 the HVIC receives the command to turn on both the high and low side switches at

the same time; correspondingly, the shoot-through protection prevents the high and low side signals HO and LO

turn on by keeping them low.

Figure 4: Input/output timing diagram

Deadtime

The IRS2334 HVIC provides an integrated deadtime protection circuitry. The deadtime interval for this HVIC is

fixed; while other ICs within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The

deadtime feature inserts a time interval in which both the gate driver outputs LO and HO are held off; to ensure

that the power switch being turned off has fully turned off before the second power switch is turned on. This

minimum deadtime is automatically inserted whenever the external deadtime commanded by the host

microcontroller is shorter than DT, while external deadtimes larger than DT are not modified by the gate driver.

Figure 7 illustrates the deadtime interval definition and the relationship between the output gate signals.

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IRS2334SPbF/MPbF

The deadtime interval introduced is matched with respect to the commutation from HIN turning off to LIN turning

on, and viceversa. Figure 5 defines the two deadtime parameters DT1 and DT2. The deadtime matching

parameter MDT is defined as the maximum difference between DT1 and DT2.

LIN

HIN

50%

LO

DT1

DT2

HO

50%

Figure 5: Deadtime definition

Matched Propagation Delays

The IRS2334 HVIC is designed for propagation delay matching. With this feature, the input to output propagation

delays t_ON, t_OFFare the same for the low side and the high side channels; the maximum difference being specified

by the delay matching parameter MT as defined in Figure 6.

Figure 6: Delay Matching Waveform Definition

Input Logic Compatibility

The IRS2334 HVIC is designed with inputs compatible with standard CMOS and TTL outputs with 3.3 V and 5 V

logic level signals. Figure 7 shows how an input signal is logically interpreted.

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IRS2334SPbF/MPbF

Figure 7: HIN & LIN input thresholds

Shoot-Through Protection

The IRS2334 is equipped with a shoot-through protection circuitry which prevents cross-conduction of the power

switches. Table 1 shows the input to output relationship in the form of a truth table. Note that the HVIC has non-

inverting inputs (the output is in-phase with the respective input).

HIN

0

LIN

0

HO

0

LO

0

1

0

1

0

1

0

1

0

Table 1: Input/output truth table

Under-Voltage Lockout Protection

The IRS2334 HVIC provides under-voltage lockout protection on both the V_CClow side and logic fixed power

supply and the VBS high side floating power supply. Figure 8 illustrates this concept by considering the V_CC(or

V_BS) plotted over time: as the waveform crosses the UVLO threshold, the under-voltage protection is entered or

exited.

Upon power up, should the V_CCvoltage fail to reach the V_CCUV+threshold, the gate driver outputs LO and HO will

remain disabled. Additionally, if the V_CCvoltage decreases below the V_CCUV-threshold during normal operation,

the under-voltage lockout circuitry will shutdown the gate driver outputs LO and HO.

Upon power up, should the V_BSvoltage fail to reach the V_BSUVthreshold, the gate driver output HO will remain

disabled. Additionally, if the V_BSvoltage decreases below the V_BSUVthreshold during normal operation, the under-

voltage lockout circuitry will shutdown the high side gate driver output HO.

The UVLO protection ensures that the HVIC drives external power devices only with a gate supply voltage

sufficient to fully enhance them. Without this protection, the gates of the external power switches could be driven

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IRS2334SPbF/MPbF

with a low voltage, which would result in power switches conducting current while with a high channel impedance,

which would produce very high conduction losses possibly leading to power device failure.

V_CC

(or

)

B

V_CCU

+

(or

)

+

BSU

V_CCU

-

(or

)

-

BSU

Time

UVLO Protection

(Gate Driver Outputs Disabled)

Norma

Operation

Norma

Operation

Figure 8: UVLO protection

Truth Table: Under-Voltage lockout

Table 2 provides the truth table for the IRS2334 HVIC.

The 1^stline shows that for V_CCbelow the UVLO threshold both the gate driver outputs LO and HO are disabled.

fter V returns above , the gate driver outputs return functional.

A

V_CCUV

CC

The 2^ndline shows that for V_BSbelow the UVLO threshold, the gate driver output HO is disabled. After V_BSreturns

above , HO remains low until a new rising transition of HIN is received.

V_BSUV

The last line shows the normal operation of the HVIC.

outputs

LO

VCC

VBS

HO

<

0

LIN

0

HIN

UVLO V_CC

UVLO V_BS

Normal operation

V_CCUV

15 V

<

V_BSUV

15 V

Table 2: UVLO truth table

Advanced Input Filter

The IRS2334 HVIC provides an advanced input filter that improves the input/output pulse symmetry of the signals

processed by the HVIC. This input filter is inserted at the HIN and LIN input pins. The working principle of the

filter is shown in Figures 9 and 10.

Figure 9 shows a typical input filter and the asymmetry it produces on its output signal. The upper waveforms of

Example 1 show an input signal with a pulse duration mush longer than the filtering time t_FILIN; the resulting output

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IRS2334SPbF/MPbF

signal has a duration given approximately by the difference between the input signal and t_FILIN. The lower

waveforms of Example 2 show an input signal with a pulse duration slightly longer than the filtering time t_FILIN; the

resulting output signal has a duration given approximately by the difference between the input signal and t_FILIN,

much shorter than it should be.

Figure 10 shows the advanced input filter and the symmetry it produces on its output signal. The upper

waveforms of Example 1 show an input signal with a pulse duration much longer than the filtering time t_FILIN; the

resulting output signal has approximately the same duration as the input signal. The lower waveforms of Example

2 show an input signal with a pulse duration slightly longer than the filtering time t_FILIN; the resulting output signal

has approximately the same duration as the input signal.

Figure 9: Typical input filter

Figure 10: Advanced input filter

Short-Pulse and Noise Rejection

The advanced input filter that improves the input/output pulse symmetry of the signals processed by the HVIC

also helps the rejection of noise spikes and of short pulses on the input signals.

Input signals with a pulse duration less than the filtering time t_FILINwill be filtered out. In Figure 11 Example 1

shows an input signal in the low state with superimposed positive noise spikes of duration less than t_FILIN; the

advanced input filter filters out the noise spikes and the output signal remains in the low state. Example 2 shows

an input signal in the high state with superimposed negative noise spikes of duration less than t_FILIN; the

advanced input filter filters out the noise spikes and the output signal remains in the high state.

Figure 11: Noise rejection of the advanced input filter

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IRS2334SPbF/MPbF

The measured characteristic of the advanced input filter is shown in Figure 12. On the left side the characteristic

for narrow ON pulses is shown (short positive pulse) while on the left side the characteristic for narrow OFF

pulses is shown (short negative pulse). The x-axis represents the input pulse duration PW_IN, while the y-axis the

resulting output pulse duration PW_OUT. For pulses with input pulse duration PW_INless than the filtering time t_FILIN

the resulting output pulse duration PW_OUTis zero because the filter rejects the input signal. For pulses with input

pulse duration PW_INgreater than the filtering time t_FILINthe resulting output pulse duration PW_OUTtracks the input

pulse durations well, the higher the duration the better the symmetry.

Figure 12: Measured advanced input filter characteristic

The difference between the output pulse duration PW_OUTand the input pulse duration PW_INof both the narrow

ON and narrow OFF cases is shown in Figure 13. The x-axis represents the input pulse duration PW_IN, while the

y-axis the resulting difference PW_OUT–PW_IN.

Figure 13: Difference between the input pulse duration and the output pulse duration

Tolerant to Negative VS Transients

A common problem in today’s high-power switching converters is the transient response of the switch node’s

voltage as the power devices switch on and off quickly while carrying a large current. A typical 3-phase inverter

circuit is shown in Figure 14; where we define the power switches and diodes of the inverter.

If the high-side switch (e.g., the IGBT Q1 in Figures 15 and 16) switches off, while the U phase current is flowing

to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with

the low-side switch of the same inverter leg. At the same instance, the voltage node V_S1, swings from the positive

DC bus voltage to the negative DC bus voltage.

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IRS2334SPbF/MPbF

Figure 14: Three phase inverter

DC+ BUS

Q1

ON

I_U

V_S1

D2

Q2

OFF

DC- BUS

Figure 15: Q1 conducting

Figure 16: D2 conducting

Also when the V phase current flows from the inductive load back to the inverter (see Figures 17 and 18), and Q4

IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V_S2,

swings from the positive DC bus voltage to the negative DC bus voltage.

DC+ BUS

D3

Q3

OFF

I_V

V_S2

D4

Q4

OFF

DC- BUS

Figure 17: D3 conducting

Figure 18: Q4 conducting

However, in a real inverter circuit, the V_Svoltage swing does not stop at the level of the negative DC bus, rather it

swings below the level of the negative DC bus. This undershoot voltage is called “negative V_Stransient”.

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IRS2334SPbF/MPbF

The circuit shown in Figure 19 depicts one leg of the three phase inverter; Figures 20 and 21 show a simplified

illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit

from the die bonding to the PCB tracks are lumped together in L_Cand L_Efor each IGBT. When the high-side

switch is on, V_S1is below the DC+ voltage by the voltage drops associated with the power switch and the

parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in

the low-side freewheeling diode due to the inductive load connected to V_S1(the load is not shown in these

figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a

negative voltage between V_S1and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential

than the V_Spin).

Figure 19: Parasitic Elements

Figure 20: V_Spositive

Figure 21: V_Snegative

In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative V_S

transient voltage can exceed this range during some events such as short circuit and over-current shutdown,

when di/dt is greater than in normal operation.

International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding

applications. An indication of the IRS2334’s robustness can be seen in Figure 22, where there is represented the

IRS2334 Safe Operating Area at V_BS=15V based on repetitive negative V_Sspikes. A negative V_Stransient voltage

falling in the grey area (outside SOA) may lead to IC permanent damage; vice versa unwanted functional

anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside SOA.

At V_BS=15V in case of -V_Stransients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will

hold by design the high-side outputs in the off state for 4.5 μs.

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IRS2334SPbF/MPbF

Figure 22: Negative V_Stransient SOA @ VBS=15V

Even though the IRS2334 has been shown able to handle these large negative VS transient conditions, it is

highly recommended that the circuit designer always limit the negative V_Stransients as much as possible by

careful PCB layout and component use.

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IRS2334SPbF/MPbF

PCB Layout Tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied to

the floating voltage pins (V_Band V_S) near the respective high voltage portions of the device. Please see the Case

Outline information in this datasheet for the details.

Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high

voltage floating side.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure

23). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive

loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the

IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to

developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.

I_GC

V_B

(or

)

CC

C_GC

G

R

H

(or

)

Gate Drive

Loo

V_GE

V_S

(or

)

Figure 23: Antenna Loops

Supply Capacitor: It is recommended to place a bypass capacitor between the VCC and COM pins. This

connection is shown in Figure 24. A ceramic 1 μF ceramic capacitor is suitable for most applications. This

component should be placed as close as possible to the pins in order to reduce parasitic elements.

Up to 600V

Vcc

HIN1,2,3

LIN1,2,3

V

B1,2,3

HIN1,2,3

LIN1,2,3

HO1,2,3

V

S1,2,3

TO

LOAD

LO1,2,3

COM

GND

Figure 24: Supply capacitor

www.irf.com

22

IRS2334SPbF/MPbF

Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients

at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such

conditions, it is recommended to 1) minimize the high-side source to low-side collector distance, and 2) minimize

the low-side emitter to negative bus rail stray inductance. However, where negative V_Sspikes remain excessive,

further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the V_Spin

and the switch node (see Figure 25), and in some cases using a clamping diode between COM and V_S(see

Figure 26). See DT04-4 at www.irf.com for more detailed information.

DC+ BU

V_B

HO

V_S

L

V_B

HO

V_S

L

C_BS

R_VS

T

Load

T

Load

D_VS

CO

DC- BU

Figure 25: V_Sresistor

Figure 26: V_Sclamping diode

Additional Documentation

Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search

function and the document number to quickly locate them. Below is a short list of some of these documents.

DT97-3: Managing Transients in Control IC Driven Power Stages

AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality

DT04-4: Using Monolithic High Voltage Gate Drivers

AN-978: HV Floating MOS-Gate Driver ICs

Parameter Temperature Trends

Figures 27-44 provide information on the experimental performance of the IRS2334 HVIC. The line plotted in

each figure is generated from actual experimental data. A small number of individual samples were tested at

three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental curve. The line labeled

Exp. consist of three data points (one data point at each of the tested temperatures) that have been

connected together to illustrate the understood temperature trend. The individual data points on the curve

were determined by calculating the averaged experimental value of the parameter (for a given temperature).

www.irf.com

23

IRS2334SPbF/MPbF

800

700

600

500

400

300

200

100

0

1000

800

600

400

200

0

Exp.

-50

-25

0

25

50

75

100 125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 27. Turn-on Propagation Delay vs. Temperature

Fig. 28. Turn-off Propagation Delay vs. Temperature

400

100

90

80

300

200

70

60

Exp.

50

40

30

20

10

0

Exp.

100

0

-50

-25

0

25

50

75

100 125

-50

-25

0

25

50

75

100 125

Temperature (^oC)

Fig. 29. Turn-on Rise Time vs. Temperature

Fig.30. Turn-off Fall Time vs. Temperature

500

400

300

200

100

0

4

3

2

1

0

Exp.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 31. Input Negative Going Threshold vs. Temperature

Fig. 32. Low Level Output Voltage vs. Temperature

www.irf.com

24

IRS2334SPbF/MPbF

20

15

10

5

4

3

2

1

0

Exp.

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 33. Offset Supply Leakage Current vs. Temperature

Fig. 34. Quiescent VCC Supply Current vs. Temperature

100

80

4

3

2

60

Exp.

40

20

0

Exp.

1

0

-50

-25

0

25

50

75

100 125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 35. Quiescent VCC Supply Current vs. Temperature

Fig. 36. Quiescent VBS Supply Current vs. Temperature

100

80

15

12

Exp.

60

9

Exp.

40

20

0

6

3

0

-50

-25

0

25

50

75

100 125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 37. Quiescent VBS Supply Current vs. Temperature

Fig. 38. VCC Supply Under-voltage Negative Going

Threshold vs. Temperature

www.irf.com

25

IRS2334SPbF/MPbF

15

12

9

15

12

9

Exp.

6

3

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Fig. 39. VCC Supply Under-voltage Positive Going

Threshold vs. Temperature

Fig. 40. VBS Supply Under-voltage Negative Going

Threshold vs. Temperature

15

500

12

400

Exp.

9

300

Exp.

6

3

0

200

100

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100 125

Temperature (^oC)

Fig. 41. VBS Supply Under-voltage Positive Going

Threshold vs. Temperature

Fig. 42. Output High Short Circuit Pulsed Current vs.

Temperature

500

-50

-25

0

25

50

75

100

125

0

-5

400

300

Exp.

-10

-15

-20

200

100

0

-50

-25

0

25

50

75

100 125

Temperature (^oC)

Fig. 44. Max –Vs vs. Temperature

Temperature (^oC)

Fig. 43. Output Low Short Circuit Pulsed Current vs.

Temperature

www.irf.com

26

IRS2334SPbF/MPbF

Package Details

www.irf.com

27

IRS2334SPbF/MPbF

Package Details

28 (32 – 4) lead MLPQ 5x5mm

www.irf.com

28

IRS2334SPbF/MPbF

Tape and Reel Details

LOADED TAPE FEED DIRECTION

A

B

H

D

F

C

NOTE : CONTROLLING

DIMENSION IN MM

E

G

CARRIER TAPE DIMENSION FOR 20SOICW

Metri

Imperial

Ma

Cod

A

B

Mi

11.9

3.9

Ma

12.1

4.1

24.3

11.6

11.0

13.4

n/

Mi

0.46

0.15

0.93

0.44

0.42

0.52

0.05

0.47

0.16

0.95

0.45

0.43

0.52

n/

C

D

E

F

G

H

23.7

11.4

10.8

13.2

1.5

1.6

0.06

F

D

B

C

A

E

G

H

REEL DIMENSIONS FOR 20SOICW

Metri

Imperial

Cod

A

B

C

D

E

F

G

H

Mi

329.6

20.9

12.8

1.9

98.0

n/

26.5

24.4

Ma

330.2

21.4

13.2

2.4

102.0

30.4

29.1

26.4

Mi

Ma

13.00

0.84

0.51

0.09

4.01

1.19

1.14

1.03

12.97

0.82

0.50

0.76

3.85

n/

1.0

0.9

www.irf.com

29

IRS2334SPbF/MPbF

Tape and Reel Details:

28 (32 – 4) lead MLPQ 5x5mm

www.irf.com

30

IRS2334SPbF/MPbF

Part Marking Information

www.irf.com

31

IRS2334SPbF/MPbF

Ordering Information

Standard Pack

Base Part Number

Package Type

Complete Part Number

Form

Quantity

Tube/Bulk

Tape and Reel

Tube/Bulk

XXX

IRS2334 SPBF

IRS2334 STRPBF

IRS2334 MPBF

SOIC20W

XXX

IRS2334

28L MLPQ 5x5mm

(32 leads without 4)

XXX

Tape and Reel

IRS2334 MTRPBF

The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the

consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties

which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International

Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information

previously supplied.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

233 Kansas St., El Segundo, California 90245

Tel: (310) 252-7105

www.irf.com

32

IRS2334SPbF/MPbF

Revision History

Revision Date

Change comments

5.0

24 Jun 2009 Ramanan updated lead assignment, MLPQ 5x5 package information and Absolute Max

Ratings to reflect 25V capability

5.1

30 Jun 2009 Updated: format, lead assignment, functional block diagram,

Added: simplified block diagram, typical application diagram, qualification information,

application details, parameters temperature trend, tape and reel detail, order

information, revision history

Removed: inputs internally clamped at 5.2V in static electrical characteristic

5.2

5.3

3 July 2009

Aug 2009

Lead definition corrected, delay matching waveform definition figure added

Package and tape & reel details for MLPQ 32-4 leads 5x5 added, package thermal

parameters added

5.4

12 Nov

2009

Advanced input filter section added

5.5

5.6

5.7

5.8

5.9

5.10

TBD values in Static Electrical Characteristics updated

Changed MM ESD rating from Class C to Class B

12 Mar 2010 Parameter limits updated: IQCC, IQBS, IIN+

02 Apr 2010 I_o+, I_o-values corrected

26 Jan 2011 Update temperature dependence tables, UVcc hyst corrected

31 Jan 2011 Include the IRS2334MPbF in the datasheet title

9 Dec 2009

www.irf.com

33


型号：	IRS2334STRPBF
厂家：	Infineon
描述：	3 PHASE GATE DRIVER HVIC 3三相栅极驱动的HVIC 栅极栅极驱动
文件：	总33页 (文件大小：725K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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