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IRS23364D [INFINEON]

HIGH VOLTAGE 3 PHASE GATE DRIVER IC; 高压3三相栅极驱动IC
IRS23364D
型号： IRS23364D
厂家： Infineon    Infineon
描述：

HIGH VOLTAGE 3 PHASE GATE DRIVER IC
高压3三相栅极驱动IC

栅极 高压 栅极驱动
文件： 总45页 (文件大小：936K)
中文：  中文翻译
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September 2007  
IRS2336D  
IRS23364D  
HIGH VOLTAGE 3 PHASE GATE DRIVER IC  
Product Summary  
Features  
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Drives up to six IGBT/MOSFET power devices  
Topology  
VOFFSET  
3 Phase  
≤ 600 V  
Gate drive supplies up to 20 V per channel  
Integrated bootstrap functionality  
Over-current protection  
Over-temperature shutdown input  
Advanced input filter  
Integrated deadtime protection  
Shoot-through (cross-conduction) protection  
Undervoltage lockout for VCC & VBS  
Enable/disable input and fault reporting  
Adjustable fault clear timing  
IRS2336D  
10 V – 20 V  
12 V – 20 V  
180 mA & 330 mA  
530 ns & 530 ns  
300 ns  
VOUT  
IRS23364D  
Io+ & I o- (typical)  
tON & tOFF (typical)  
Deadtime (typical)  
Separate logic and power grounds  
3.3 V input logic compatible  
Package Options  
Tolerant to negative transient voltage  
Designed for use with bootstrap power supplies  
Matched propagation delays for all channels  
-40 °C to 125 °C operating range  
RoHS compliant  
Typical Applications  
28-Lead PDIP  
28-Lead SOIC Wide Body  
44-Lead PLCC (without 12 leads)  
•
•
•
•
Appliance motor drives  
Servo drives  
Micro inverter drives  
General purpose three phase inverters  
Typical Connection Diagram  
www.irf.com  
© 2007 International Rectifier  
IRS2336xD Family  
Table of Contents  
Page  
3
Description  
Feature Comparison  
3
Simplified Block Diagram  
Typical Application Diagram  
Qualification Information  
Absolute Maximum Ratings  
Recommended Operating Conditions  
Static Electrical Characteristics  
Dynamic Electrical Characteristics  
Functional Block Diagram  
Input/Output Pin Equivalent Circuit Diagram  
Lead Definitions  
4
4
5
6
7
8
10  
11  
13  
15  
17  
18  
35  
39  
42  
44  
45  
Lead Assignments  
Application Information and Additional Details  
Parameter Temperature Trends  
Package Details  
Tape and Reel Details  
Part Marking Information  
Ordering Information  
www.irf.com  
© 2007 International Rectifier  
2
IRS2336xD Family  
Description  
The IRS2336xD are high voltage, high speed, power MOSFET and IGBT gate drivers with three high-side and  
three low-side referenced output channels for 3-phase applications. This IC is designed to be used with low-cost  
bootstrap power supplies; the bootstrap diode functionality has been integrated into this device to reduce the  
component count and the PCB size. Proprietary HVIC and latch immune CMOS technologies have been  
implemented in a rugged monolithic structure. The floating logic input is compatible with standard CMOS or  
LSTTL outputs (down to 3.3 V logic). A current trip function which terminates all six outputs can be derived from  
an external current sense resistor. Enable functionality is available to terminate all six outputs simultaneously.  
An open-drain FAULT signal is provided to indicate that a fault (e.g., over-current, over-temperature, or  
undervoltage shutdown event) has occurred. Fault conditions are cleared automatically after a delay  
programmed externally via an RC network connected to the RCIN input. The output drivers feature a high-pulse  
current buffer stage designed for minimum driver cross-conduction. Shoot-through protection circuitry and a  
minimum deadtime circuitry have been integrated into this IC. Propagation delays are matched to simplify the  
HVIC’s use in high frequency applications. The floating channels can be used to drive N-channel power  
MOSFETs or IGBTs in the high-side configuration, which operate up to 600 V.  
Feature Comparison: IRS2336xD Family  
Part Number  
IRS2336D  
Input Logic  
HIN/N, LIN/N  
HIN, LIN  
UVLO  
VIT,TH  
0.46 V  
0.46 V  
tON, tOFF  
VOUT  
8.9 V/ 8.2 V  
10.4 V/ 9.4 V  
530 ns, 530 ns  
530 ns, 530 ns  
10 V – 20 V  
12 V – 20 V  
IRS23364D  
www.irf.com  
© 2007 International Rectifier  
3
IRS2336xD Family  
Simplified Block Diagram  
Typical Application Diagram  
www.irf.com  
© 2007 International Rectifier  
4
IRS2336xD Family  
Qualification Information†  
Industrial††  
(per JEDEC JESD 47E)  
Qualification Level  
Comments: This family of ICs has passed JEDEC’s  
Industrial qualification. IR’s Consumer qualification level is  
granted by extension of the higher Industrial level.  
SOIC28W  
PLCC44  
MSL3†††  
(per IPC/JEDEC J-STD-020C)  
Moisture Sensitivity Level  
Not applicable  
(non-surface mount package style)  
Class B  
PDIP28  
Machine Model  
(per JEDEC standard JESD22-A114D)  
Class 2  
ESD  
Human Body Model  
(per EIA/JEDEC standard EIA/JESD22-A115-A)  
Class IV  
(per JEDEC standard JESD22-C101C)  
Class I, Level A  
Charged Device Model  
IC Latch-Up Test  
RoHS Compliant  
(per JESD78A)  
Yes  
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/  
†† Higher qualification ratings may be available should the user have such requirements. Please contact your  
International Rectifier sales representative for further information.  
††† Higher MSL ratings may be available for the specific package types listed here. Please contact your  
International Rectifier sales representative for further information.  
www.irf.com  
© 2007 International Rectifier  
5
IRS2336xD Family  
Absolute Maximum Ratings  
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage  
parameters are absolute voltages referenced to VSS unless otherwise stated in the table. The thermal resistance  
and power dissipation ratings are measured under board mounted and still air conditions. Voltage clamps are  
included between VCC & COM (25 V), VCC & VSS (20 V), and VB & VS (20 V).  
Symbol  
VCC  
Definition  
Min  
-0.3  
Max  
20†  
Units  
Low side supply voltage  
IRS2336D  
IRS23364D  
VSS-0.3  
VSS-0.3  
VSS-0.3  
-0.3  
VSS+5.2  
VCC+0.3  
VCC+0.3  
620†  
VB+0.3  
VB+0.3  
VCC+0.3  
VCC+0.3  
VCC+0.3  
50  
VIN  
Logic input voltage (HIN, LIN, ITRIP, EN)  
VRCIN  
VB  
VS  
VHO  
VLO  
VFLT  
COM  
dVS/dt  
PWHIN  
RCIN input voltage  
High-side floating well supply voltage  
High-side floating well supply return voltage  
Floating gate drive output voltage  
Low-side output voltage  
Fault output voltage  
Power ground  
V
VB-20†  
VS-0.3  
COM-0.3  
VSS-0.3  
VCC-25  
---  
Allowable VS offset supply transient relative to VSS  
High-side input pulse width  
V/ns  
ns  
500  
---  
---  
1.5  
28-Lead PDIP  
PD  
W
ºC/W  
ºC  
Package power dissipation @ TA ≤+25 ºC 28-Lead SOICW  
---  
---  
---  
---  
---  
---  
-55  
---  
1.6  
2.0  
83  
78  
63  
150  
150  
300  
44-Lead PLCC  
28-Lead PDIP  
RΘJA  
Thermal resistance, junction to ambient  
28-Lead SOICW  
44-Lead PLCC  
TJ  
TS  
TL  
Junction temperature  
Storage temperature  
Lead temperature (soldering, 10 seconds)  
†
All supplies are tested at 25 V. An internal 20 V clamp exists for each supply.  
www.irf.com  
© 2007 International Rectifier  
6
IRS2336xD Family  
Recommended Operating Conditions  
For proper operation, the device should be used within the recommended conditions. All voltage parameters are  
absolute voltages referenced to VSS unless otherwise stated in the table. The offset rating is tested with supplies of  
(VCC-COM) = (VB-VS) = 15 V.  
Symbol  
Definition  
Low-side supply voltage  
Min  
10  
12  
Max  
20  
20  
VSS+5  
VCC  
VS+20  
VS+20  
600  
600  
VB  
VCC  
5
VCC  
VCC  
VSS+5  
125  
Units  
IRS2336D  
IRS23364D  
IRS2336D  
IRS23364D  
IRS2336D  
IRS23364D  
VCC  
VIN  
VB  
HIN, LIN, & EN input voltage  
VSS  
VS+10  
VS+12  
COM-8  
-50  
Vs  
COM  
-5  
VSS  
VSS  
VSS  
-40  
High-side floating well supply voltage  
High-side floating well supply offset voltage†  
Transient high-side floating supply voltage††  
Floating gate drive output voltage  
Low-side output voltage  
Power ground  
FAULT output voltage  
RCIN input voltage  
ITRIP input voltage  
Ambient temperature  
VS  
VS(t)  
VHO  
V
VLO  
COM  
VFLT  
VRCIN  
VITRIP  
TA  
ºC  
†
V
V
of –8 V to 600 V. Logic state held for of –8 V to –VBS. Please refer to Design Tip  
S
Logic operation for  
DT97-3 for more details.  
S
†† Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to  
the Application Information section of this datasheet for more details.  
www.irf.com  
© 2007 International Rectifier  
7
IRS2336xD Family  
Static Electrical Characteristics  
o
(VCC-COM) = (VB-VS) = 15 V. TA = 25 C unless otherwise specified. The VIN and IIN parameters are referenced to  
VSS and are applicable to all six channels. The VO and IO parameters are referenced to respective VS and COM and  
are applicable to the respective output leads HO or LO. The  
parameters are referenced to VSS. The  
VCCUV  
VBSUV  
parameters are referenced to VS.  
Symbol  
Definition  
VCC supply undervoltage positive  
going threshold  
Min  
8
Typ Max  
Units Test Conditions  
IRS2336D  
IRS23364D  
8.9  
9.8  
11.6  
9
VCCUV  
+
10.4 11.1  
7.4 8.2  
10.2 10.9  
0.3  
---  
8
10.4 11.1  
7.4 8.2  
10.2 10.9  
0.3  
---  
---  
---  
---  
---  
---  
VCC supply undervoltage negative IRS2336D  
VCCUV  
-
going threshold  
VCC supply undervoltage  
hysteresis  
VBS supply undervoltage positive  
going threshold  
IRS23364D  
IRS2336D  
IRS23364D  
IRS2336D  
IRS23364D  
11.4  
---  
---  
9.8  
11.6  
9
0.7  
0.2  
8.9  
VCCUVHY  
VBSUV+  
VBSUV-  
V
NA  
VBS supply undervoltage negative IRS2336D  
going threshold  
VBS supply undervoltage  
hysteresis  
High-side floating well offset supply leakage  
Quiescent VBS supply current  
Quiescent VCC supply current  
High level output voltage drop, VBIAS-VO  
Low level output voltage drop, VO  
IRS23364D  
IRS2336D  
IRS23364D  
11.4  
---  
---  
0.7  
0.2  
---  
VBSUVHY  
ILK  
50  
VB = VS = 600 V  
µA  
IQBS  
IQCC  
VOH  
VOL  
50  
120  
4
1.4  
0.6  
All inputs are in the  
off state  
2.5  
0.75  
0.15  
mA  
V
V
Io= 20 mA  
VO=0 V,VIN=0 V,  
PW ≤ 10 µs  
VO=15 V,VIN=5 V,  
PW ≤ 10 µs  
Io+  
Io-  
Output high short circuit pulsed current  
Output low short circuit pulsed current  
120  
250  
2.5  
---  
180  
330  
1.9  
1
---  
---  
mA  
Logic “0” input voltage  
Logic “1” input voltage  
Logic “1” input voltage  
Logic “0” input voltage  
Input voltage clamp  
IRS2336D  
VIH  
---  
IRS23364D  
IRS2336D  
IRS23364D  
NA  
V
VIL  
VIN,CLAMP  
IHIN+  
0.8  
5.65  
IRS2336D  
4.8  
5.2  
IIN = 100 µA  
VIN = 0 V  
(HIN, LIN, ITRIP and EN)  
IRS2336D  
IRS23364D  
IRS2336D  
IRS23364D  
IRS2336D  
IRS23364D  
IRS2336D  
IRS23364D  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
150  
120  
110  
---  
150  
120  
110  
---  
8
3
---  
35  
200  
165  
150  
1
200  
165  
150  
1
---  
---  
1
100  
Input bias current (HO = High)  
Input bias current (HO = Low)  
Input bias current (LO = High)  
Input bias current (LO = Low)  
VIN = 4 V  
IHIN-  
µA  
V
VIN = 0 V  
ILIN+  
VIN = 4 V  
VIN = 0 V  
NA  
ILIN-  
VRCIN,TH RCIN positive going threshold  
VRCIN,HY RCIN hysteresis  
IRCIN  
RCIN input bias current  
µA  
Ω
VRCIN = 0 V or 15 V  
I = 1.5 mA  
RON,RCIN RCIN low on resistance  
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© 2007 International Rectifier  
8
IRS2336xD Family  
Static Electrical Characteristics (continued)  
Symbol  
VIT,TH+ ITRIP positive going threshold  
VIT,TH- ITRIP negative going threshold  
VIT,HYS ITRIP hysteresis  
IITRIP+ “High” ITRIP input bias current  
IITRIP- “Low” ITRIP input bias current  
Definition  
Min  
0.37 0.46  
Typ Max  
Units Test Conditions  
0.55  
---  
---  
40  
1
V
NA  
---  
---  
---  
---  
---  
0.8  
---  
---  
---  
---  
---  
---  
0.4  
0.06  
5
VIN = 4 V  
VIN = 0 V  
µA  
V
---  
VEN,TH+ Enable positive going threshold  
VEN,TH- Enable negative going threshold  
---  
---  
2.5  
---  
NA  
IRS2336D  
IRS23364D  
IRS2336D  
IRS23364D  
5
120  
---  
40  
165  
1
IEN+  
IEN-  
“High” enable input bias current  
“Low” enable input bias current  
VIN = 4 V  
VIN = 0 V  
µA  
---  
1
RON,FLT FAULT low on resistance  
RBS Internal BS diode Ron  
45  
160  
100  
---  
I = 1.5 mA  
NA  
Ω
www.irf.com  
© 2007 International Rectifier  
9
IRS2336xD Family  
Dynamic Electrical Characteristics  
VCC= VB = 15 V, VS = VSS = COM, TA = 25 oC, and CL = 1000 pF unless otherwise specified.  
Symbol  
Definition  
Turn-on propagation delay  
Turn-off propagation delay  
Turn-on rise time  
Min  
400  
400  
---  
Typ  
530  
530  
110  
35  
Max Units  
Test Conditions  
tON  
tOFF  
tR  
750  
750  
190  
75  
VIN = 0 V & 5 V  
tF  
Turn-off fall time  
---  
Input filter time†  
ns  
tFIL,IN  
tEN  
200  
350  
510  
(HIN, LIN, ITRIP & EN)  
Enable low to output shutdown  
propagation delay  
350  
100  
1.3  
440  
200  
1.65  
650  
---  
V
IN, VEN = 0 V or 5 V  
tFILTER,EN Enable input filter time  
NA  
FAULT clear time  
RCIN: R = 2 MΩ, C = 1 nF  
ITRIP to output shutdown  
propagation delay  
VIN = 0 V or 5 V  
VITRIP = 0 V  
tFLTCLR  
2
ms  
ns  
tITRIP  
500  
750  
1200  
VITRIP =5 V  
tBL  
tFLT  
DT  
ITRIP blanking time  
ITRIP to FAULT propagation delay  
Deadtime  
---  
400  
190  
---  
400  
575  
300  
---  
---  
950  
420  
60  
VIN = 0 V or 5 V  
VITRIP = 5 V  
VIN = 0 V & 5 V without  
external deadtime  
DT matching††  
MDT  
††  
VIN = 0 V & 5 V with external  
deadtime larger than DT  
MT  
PM  
---  
---  
---  
---  
50  
75  
Delay matching time (tON, tOFF  
Pulse width distortion†††  
)
PW input=10 µs  
†
The minimum width of the input pulse is recommended to exceed 500 ns to ensure the filtering time of the  
input filter is exceeded.  
†† This parameter applies to all of the channels. Please see the application section for more details.  
††† PM is defined as PWIN - PWOUT  
.
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© 2007 International Rectifier  
10  
IRS2336xD Family  
Functional Block Diagram: IRS2336D  
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© 2007 International Rectifier  
11  
IRS2336xD Family  
Functional Block Diagram: IRS23364D  
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© 2007 International Rectifier  
12  
IRS2336xD Family  
Input/Output Pin Equivalent Circuit Diagrams: IRS2336D  
VCC  
ESD  
Diode  
ITRIP  
or EN  
ESD  
RPD  
Diode  
VSS  
www.irf.com  
© 2007 International Rectifier  
13  
IRS2336xD Family  
Input/Output Pin Equivalent Circuit Diagrams: IRS23364D  
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© 2007 International Rectifier  
14  
IRS2336xD Family  
Lead Definitions: IRS2336D  
Symbol  
Description  
VCC  
VSS  
Low-side supply voltage  
Logic ground  
VB1  
High-side gate drive floating supply (phase 1)  
High-side gate drive floating supply (phase 2)  
High-side gate drive floating supply (phase 3)  
High voltage floating supply return (phase 1)  
High voltage floating supply return (phase 2)  
High voltage floating supply return (phase 3)  
VB2  
VB3  
VS1  
VS2  
VS3  
HIN1/N  
HIN2/N  
HIN3/N  
LIN1/N  
LIN2/N  
LIN3/N  
HO1  
Logic inputs for high-side gate driver outputs (phase 1); input is out-of-phase with output  
Logic inputs for high-side gate driver outputs (phase 2); input is out-of-phase with output  
Logic inputs for high-side gate driver outputs (phase 3); input is out-of-phase with output  
Logic inputs for low-side gate driver outputs (phase 1); input is out-of-phase with output  
Logic inputs for low-side gate driver outputs (phase 2); input is out-of-phase with output  
Logic inputs for low-side gate driver outputs (phase 3); input is out-of-phase with output  
High-side driver outputs (phase 1)  
HO2  
High-side driver outputs (phase 2)  
HO3  
High-side driver outputs (phase 3)  
LO1  
Low-side driver outputs (phase 1)  
LO2  
Low-side driver outputs (phase 2)  
LO3  
Low-side driver outputs (phase 3)  
COM  
Low-side gate drive return  
Indicates over-current, over-temperature (ITRIP), or low-side undervoltage lockout has occurred.  
This pin has negative logic and an open-drain output. The use of over-current and over-  
temperature protection requires the use of external components.  
Logic input to shutdown functionality. Logic functions when EN is high (i.e., positive logic). No  
effect on FAULT and not latched.  
FAULT/N  
EN  
Analog input for over-current shutdown. When active, ITRIP shuts down outputs and activates  
FAULT and RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally  
set time tFLTCLR, then automatically becomes inactive (open-drain high impedance).  
An external RC network input used to define the FAULT CLEAR delay (tFLTCLR) approximately  
equal to R*C. When RCIN > 8 V, the FAULT pin goes back into an open-drain high-impedance  
state.  
ITRIP  
RCIN  
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© 2007 International Rectifier  
15  
IRS2336xD Family  
Lead Definitions: IRS23364D  
Symbol  
Description  
VCC  
VSS  
VB1  
VB2  
VB3  
VS1  
VS2  
VS3  
HIN1  
HIN2  
HIN3  
LIN1  
LIN2  
LIN3  
HO1  
HO2  
HO3  
LO1  
LO2  
LO3  
COM  
Low-side supply voltage  
Logic ground  
High-side gate drive floating supply (phase 1)  
High-side gate drive floating supply (phase 2)  
High-side gate drive floating supply (phase 3)  
High voltage floating supply return (phase 1)  
High voltage floating supply return (phase 2)  
High voltage floating supply return (phase 3)  
Logic inputs for high-side gate driver outputs (phase 1); input is in-phase with output  
Logic inputs for high-side gate driver outputs (phase 2); input is in-phase with output  
Logic inputs for high-side gate driver outputs (phase 3); input is in-phase with output  
Logic inputs for low-side gate driver outputs (phase 1); input is in-phase with output  
Logic inputs for low-side gate driver outputs (phase 2); input is in-phase with output  
Logic inputs for low-side gate driver outputs (phase 3); input is in-phase with output  
High-side driver outputs (phase 1)  
High-side driver outputs (phase 2)  
High-side driver outputs (phase 3)  
Low-side driver outputs (phase 1)  
Low-side driver outputs (phase 2)  
Low-side driver outputs (phase 3)  
Low-side gate drive return  
Indicates over-current, over-temperature (ITRIP), or low-side undervoltage lockout has occurred.  
This pin has negative logic and an open-drain output. The use of over-current and over-  
temperature protection requires the use of external components.  
Logic input to shutdown functionality. Logic functions when EN is high (i.e., positive logic). No  
effect on FAULT and not latched.  
FAULT/N  
EN  
Analog input for over-current shutdown. When active, ITRIP shuts down outputs and activates  
FAULT and RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally  
set time tFLTCLR, then automatically becomes inactive (open-drain high impedance).  
An external RC network input used to define the FAULT CLEAR delay (tFLTCLR) approximately  
equal to R*C. When RCIN > 8 V, the FAULT pin goes back into an open-drain high-impedance  
state.  
ITRIP  
RCIN  
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© 2007 International Rectifier  
16  
IRS2336xD Family  
Lead Assignments  
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© 2007 International Rectifier  
17  
IRS2336xD Family  
Application Information and Additional Details  
Information regarding the following topics are included as subsections within this section of the datasheet.  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IGBT/MOSFET Gate Drive  
Switching and Timing Relationships  
Deadtime  
Matched Propagation Delays  
Input Logic Compatibility  
Undervoltage Lockout Protection  
Shoot-Through Protection  
Enable Input  
Fault Reporting and Programmable Fault Clear Timer  
Over-Current Protection  
Over-Temperature Shutdown Protection  
Truth Table: Undervoltage lockout, ITRIP, and ENABLE  
Advanced Input Filter  
Short-Pulse / Noise Rejection  
Integrated Bootstrap Functionality  
Bootstrap Power Supply Design  
Separate Logic and Power Grounds  
Tolerant to Negative VS Transients  
PCB Layout Tips  
Additional Documentation  
IGBT/MOSFET Gate Drive  
The IRS2336xD HVICs are designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate  
several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to  
drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is  
defined as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is sometimes  
generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage.  
VB  
VB  
(or VCC  
)
(or VCC)  
IO+  
HO  
HO  
(or LO)  
(or LO)  
+
IO-  
VHO (or VLO)  
-
VS  
VS  
(or COM)  
(or COM)  
Figure 1: HVIC sourcing current  
Figure 2: HVIC sinking current  
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IRS2336xD Family  
Switching and Timing Relationships  
The relationship between the input and output signals of the IRS2336D and IRS23364D are illustrated below in  
Figures 3 and 4. From these figures, we can see the definitions of several timing parameters (i.e., PWIN, PWOUT, tON,  
tOFF, tR, and tF) associated with this device.  
Figure 3: Switching time waveforms (IRS2336D)  
Figure 4: Switching time waveforms (IRS23364D)  
The following two figures illustrate the timing relationships of some of the functionality of the IRS2336xD; this  
functionality is described in further detail later in this document.  
During interval A of Figure 5, the HVIC has received the command to turn-on both the high- and low-side switches at  
the same time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high-  
and low-side output are held in the off state.  
Interval B of Figures 5 and 6 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a  
result, all of the gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also  
held low), the voltage on the RCIN pin has been pulled to 0 V, and a fault is reported by the FAULT output  
transitioning to the low state. Once the ITRIP input has returned to the low state, the output will remain disabled and  
the fault condition reported until the voltage on the RCIN pin charges up to VRCIN,TH (see interval C in Figure 6); the  
charging characteristics are dictated by the RC network attached to the RCIN pin.  
During intervals D and E of Figure 5, we can see that the enable (EN) pin has been pulled low (as is the case when  
the driver IC has received a command from the control IC to shutdown); this results in the outputs (HOx and LOx)  
being held in the low state until the enable pin is pulled high.  
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IRS2336xD Family  
Figure 5: Input/output timing diagram for the IRS2336xD family  
Figure 6: Detailed view of B & C intervals  
Deadtime  
This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs  
within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts  
a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to  
ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This  
minimum deadtime is automatically inserted whenever the external deadtime is shorter than DT; external deadtimes  
larger than DT are not modified by the gate driver. Figure 7 illustrates the deadtime period and the relationship  
between the output gate signals.  
The deadtime circuitry of the IRS2336xD is matched with respect to the high- and low-side outputs of a given  
channel; additionally, the deadtimes of each of the three channels are matched. Figure 7 defines the two deadtime  
parameters (i.e., DT1 and DT2) of a specific channel; the deadtime matching parameter (MDT) associated with the  
IRS2336xD specifies the maximum difference between DT1 and DT2. The MDT parameter also applies when  
comparing the DT of one channel of the IRS2336xD to that of another.  
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IRS2336xD Family  
LINx  
HINx  
50%  
50%  
LOx  
HOx  
DT  
DT  
50%  
50%  
Figure 7: Illustration of deadtime  
Matched Propagation Delays  
The IRS2336xD family of HVICs is designed with propagation delay matching circuitry. With this feature, the IC’s  
response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both  
the low-side channels and the high-side channels; the maximum difference is specified by the delay matching  
parameter (MT). Additionally, the propagation delay for each low-side channel is matched when compared to the  
other low-side channels and the propagation delays of the high-side channels are matched with each other; the MT  
specification applies as well. The propagation turn-on delay (tON) of the IRS2336xD is matched to the propagation  
turn-on delay (tOFF).  
Input Logic Compatibility  
The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS2336xD family has been  
designed to be compatible with 3.3 V and 5 V logic-level signals. The IRS2336D features an integrated 5.2 V Zener  
clamp on the HIN, LIN, ITRIP, and EN pins; the IRS23364D does not offer this input clamp. Figure 8 illustrates an  
input signal to the IRS2336D and IRS23364D, its input threshold values, and the logic state of the IC as a result of  
the input signal.  
Figure 8: HIN & LIN input thresholds  
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IRS2336xD Family  
Undervoltage Lockout Protection  
This family of ICs provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power  
supply and the VBS (high-side circuitry) power supply. Figure 9 is used to illustrate this concept; VCC (or VBS) is  
plotted over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection  
is enabled or disabled.  
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the  
VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize  
a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low  
state to inform the controller of the fault condition.  
Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the  
VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a  
fault condition, and shutdown the high-side gate drive outputs of the IC.  
The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is  
sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be  
driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this  
could result in very high conduction losses within the power device and could lead to power device failure.  
Figure 9: UVLO protection  
Shoot-Through Protection  
The IRS2336xD family of high-voltage ICs is equipped with shoot-through protection circuitry (also known as cross-  
conduction prevention circuitry). Figure 10 shows how this protection circuitry prevents both the high- and low-side  
switches from conducting at the same time. Table 1 illustrates the input/output relationship of the devices in the form  
of a truth table. Note that the IRS2336D has inverting inputs (the output is out-of-phase with its respective input)  
while the IRS23364D has non-inverting inputs (the output is in-phase with its respective input).  
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IRS2336xD Family  
Shoot-through  
protection enabled  
HIN  
LIN  
HO  
LO  
Figure 10: Illustration of shoot-through protection circuitry  
IRS2336D  
IRS23364D  
HIN  
0
LIN  
0
HO  
0
LO  
0
HIN  
0
LIN  
0
HO  
0
LO  
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
0
0
Table 1: Input/output truth table for IRS2336D and IRS23364D  
Enable Input  
The IRS2336xD family of HVICs is equipped with an enable input pin that is used to shutdown or enable the HVIC.  
When the EN pin is in the high state the HVIC is able to operate normally (assuming no other fault conditions).  
When a condition occurs that should shutdown the HVIC, the EN pin should see a low logic state. The enable  
circuitry of the IRS2336xD features an input filter; the minimum input duration is specified by tFILTER,EN. Please refer  
to the EN pin parameters VEN,TH+, VEN,TH-, and IEN for the details of its use. Table 2 gives a summary of this pin’s  
functionality and Figure 11 illustrates the outputs’ response to a shutdown command.  
Enable Input  
Enable input high  
Enable input low  
Outputs enabled*  
Outputs disabled  
Table 2: Enable functionality truth table  
Figure 11: Output enable timing waveform  
(*assumes no other fault condition)  
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IRS2336xD Family  
Fault Reporting and Programmable Fault Clear Timer  
The IRS2336xD family provides an integrated fault reporting output and an adjustable fault clear timer. There are  
two situations that would cause the HVIC to report a fault via the FAULT pin. The first is an undervoltage condition  
of VCC and the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the FAULT pin is  
internally pulled to VSS and the fault clear timer is activated. The fault output stays in the low state until the fault  
condition has been removed and the fault clear timer expires; once the fault clear timer expires, the voltage on the  
FAULT pin will return to VCC.  
The length of the fault clear time period (tFLTCLR) is determined by exponential charging characteristics of the  
capacitor where the time constant is set by RRCIN and CRCIN. In Figure 12 where we see that a fault condition has  
occurred (UVLO or ITRIP), RCIN and FAULT are pulled to VSS, and once the fault has been removed, the fault clear  
timer begins. Figure 13 shows that RRCIN is connected between the VCC and the RCIN pin, while CRCIN is placed  
between the RCIN and VSS pins.  
Figure 12: RCIN and FAULT pin waveforms  
Figure 13: Programming the fault clear timer  
The design guidelines for this network are shown in Table 3.  
≤1 nF  
Ceramic  
CRCIN  
0.5 MΩ to 2 MΩ  
>> RON,RCIN  
RRCIN  
Table 3: Design guidelines  
The length of the fault clear time period can be determined by using the formula below.  
vC(t) = Vf(1-e-t/RC  
)
tFLTCLR = -(RRCINCRCIN)ln(1-VRCIN,TH/VCC)  
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IRS2336xD Family  
Over-Current Protection  
The IRS2336xD HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current  
events in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are  
shutdown, a fault is reported through the FAULT pin, and RCIN is pulled to VSS.  
The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R0, R1,  
and R2) connected to ITRIP as shown in Figure 14, and the ITRIP threshold (VIT,TH+). The circuit designer will need  
to determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the voltage  
at node VX reaches the over-current threshold (VIT,TH+) at that current level.  
VIT,TH+ = R0IDC-(R1/(R1+R2))  
Figure 14: Programming the over-current protection  
For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to  
exceed 5 V; if necessary, an external voltage clamp may be used.  
Over-Temperature Shutdown Protection  
The ITRIP input of the IRS2336xD can also be used to detect over-temperature events in the system and initiate a  
shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will  
need to design the resistor network as shown in Figure 15 and select the maximum allowable temperature.  
This network consists of a thermistor and two standard resistors R3 and R4. As the temperature changes, the  
resistance of the thermistor will change; this will result in a change of voltage at node VX. The resistor values should  
be selected such the voltage VX should reach the threshold voltage (VIT,TH+) of the ITRIP functionality by the time that  
the maximum allowable temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V.  
When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes  
(e.g., DL4148) can be used. This network is shown in Figure 16; the OR-ing diodes have been labeled D1 and D2.  
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IRS2336xD Family  
Figure 15: Programming over-temperature  
protection  
Figure 16: Using over-current protection and over-  
temperature protection  
Truth Table: Undervoltage lockout, ITRIP, and ENABLE  
Table 4 provides the truth table for the IRS2336xD. The first line shows that the UVLO for VCC has been tripped; the  
FAULT output has gone low and the gate drive outputs have been disabled. is not latched in this case and  
VCCUV  
, the FAULT output returns to the high impedance state.  
when VCC is greater than  
VCCUV  
The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have been  
disabled. After VBS exceeds the , HO will stay low until the HVIC input receives a new falling  
VBSUV threshold  
(IRS2336D) or rising (IRS23364D) transition of HIN. The third case shows the normal operation of the HVIC. The  
fourth case illustrates that the ITRIP trip threshold has been reached and that the gate drive outputs have been  
disabled and a fault has been reported through the fault pin. In the last case, the HVIC has received a command  
through the EN input to shutdown; as a result, the gate drive outputs have been disabled.  
VCC  
VBS  
---  
ITRIP  
---  
0 V  
0 V  
>VITRIP  
0 V  
EN  
---  
5 V  
5 V  
5 V  
0 V  
RCIN  
High  
High  
High  
Low  
FAULT  
0
High impedance  
High impedance  
0
LO  
0
LIN  
LIN  
0
HO  
0
0
HIN  
0
0
<
UVLO VCC  
UVLO VBS  
Normal operation  
ITRIP fault  
VCCUV  
15 V  
15 V  
15 V  
15 V  
<
VBSUV  
15 V  
15 V  
15 V  
High  
High impedance  
0
EN command  
Table 4: IRS2336xD UVLO, ITRIP, EN, RCIN, & FAULT truth table  
Advanced Input Filter  
The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject  
noise spikes and short pulses. This input filter has been applied to the HIN, LIN, and EN inputs. The working  
principle of the new filter is shown in Figures 17 and 18.  
Figure 17 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms  
(Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the  
difference between the input signal and tFIL,IN. The lower pair of waveforms (Example 2) show an input signal with a  
duration slightly longer then tFIL,IN; the resulting output is approximately the difference between the input signal and  
tFIL,IN  
.
Figure 18 shows the advanced input filter and the symmetry between the input and output. The upper pair of  
waveforms (Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting output is  
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IRS2336xD Family  
approximately the same duration as the input signal. The lower pair of waveforms (Example 2) show an input signal  
with a duration slightly longer then tFIL,IN; the resulting output is approximately the same duration as the input signal.  
Figure 17: Typical input filter  
Figure 18: Advanced input filter  
Short-Pulse / Noise Rejection  
This device’s input filter provides protection against short-pulses (e.g., noise) on the input lines. If the duration of the  
input signal is less than tFIL,IN, the output will not change states. Example 1 of Figure 19 shows the input and output  
in the low state with positive noise spikes of durations less than tFIL,IN; the output does not change states. Example 2  
of Figure 19 shows the input and output in the high state with negative noise spikes of durations less than tFIL,IN; the  
output does not change states.  
Figure 19: Noise rejecting input filters  
Figures 20 and 21 present lab data that illustrates the characteristics of the input filters while receiving ON and OFF  
pulses.  
The input filter characteristic is shown in Figure 20; the left side illustrates the narrow pulse ON (short positive pulse)  
characteristic while the left shows the narrow pulse OFF (short negative pulse) characteristic. The x-axis of Figure  
20 shows the duration of PWIN, while the y-axis shows the resulting PWOUT duration. It can be seen that for a PWIN  
duration less than tFIL,IN, that the resulting PWOUT duration is zero (e.g., the filter rejects the input signal/noise). We  
also see that once the PWIN duration exceed tFIL,IN, that the PWOUT durations mimic the PWIN durations very well over  
this interval with the symmetry improving as the duration increases. To ensure proper operation of the HVIC, it is  
suggested that the input pulse width for the high-side inputs be ≥ 500 ns.  
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IRS2336xD Family  
The difference between the PWOUT and PWIN signals of both the narrow ON and narrow OFF cases is shown in  
Figure 21; the careful reader will note the scale of the y-axis. The x-axis of Figure 21 shows the duration of PWIN,  
while the y-axis shows the resulting PWOUT–PWIN duration. This data illustrates the performance and near symmetry  
of this input filter.  
Narrow Pulse OFF  
1000  
PWOUT  
PWIN  
800  
600  
400  
200  
0
0
200  
400  
Time (ns)  
600  
800  
1000  
Figure 20: IRS2336xD input filter characteristic  
Figure 21: Difference between the input pulse and the output pulse  
Integrated Bootstrap Functionality  
The new IRS2336xD family features integrated high-voltage bootstrap MOSFETs that eliminate the need of the  
external bootstrap diodes and resistors in many applications.  
There is one bootstrap MOSFET for each high-side output channel and it is connected between the VCC supply and  
its respective floating supply (i.e., VB1, VB2, VB3); see Figure 22 for an illustration of this internal connection.  
The integrated bootstrap MOSFET is turned on only during the time when LO is ‘high’, and it has a limited source  
current due to RBS. The VBS voltage will be charged each cycle depending on the on-time of LO and the value of the  
CBS capacitor, the drain-source (collector-emitter) drop of the external IGBT (or MOSFET), and the low-side free-  
wheeling diode drop.  
The bootstrap MOSFET of each channel follows the state of the respective low-side output stage (i.e., the bootstrap  
MOSFET is ON when LO is high, it is OFF when LO is low), unless the VB voltage is higher than approximately  
110% of VCC. In that case, the bootstrap MOSFET is designed to remain off until VB returns below that threshold; this  
concept is illustrated in Figure 23.  
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IRS2336xD Family  
Figure 22: Internal bootstrap MOSFET connection  
Figure 23: Bootstrap MOSFET state diagram  
A bootstrap MOSFET is suitable for most of the PWM modulation schemes and can be used either in parallel with  
the external bootstrap network (i.e., diode and resistor) or as a replacement of it. The use of the integrated bootstrap  
as a replacement of the external bootstrap network may have some limitations. An example of this limitation may  
arise when this functionality is used in non-complementary PWM schemes (typically 6-step modulations) and at very  
high PWM duty cycle. In these cases, superior performances can be achieved by using an external bootstrap diode  
in parallel with the internal bootstrap network.  
Bootstrap Power Supply Design  
For information related to the design of the bootstrap power supply while using the integrated bootstrap functionality  
of the IRS2336xD family, please refer to Application Note 1123 (AN-1123) entitled “Bootstrap Network Analysis:  
Focusing on the Integrated Bootstrap Functionality.” This application note is available at www.irf.com.  
For information related to the design of a standard bootstrap power supply (i.e., using an external discrete diode)  
please refer to Design Tip 04-4 (DT04-4) entitled “Using Monolithic High Voltage Gate Drivers.” This design tip is  
available at www.irf.com.  
Separate Logic and Power Grounds  
The IRS2336xD has separate logic and power ground pin (VSS and COM respectively) to eliminate some of the noise  
problems that can occur in power conversion applications. Current sensing shunts are commonly used in many  
applications for power inverter protection (i.e., over-current protection), and in the case of motor drive applications,  
for motor current measurements. In these situations, it is often beneficial to separate the logic and power grounds.  
Figure 24 shows a HVIC with separate VSS and COM pins and how these two grounds are used in the system. The  
VSS is used as the reference point for the logic and over-current circuitry; VX in the figure is the voltage between the  
ITRIP pin and the VSS pin. Alternatively, the COM pin is the reference point for the low-side gate drive circuitry. The  
output voltage used to drive the low-side gate is VLO-COM; the gate-emitter voltage (VGE) of the low-side switch is the  
output voltage of the driver minus the drop across RG,LO  
.
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IRS2336xD Family  
DC+ BUS  
DBS  
VB  
(x3)  
VCC  
CBS  
HO  
RG,HO  
(x3)  
VS  
(x3)  
VS1  
VS2  
VS3  
LO  
(x3)  
RG,LO  
ITRIP  
+
+
+
VGE1  
VGE2  
VGE3  
-
-
-
VSS  
COM  
R2  
R0  
+
R1  
VX  
-
DC- BUS  
Figure 24: Separate VSS and COM pins  
Tolerant to Negative VS Transients  
A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage  
as the power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is  
shown in Figure 25; here we define the power switches and diodes of the inverter.  
If the high-side switch (e.g., the IGBT Q1 in Figures 26 and 27) switches off, while the U phase current is flowing to  
an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-  
side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus  
voltage to the negative DC bus voltage.  
Figure 25: Three phase inverter  
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IRS2336xD Family  
DC+ BUS  
Q1  
ON  
IU  
VS1  
D2  
Q2  
OFF  
DC- BUS  
Figure 26: Q1 conducting  
Figure 27: D2 conducting  
Also when the V phase current flows from the inductive load back to the inverter (see Figures 28 and 29), and Q4  
IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2,  
swings from the positive DC bus voltage to the negative DC bus voltage.  
DC+ BUS  
D3  
Q3  
OFF  
IV  
VS2  
D4  
Q4  
OFF  
DC- BUS  
Figure 28: D3 conducting  
Figure 29: Q4 conducting  
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it  
swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”.  
The circuit shown in Figure 30 depicts one leg of the three phase inverter; Figures 31 and 32 show a simplified  
illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from  
the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch is on,  
VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of  
the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side  
freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures). This current  
flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between  
VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS pin).  
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IRS2336xD Family  
Figure 30: Parasitic Elements  
Figure 31: VS positive  
Figure 32: VS negative  
In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient  
voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is  
greater than in normal operation.  
International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding  
applications. The IRS2336xD has been seen to withstand large negative VS transient conditions on the order of -50  
V for a period of 50 ns. An illustration of the IRS2336D’s performance can be seen in Figure 33. This experiment  
was conducted using various loads to create this condition; the curve shown in this figure illustrates the successful  
operation of the IRS2336D under these stressful conditions. In case of -VS transients greater then -20 V for a period  
of time greater than 100 ns; the HVIC is designed to hold the high-side outputs in the off state for 4.5 µs in order to  
ensure that the high- and low-side power switches are not on at the same time.  
Figure 33: Negative VS transient results for an International Rectifier HVIC  
Even though the IRS2336xD has been shown able to handle these large negative VS transient conditions, it is highly  
recommended that the circuit designer always limit the negative VS transients as much as possible by careful PCB  
layout and component use.  
PCB Layout Tips  
Distance between high and low voltage components: It’s strongly recommended to place the components tied to the  
floating voltage pins (VB and VS) near the respective high voltage portions of the device. The IRS2336xD in the  
PLCC44 package has had some unused pins removed in order to maximize the distance between the high voltage  
and low voltage pins. Please see the Case Outline PLCC44 information in this datasheet for the details.  
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IRS2336xD Family  
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high  
voltage floating side.  
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure  
34). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops  
must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT  
collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a  
voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.  
Figure 34: Antenna Loops  
Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and VSS pins. This  
connection is shown in Figure 35. A ceramic 1 µF ceramic capacitor is suitable for most applications. This  
component should be placed as close as possible to the pins in order to reduce parasitic elements.  
Figure 35: Supply capacitor  
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IRS2336xD Family  
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at  
the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions,  
it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side  
emitter to negative bus rail stray inductance. However, where negative VS spikes remain excessive, further steps  
may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin and the switch  
node (see Figure 36), and in some cases using a clamping diode between VSS and VS (see Figure 37). See DT04-4  
at www.irf.com for more detailed information.  
Figure 36: VS resistor  
Figure 37: VS clamping diode  
Additional Documentation  
Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search  
function and the document number to quickly locate them. Below is a short list of some of these documents.  
DT97-3: Managing Transients in Control IC Driven Power Stages  
AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality  
DT04-4: Using Monolithic High Voltage Gate Drivers  
AN-978: HV Floating MOS-Gate Driver ICs  
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© 2007 International Rectifier  
34  
IRS2336xD Family  
Parameter Temperature Trends  
Figures 38-58 provide information on the experimental performance of the IRS2336xD HVIC. The line plotted in  
each figure is generated from actual lab data. A small number of individual samples were tested at three  
temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled  
Exp. consist of three data points (one data point at each of the tested temperatures) that have been connected  
together to illustrate the understood temperature trend. The individual data points on the curve were determined  
by calculating the averaged experimental value of the parameter (for a given temperature).  
1000  
800  
600  
400  
200  
0
1000  
800  
600  
400  
200  
0
Exp.  
Exp.  
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (oC)  
Temperature (oC)  
Figure 38: tON vs. temperature  
Figure 39: tOFF vs. temperature  
600  
450  
300  
150  
0
1500  
1200  
900  
600  
300  
0
Exp.  
Exp.  
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (oC)  
Temperature (oC)  
Figure 40: DT vs. temperature  
Figure 41: tITRIP vs. temperature  
www.irf.com  
© 2007 International Rectifier  
35  
IRS2336xD Family  
1200  
1000  
800  
600  
400  
200  
0
1000  
800  
600  
400  
200  
0
Exp.  
Exp.  
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
125  
125  
Temperature (oC)  
Temperature (oC)  
Figure 42: tFLT vs. temperature  
Figure 43: tEN vs. temperature  
60  
40  
20  
0
60  
40  
20  
0
Exp.  
Exp.  
-50  
-25  
0
25  
50  
75  
100  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (oC)  
Temperature (oC)  
Figure 44: MT vs. temperature  
Figure 45: MDT vs. temperature  
60  
40  
20  
0
16  
12  
8
Exp.  
Exp.  
4
0
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
Temperature (oC)  
Temperature (oC)  
Figure 46: PM vs. temperature  
Figure 47: IITRIP+ vs. temperature  
www.irf.com  
© 2007 International Rectifier  
36  
IRS2336xD Family  
5
4
3
2
1
0
120  
100  
80  
60  
40  
20  
0
Exp.  
Exp.  
-50  
-25  
0
25  
50  
75  
100  
125  
125  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (oC)  
Temperature (oC)  
Figure 48: IQCC vs. temperature  
Figure 49: IQBS vs. temperature  
0.60  
0.40  
0.20  
0.00  
0.60  
Exp.  
0.40  
0.20  
0.00  
Exp.  
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
Temperature (oC)  
Temperature (oC)  
Figure 08: IO+ vs. temperature  
Figure 51: IO- vs. temperature  
12  
10  
8
12  
10  
8
Exp.  
Exp.  
6
6
4
4
2
2
0
0
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
Temperature (oC)  
Temperature (oC)  
Figure 52: VCCUV+ vs. temperature  
Figure 53: VCCUV- vs. temperature  
www.irf.com  
© 2007 International Rectifier  
37  
IRS2336xD Family  
10  
9
10  
9
Exp.  
Exp.  
8
8
7
7
6
6
5
5
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (oC)  
Temperature (oC)  
Figure 54: VBSUV+ vs. temperature  
Figure 55: VBSUV- vs. temperature  
800  
600  
400  
200  
800  
600  
400  
200  
0
Exp.  
EXP.  
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (oC)  
Temperature (oC)  
Figure 56: VIT,TH+ vs. temperature  
Figure 57: VIT,TH- vs. temperature  
100  
80  
60  
40  
20  
0
100  
80  
60  
40  
20  
0
Exp.  
Exp.  
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (oC)  
Temperature (oC)  
Figure 58: RON,RCIN vs. temperature  
Figure 59: RON,FLT vs. temperature  
www.irf.com  
© 2007 International Rectifier  
38  
IRS2336xD Family  
Package Details: PDIP28  
www.irf.com  
© 2007 International Rectifier  
39  
IRS2336xD Family  
Package Details: SOIC28W  
www.irf.com  
© 2007 International Rectifier  
40  
IRS2336xD Family  
Package Details: PLCC44  
www.irf.com  
© 2007 International Rectifier  
41  
IRS2336xD Family  
Tape and Reel Details: SOIC28W  
LOADED TAPE FEED DIRECTION  
A
B
H
D
F
C
NOTE : CONTROLLING  
DIMENSION IN MM  
E
G
CARRIER TAPE DIMENSION FOR 28SOICW  
Metric  
Imperial  
Code  
A
B
C
D
E
F
G
H
Min  
11.90  
3.90  
23.70  
11.40  
10.80  
18.20  
1.50  
Max  
12.10  
4.10  
24.30  
11.60  
11.00  
18.40  
n/a  
Min  
Max  
0.476  
0.161  
0.956  
0.456  
0.433  
0.724  
n/a  
0.468  
0.153  
0.933  
0.448  
0.425  
0.716  
0.059  
0.059  
1.50  
1.60  
0.062  
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 28SOICW  
Metric  
Imperial  
Min  
Code  
A
B
C
D
Min  
329.60  
20.95  
12.80  
1.95  
Max  
330.25  
21.45  
13.20  
2.45  
102.00  
30.40  
29.10  
26.40  
Max  
13.001  
0.844  
0.519  
0.096  
4.015  
1.196  
1.145  
1.039  
12.976  
0.824  
0.503  
0.767  
3.858  
n/a  
E
F
98.00  
n/a  
G
H
26.50  
24.40  
1.04  
0.96  
www.irf.com  
© 2007 International Rectifier  
42  
IRS2336xD Family  
Tape and Reel Details: PLCC44  
LOADED TAPE FEED DIRECTION  
A
B
H
D
F
C
NOTE : CONTROLLING  
DIMENSION IN MM  
E
G
CARRIER TAPE DIMENSION FOR 44PLCC  
Metric  
Imperial  
Code  
A
B
C
D
E
F
G
H
Min  
23.90  
3.90  
31.70  
14.10  
17.90  
17.90  
2.00  
Max  
24.10  
4.10  
32.30  
14.30  
18.10  
18.10  
n/a  
Min  
0.94  
Max  
0.948  
0.161  
1.271  
0.562  
0.712  
0.712  
n/a  
0.153  
1.248  
0.555  
0.704  
0.704  
0.078  
0.059  
1.50  
1.60  
0.062  
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 44PLCC  
Metric  
Imperial  
Max  
Code  
A
B
C
D
Min  
329.60  
20.95  
12.80  
1.95  
Max  
330.25  
21.45  
13.20  
2.45  
Min  
12.976  
0.824  
0.503  
0.767  
3.858  
n/a  
13.001  
0.844  
0.519  
0.096  
4.015  
1.511  
1.409  
1.303  
E
F
98.00  
n/a  
102.00  
38.4  
G
34.7  
35.8  
1.366  
1.283  
H
32.6  
33.1  
www.irf.com  
© 2007 International Rectifier  
43  
IRS2336xD Family  
Part Marking Information  
www.irf.com  
© 2007 International Rectifier  
44  
IRS2336xD Family  
Ordering Information  
Standard Pack  
Base Part Number  
Package Type  
Complete Part Number  
Form  
Quantity  
PDIP28  
Tube/Bulk  
13  
25  
IRS2336DPBF  
IRS2336DSPBF  
Tube/Bulk  
SOIC28W  
IRS2336D  
Tape and Reel  
Tube/Bulk  
1000  
27  
IRS2336DSTRPBF  
IRS2336DJPBF  
PLCC44  
Tape and Reel  
Tube/Bulk  
500  
13  
IRS2336DJTRPBF  
IRS23364DPBF  
PDIP28  
Tube/Bulk  
25  
IRS23364DSPBF  
IRS23364DSTRPBF  
IRS23364DJPBF  
IRS23364DJTRPBF  
SOIC28W  
IRS23364D  
Tape and Reel  
Tube/Bulk  
1000  
27  
PLCC44  
Tape and Reel  
500  
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for  
the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other  
rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or  
patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document  
supersedes and replaces all information previously supplied.  
For technical support, please contact IR’s Technical Assistance Center  
http://www.irf.com/technical-info/  
WORLD HEADQUARTERS:  
233 Kansas St., El Segundo, California 90245  
Tel: (310) 252-7105  
www.irf.com  
© 2007 International Rectifier  
45  

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