IRFS4115PBF [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET
| 型号： | IRFS4115PBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET Power MOSFET |
| 文件： | 总10页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 96198
IRFS4115PbF
IRFSL4115PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
D
VDSS
RDS(on) typ.
150V
10.3m
12.1m
99A
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
max.
G
ID
(Silicon Limited)
Benefits
ID (Package Limited)
195A
S
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
D
SOA
D
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
S
D
G
G
D2Pak
IRFS4115PbF
TO-262
IRFSL4115PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
Parameter
Max.
99
Units
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
70
A
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
Pulsed Drain Current
195
396
375
2.5
PD @TC = 25°C
W
Maximum Power Dissipation
Linear Derating Factor
W/°C
V
VGS
± 20
18
Gate-to-Source Voltage
Peak Diode Recovery
dv/dt
TJ
V/ns
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
°C
300
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
EAS (Thermally limited)
220
mJ
A
Avalanche Current
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.4
Units
RθJC
Junction-to-Case
°C/W
RθJA
–––
40
Junction-to-Ambient
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1
11/11/08
IRFS/SL4115PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
150 ––– –––
V
Reference to 25°C, ID = 3.5mA
VGS = 10V, ID = 62A
V
/ T
∆
J
∆
––– 0.18 ––– V/°C
(BR)DSS
RDS(on)
VGS(th)
IDSS
––– 10.3 12.1
mΩ
V
VDS = VGS, ID = 250µA
VDS = 150V, VGS = 0V
VDS = 150V, VGS = 0V, TJ = 125°C
VGS = 20V
3.0
–––
5.0
20
Drain-to-Source Leakage Current
––– –––
µA
––– ––– 250
––– ––– 100
––– ––– -100
IGSS
RG
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
nA
VGS = -20V
–––
2.3
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Conditions
VDS = 50V, ID = 62A
Symbol
gfs
Qg
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
97
––– –––
S
ID = 62A
–––
–––
–––
–––
–––
–––
–––
–––
77
28
26
51
18
73
41
39
120
–––
–––
–––
–––
–––
–––
–––
nC
VDS = 75V
Qgs
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
VGS = 10V
Qgd
ID = 62A, VDS =0V, VGS = 10V
VDD = 98V
Qsync
td(on)
ns
ID = 62A
tr
Rise Time
td(off)
RG = 2.2Ω
VGS = 10V
Turn-Off Delay Time
tf
Fall Time
VGS = 0V
Ciss
Input Capacitance
––– 5270 –––
––– 490 –––
––– 105 –––
pF
VDS = 50V
Coss
Output Capacitance
Crss
ƒ = 1.0 MHz, See Fig. 5
VGS = 0V, VDS = 0V to 120V , See Fig. 11
VGS = 0V, VDS = 0V to 120V
Reverse Transfer Capacitance
Coss eff. (ER)
Coss eff. (TR)
Effective Output Capacitance (Energy Related) ––– 460 –––
Effective Output Capacitance (Time Related) ––– 530 –––
Diode Characteristics
Conditions
Symbol
Parameter
Min. Typ. Max. Units
D
IS
MOSFET symbol
Continuous Source Current
––– –––
99
A
showing the
(Body Diode)
G
ISM
integral reverse
p-n junction diode.
Pulsed Source Current
(Body Diode)
––– ––– 396
A
S
TJ = 25°C, IS = 62A, VGS = 0V
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
––– 86
1.3
V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 130V,
IF = 62A
–––
ns
––– 110 –––
––– 300 –––
––– 450 –––
Qrr
Reverse Recovery Charge
nC
A
di/dt = 100A/µs
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
–––
6.5
–––
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
ISD ≤ 62A, di/dt ≤ 1040A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
ꢀ Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
some lead mounting arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.11mH
RG = 25Ω, IAS = 62A, VGS =10V. Part not recommended for use
above this value .
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
.
.
RθJC value shown is at time zero
2
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IRFS/SL4115PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
TOP
TOP
BOTTOM
BOTTOM
5.0V
1
60µs PULSE WIDTH
Tj = 175°C
≤
5.0V
60µs PULSE WIDTH
Tj = 25°C
≤
1
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
I
= 62A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 50V
DS
≤
60µs PULSE WIDTH
0.1
2
4
6
8
10 12 14 16
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
10000
1000
100
14.0
V
= 0V,
= C
f = 1 MHZ
GS
I = 62A
D
C
C
C
+ C , C
SHORTED
ds
iss
gs
gd
V
V
V
= 120V
= 75V
= 30V
DS
DS
DS
12.0
10.0
8.0
= C
rss
oss
gd
= C + C
ds
gd
C
iss
C
oss
6.0
C
rss
4.0
2.0
10
0.0
1
10
100
1000
0
20
40
60
80
100
V
, Drain-to-Source Voltage (V)
Q , Total Gate Charge (nC)
DS
G
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFS/SL4115PbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
100
10
1
J
100µsec
1msec
DC
T
J
= 25°C
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
3.0
GS
0.1
1
0.0
0.5
V
1.0
1.5
2.0
2.5
3.5
1
10
100
1000
, Source-to-Drain Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
200
190
180
170
160
150
140
120
100
80
60
40
20
0
Id = 3.5mA
-60 -40 -20 0 20 40 60 80 100120140160180
25
50
75
100
125
150
175
T
, Temperature ( °C )
T
, Case Temperature (°C)
J
C
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
900
6.0
5.0
4.0
3.0
2.0
1.0
0.0
I
D
800
700
600
500
400
300
200
100
0
TOP
10A
22A
BOTTOM 62A
-20
0
20 40 60 80 100 120 140 160
Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
V
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRFS/SL4115PbF
1
0.1
D = 0.50
0.20
0.10
0.05
R1
R1
R2
R2
R3
R3
Ri (°C/W) τi (sec)
0.02
0.01
0.01
τ
J τJ
τ
τ
Cτ
0.0500 0.000052
0.1461 0.000468
0.2041 0.004702
τ
1τ1
τ
2 τ2
3τ3
Ci= τi/Ri
0.001
0.0001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
BOTTOM 1.0% Duty Cycle
= 62A
Single Pulse
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
Starting T , Junction Temperature (°C)
EAS (AR) = PD (ave)·tav
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFS/SL4115PbF
50
40
30
20
10
0
6.0
I = 42A
F
V
= 130V
R
5.0
4.0
T = 25°C
J
T = 125°C
J
I
I
I
= 250µA
= 1.0mA
= 1.0A
D
D
D
3.0
2.0
1.0
0
200
400
600
800
1000
-75 -50 -25
0
25 50 75 100 125 150 175
di /dt (A/µs)
T , Temperature ( °C )
F
J
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
50
2500
I = 62A
I = 42A
F
F
V
= 130V
V
= 130V
R
R
40
30
20
10
0
2000
1500
1000
500
0
T = 25°C
T = 25°C
J
J
T = 125°C
J
T = 125°C
J
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/µs)
di /dt (A/µs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
3000
I = 62A
F
V
= 130V
R
2400
1800
1200
600
0
T = 25°C
J
T = 125°C
J
0
200
400
600
800
1000
di /dt (A/µs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFS/SL4115PbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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7
IRFS/SL4115PbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
www.irf.com
IRFS/SL4115PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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9
IRFS/SL4115PbF
D2Pak (TO-263AB) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 11/2008
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10
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