IRFH7004 [INFINEON]
The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. ;型号: | IRFH7004 |
厂家: | Infineon |
描述: | The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. |
文件: | 总12页 (文件大小:274K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
StrongIRFET
IRFH7004PbF
HEXFET® Power MOSFET
Applications
l Brushed Motor drive applications
l BLDC Motor drive applications
l Battery powered circuits
l Half-bridge and full-bridge topologies
l Synchronous rectifier applications
l Resonant mode power supplies
l OR-ing and redundant power switches
l DC/DC and AC/DC converters
l DC/AC Inverters
VDSS
RDS(on) typ.
max.
40V
1.1mΩ
1.4mΩ
259A
ID (Silicon Limited)
ID
100A
(Package Limited)
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
PQFN 5X6 mm
l Enhanced body diode dV/dt and dI/dt Capability
l RoHS Compliant containing no Lead, no Bromide,
and no Halogen
Base Part Number
Package Type
Standard Pack
Form
Tape and Reel
Orderable Part Number
Quantity
4000
IRFH7004PBF
PQFN 5mm x 6mm
IRFH7004TRPBF
6.0
4.0
2.0
0.0
300
250
200
150
100
50
I
= 100A
D
Limited By Package
T
= 125°C
J
T
= 25°C
J
0
4
6
8
10 12 14
16 18 20
25
50
75
100
125
150
T
, Case Temperature (°C)
C
V
Gate -to -Source Voltage (V)
GS,
Fig 2. Maximum Drain Current vs. Case Temperature
Fig 1. Typical On-Resistance vs. Gate Voltage
1
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Absolute Maximum Ratings
Symbol
Parameter
Max.
Units
259
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
Pulsed Drain Current
164
100
1247
156
1.3
A
Maximum Power Dissipation
PD @TC = 25°C
W
Linear Derating Factor
W/°C
V
Gate-to-Source Voltage
± 20
VGS
TJ
Operating Junction and
-55 to + 150
°C
Storage Temperature Range
TSTG
Avalanche Characteristics
Single Pulse Avalanche Energy
EAS (Thermally limited)
191
479
mJ
Single Pulse Avalanche Energy
Avalanche Current
EAS (Thermally limited)
IAR
See Fig. 14, 15, 22a, 22b
A
Repetitive Avalanche Energy
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
0.5
Max.
Units
Junction-to-Case
Junction-to-Case
Junction-to-Ambient
Junction-to-Ambient
0.8
RθJC (Bottom)
RθJC (Top)
–––
–––
–––
15
34
21
°C/W
RθJA
RθJA (<10s)
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min.
Typ.
Max.
Units
Conditions
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
40
–––
–––
V
VGS = 0V, ID = 250μA
V / T
(BR)DSS Δ
––– 0.033 –––
V/°C Reference to 25°C, ID = 1.0mA
Δ
J
m
m
RDS(on)
–––
–––
2.2
1.1
1.7
1.4
–––
3.9
VGS = 10V, ID = 100A
VGS = 6.0V, ID = 50A
VDS = VGS, ID = 150μA
VDS = 40V, VGS = 0V
Ω
Ω
VGS(th)
IDSS
Gate Threshold Voltage
3.0
V
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
–––
–––
–––
–––
2.4
1.0
μA
nA
Ω
150
100
-100
–––
VDS = 40V, VGS = 0V, TJ = 125°C
GS = 20V
VGS = -20V
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
V
RG
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package is limited to 100A by production test
ꢀ Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
capability. Note that current limitations arising from heating of the
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
device leads may occur with some lead mounting arrangements.
(RefertoAN-1140)
.
Repetitive rating; pulse width limited by max. junction
temperature.
When mounted on 1 inch square 2 oz copper pad on 1.5 x 1.5 in. board of
FR-4material.
Rθ is measured at TJ approximately 90°C.
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50Ω, IAS = 31A,
Limited by TJmax, starting TJ = 25°C, L = 0.038mH
RG = 50Ω, IAS = 100A, VGS =10V.
ISD ≤ 100A, di/dt ≤ 1366A/μs, VDD ≤ V(BR)DSS, TJ ≤ 150°C.
VGS =10V.
2
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IRFH7004PbF
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter
Forward Transconductance
Min.
117
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
129
34
Max.
–––
194
–––
–––
–––
–––
–––
–––
–––
Units
S
Conditions
gfs
Qg
VDS = 10V, ID = 100A
Total Gate Charge
nC
ID = 100A
VDS =20V
VGS = 10V
Qgs
Qgd
Qsync
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
40
169
15
ns
VDD = 20V
ID = 30A
Rise Time
51
td(off)
tf
Turn-Off Delay Time
73
R = 2.7
Ω
G
Fall Time
49
VGS = 10V
VGS = 0V
Ciss
Coss
Crss
Input Capacitance
––– 6419 –––
pF
Output Capacitance
–––
–––
952
656
–––
–––
V
DS = 25V
ƒ = 1.0 MHz
VGS = 0V, VDS = 0V to 32V
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
Coss eff. (ER)
oss eff. (TR)
––– 1161 –––
––– 1305 –––
C
VGS = 0V, VDS = 0V to 32V
Diode Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Units
Conditions
100
IS
Continuous Source Current
–––
–––
A
MOSFET symbol
D
S
(Body Diode)
showing the
G
ISM
Pulsed Source Current
–––
––– 1247
A
integral reverse
(Body Diode)
p-n junction diode.
VSD
dv/dt
trr
Diode Forward Voltage
Peak Diode Recovery
–––
–––
–––
–––
–––
–––
–––
0.95
2.5
35
1.3
–––
–––
–––
–––
–––
–––
V
TJ = 25°C, IS = 100A, VGS = 0V
V/ns TJ = 175°C, IS = 100A, VDS = 40V
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ns
nC
A
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 34V,
35
IF = 100A
di/dt = 100A/μs
Qrr
26
27
IRRM
1.5
3
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IRFH7004PbF
10000
1000
100
10
10000
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.0V
4.5V
4.25V
VGS
15V
10V
8.0V
7.0V
6.0V
5.0V
4.5V
4.25V
TOP
TOP
BOTTOM
BOTTOM
4.25V
60μs PULSE WIDTH
Tj = 150°C
≤
60μs PULSE WIDTH
Tj = 25°C
≤
4.25V
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 3. Typical Output Characteristics
Fig 4. Typical Output Characteristics
10000
1000
100
10
1.8
I
= 100A
= 10V
D
V
GS
1.6
1.4
1.2
1.0
0.8
0.6
T
= 150°C
J
T
= 25°C
J
V
= 10V
DS
≤
60μs PULSE WIDTH
1.0
3
4
5
6
7
8
9
-60 -40 -20
0
20 40 60 80 100 120140 160
T
J
, Junction Temperature (°C)
V
, Gate-to-Source Voltage (V)
GS
Fig 6. Normalized On-Resistance vs. Temperature
Fig 5. Typical Transfer Characteristics
14.0
100000
10000
1000
V
= 0V,
= C
f = 1 MHZ
GS
I = 100A
D
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
12.0
= C
rss
oss
gd
= C + C
V
= 32V
= 20V
DS
ds
gd
V
10.0
8.0
6.0
4.0
2.0
0.0
DS
C
iss
C
oss
C
rss
100
0
20 40 60 80 100 120 140 160
0.1
1
10
100
Q , Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage
4
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10000
1000
100
10
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100μsec
T
= 150°C
J
1msec
Limited by
package
10msec
DC
T
= 25°C
J
1
Tc = 25°C
Tj = 150°C
0.1
V
= 0V
Single Pulse
GS
0.01
1.0
0.1
1
10
100
0.0
0.5
1.0
1.5
2.0
2.5
V
, Drain-to-Source Voltage (V)
DS
V
, Source-to-Drain Voltage (V)
SD
Fig 10. Maximum Safe Operating Area
Fig 9. Typical Source-Drain Diode
Forward Voltage
1.0
49
48
47
46
45
44
43
42
41
40
V
= 0V to 32V
Id = 1.0mA
DS
0.8
0.6
0.4
0.2
0.0
0
5
10 15 20
25 30 35 40
-60 -40 -20
0
20 40 60 80 100 120140 160
, Temperature ( °C )
T
V
Drain-to-Source Voltage (V)
J
DS,
Fig 11. Drain-to-Source Breakdown Voltage
Fig 12. Typical COSS Stored Energy
40
V
V
V
V
V
= 5.0V
GS
GS
GS
GS
GS
= 6.0V
= 7.0V
= 8.0V
=10V
30
20
10
0
0
200 400 600 800 1000 1200 1400
I , Drain Current (A)
D
Fig 13. Typical On-Resistance vs. Drain Current
5
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1
D = 0.50
0.20
0.10
0.05
0.1
0.02
0.01
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t
, Rectangular Pulse Duration (sec)
1
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 125°C and
Tstart =25°C (Single Pulse)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 125°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
140
120
100
80
TOP
BOTTOM 1.0% Duty Cycle
= 100A
Single Pulse
I
D
6. Iav = Allowable avalanche current.
60
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
40
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
20
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
0
25
50
75
100
125
150
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 16. Maximum Avalanche Energy vs. Temperature
6
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IRFH7004PbF
4.0
3.0
2.0
1.0
10
8
I = 60A
F
V
= 34V
R
T = 25°C
J
T = 125°C
J
6
I
I
I
= 150μA
= 1.0mA
= 1.0A
D
D
D
4
2
0
-75 -50 -25
0
25 50 75 100 125 150
0
200
400
600
800
1000
T , Temperature ( °C )
di /dt (A/μs)
J
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig 17. Threshold Voltage vs. Temperature
10
300
I = 100A
F
I = 60A
F
V
= 34V
V
= 34V
R
R
250
200
150
100
50
8
6
4
2
0
T = 25°C
T = 25°C
J
J
T = 125°C
J
T = 125°C
J
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/μs)
di /dt (A/μs)
F
F
Fig. 19 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
250
I = 100A
F
V
= 34V
R
200
150
100
50
T = 25°C
J
T = 125°C
J
0
0
200
400
600
800
1000
di /dt (A/μs)
F
Fig. 21 - Typical Stored Charge vs. dif/dt
7
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IRFH7004PbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
-
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
•
dv/dt controlled by RG
• Driver same type as D.U.T.
RG
+
-
Body Diode
Inductor Current
Forward Drop
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
VGS
Ω
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test
Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
Vgs(th)
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 24a. Gate Charge Test Circuit
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Fig 24b. Gate Charge Waveform
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IRFH7004PbF
PQFN 5x6 Outline "B" Package Details
For more information on board mounting, including footprint and stencil recommendation, please refer to application note AN-1136:
http://www.irf.com/technical-info/appnotes/an-1136.pdf
For more information on package inspection techniques, please refer to application note AN-1154:
http://www.irf.com/technical-info/appnotes/an-1154.pdf
PQFN 5x6 Part Marking
INTERNATIONAL
RECTIFIER LOGO
DATE CODE
PART NUMBER
XXXX
(“4 or 5 digits”)
ASSEMBLY
SITE CODE
(Per SCOP 200-002)
MARKING CODE
XYWWX
XXXXX
(Per Marking Spec)
PIN 1
IDENTIFIER
LOT CODE
(Eng Mode - Min last 4 digits of EATI#)
(Prod Mode - 4 digits of SPN code)
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
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IRFH7004PbF
PQFN 5x6 Tape and Reel
REEL DIMENSIONS
TAPE DIMENSIONS
CODE
Ao
DES CRIPTION
Dimension design to accommodate the component width
Dimension design to accommodate the component lenght
Dimension design to accommodate the component thickness
Overall width of the carrier tape
Bo
Ko
W
P
1
Pitch between s ucces sive cavity centers
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Note: All dimens ion are nominal
Package
Type
Reel
Diameter
(Inch)
QTY
Reel
Width
W1
Ao
Bo
Ko
P1
W
Pin 1
(mm)
(mm)
(mm)
(mm)
(mm)
Quadrant
(mm)
5 X 6 PQFN
13
4000
12.4
6.300
5.300
1.20
8.00
12
Q1
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
10
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IRFH7004PbF
Qualification information†
Industrial
Qualification level
(per JEDEC JESD47F †† guidelines )
MS L 1
(per JEDEC J-S TD-020D†† )
Moisture Sensitivity Level
RoHS compliant
PQFN 5mm x 6mm
Yes
Qualification standards can be found at International Rectifiers web site: http://www.irf.com/product-info/reliability/
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
Comment
•
•
Updated EAS (L =1mH) = 479mJ on page 2
2/19/2015
Ω
Updated note 10 “Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50 , IAS = 31A, VGS =10V”. on page 2
•
3/17/2015
Updated package outline and tape and reel on pages 9 and 10.
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
11
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IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
characteristics (“Beschaffenheitsgarantie”) .
contact your nearest Infineon Technologies office
(www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
相关型号:
IRFH7004TRPBF
Power Field-Effect Transistor, 100A I(D), 40V, 0.0014ohm, 1-Element, N-Channel, Silicon, Metal-Oxide Semiconductor FET, 6 X 5 MM, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, B, QFN-8
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