IRFBL12N50A [INFINEON]
HEXFET㈢ Power MOSFET; HEXFET㈢功率MOSFET型号: | IRFBL12N50A |
厂家: | Infineon |
描述: | HEXFET㈢ Power MOSFET |
文件: | 总8页 (文件大小:123K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PD - 91818A
SMPS MOSFET
IRFBL12N50A
HEXFET® Power MOSFET
Applications
VDSS
500V
RDS(on) max
ID
13A
l Switch Mode Power Supply (SMPS)
l Uninterruptible Power Supply
l High Speed Power Switching
0.45Ω
Benefits
l Low Gate Charge Qg Results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
Super-D2PakTM
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
13
8.2
A
52
PD @TC = 25°C
Power Dissipation
180
W
W/°C
V
Linear Derating Factor
1.4
VGS
dv/dt
TJ
Gate-to-Source Voltage
± 30
Peak Diode Recovery dv/dt
Operating Junction and
3.1
V/ns
-55 to + 150
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Typical SMPS Topologies
l Active Clamped Forward
l Main Switch
Notes through ꢀ are on page 8
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1
2/16/00
IRFBL12N50A
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
RDS(on)
VGS(th)
Drain-to-Source Breakdown Voltage
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
500 ––– –––
––– ––– 0.45
V
Ω
V
VGS = 10V, ID = 7.8A
VDS = VGS, ID = 250µA
VDS = 500V, VGS = 0V
VDS = 400V, VGS = 0V, TJ = 150°C
VGS = 30V
2.0
––– 4.0
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
IDSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
IGSS
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
7.5 ––– –––
Conditions
VDS = 50V, ID = 7.8A
ID = 13A
gfs
S
Qg
––– ––– 64
––– ––– 17
––– ––– 26
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC VDS = 400V
VGS = 10V, See Fig. 6 and 13
–––
–––
–––
–––
20 –––
53 –––
43 –––
42 –––
VDD = 250V
ID = 13A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 8.8Ω
RD = 21Ω,See Fig. 10
VGS = 0V
Ciss
Coss
Crss
Coss
Coss
Input Capacitance
––– 1900 –––
––– 290 –––
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
VDS = 25V
–––
12 –––
pF
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 400V ꢀ
––– 2615 –––
–––
–––
76 –––
84 –––
Coss eff.
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
430
13
Units
mJ
EAS
IAR
Avalanche Current
A
EAR
Repetitive Avalanche Energy
18
mJ
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
0.70
40
Units
°C/W
RθJC
RθJA
Junction-to-Ambient (PCB Mounted,steady-state)
–––
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
D
IS
Continuous Source Current
(Body Diode)
MOSFET symbol
13
52
––– –––
––– –––
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
p-n junction diode.
S
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 2.0
––– 540 810
––– 4.1 6.1
V
TJ = 25°C, IS = 13A, VGS = 0V
ns
TJ = 25°C, IF = 13A
Qrr
ton
µC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFBL12N50A
100
10
1
100
10
1
VGS
15V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
TOP
TOP
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
BOTTOM 4.5V
4.5V
4.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
T = 25 C
J
°
T = 150 C
J
°
0.1
0.1
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
13A
=
I
D
2.5
2.0
1.5
1.0
0.5
0.0
°
T = 150 C
J
10
°
T = 25 C
J
1
V
= 50V
DS
V
= 10V
GS
20µs PULSE WIDTH
0.1
4.0
-60 -40 -20
0
20 40 60 80 100 120 140 160
°
5.0
6.0
7.0 8.0
T , Junction Temperature ( C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRFBL12N50A
100000
20
16
12
8
V
= 0V,
f = 1 MHZ
I
D
= 13A
GS
C
= C + C
,
C
SHORTED
V
V
V
= 400V
= 250V
= 100V
iss
gs
gd
ds
DS
DS
DS
C
= C
rss
gd
10000
1000
100
10
C
= C + C
oss
ds
gd
Ciss
Coss
Crss
4
FOR TEST CIRCUIT
SEE FIGURE 13
1
0
1
10
100
1000
0
10
20
30
40
50
60
Q
, Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
100
1000
100
10
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
T
= 150°C
J
10us
100us
10
1ms
T
= 25°C
10ms
J
1
°
T = 25 C
C
°
T = 150 C
Single Pulse
J
V
= 0V
G S
A
1
0.1
10
100
1000
10000
0.4
0.6
0.8
1.0
1.2
1.4
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRFBL12N50A
14
12
10
8
RD
VDS
VGS
D.U.T.
RG
+VDD
-
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
6
Fig 10a. Switching Time Test Circuit
4
V
DS
2
90%
0
25
50
T
75
100
125
°
150
, Case Temperature ( C)
C
10%
V
GS
Fig 9. Maximum Drain Current Vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
P
DM
0.01
t
1
t
2
Notes:
1. Duty factor D =
t / t
1 2
2. Peak T = P
x Z
+ T
C
J
DM
thJC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFBL12N50A
1000
800
600
400
200
0
1 5V
I
D
TOP
5.8A
8.2A
13A
BOTTOM
DRIVER
L
V
G
DS
D.U.T
R
+
V
D D
-
I
A
AS
20V
0.01
t
Ω
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
°
Starting T , Junction Temperature ( C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
6 6 0
Q
Q
GD
GS
V
G
6 4 0
6 2 0
6 0 0
5 8 0
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
A
0
2
4
6
8
1 0
1 2
1 4
V
GS
I
, Avalanche Current (A)
av
3mA
I
I
D
G
Current Sampling Resistors
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
Fig 13b. Gate Charge Test Circuit
6
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IRFBL12N50A
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFBL12N50A
Super-D2PakTM Package Outline
Dimensions are shown in millimeters (inches)
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. (See fig. 11)
Starting TJ = 25°C, L = 5.1mH
RG = 25Ω, IAS = 13A. (See Figure 12)
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630
IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
Data and specifications subject to change without notice. 2/00
8
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