IRFB4310GPBF [INFINEON]
HEXFETPower MOSFET; HEXFETPower MOSFET
| 型号： | IRFB4310GPBF |
| 厂家： | 
Infineon |
| 描述： | HEXFETPower MOSFET |
| 文件： | 总8页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 96190
IRFB4310GPbF
Applications
l High Efficiency Synchronous Rectification in SMPS
HEXFET® Power MOSFET
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
S
VDSS
RDS(on) typ.
max.
100V
5.6m
7.0m
130A
G
ID
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
l Halogen-Free
S
D
G
TO-220AB
IRFB4310GPbF
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Max.
130
Units
92
A
550
PD @TC = 25°C
W
300
Maximum Power Dissipation
Linear Derating Factor
2.0
W/°C
V
VGS
± 20
Gate-to-Source Voltage
14
Peak Diode Recovery
dV/dt
TJ
V/ns
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
°C
300
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
EAS (Thermally limited)
980
mJ
A
Avalanche Current
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.50
–––
62
Units
RθJC
Junction-to-Case
RθCS
RθJA
0.50
–––
°C/W
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
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1
10/15/08
IRFB4310GPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
100 ––– –––
––– 0.064 ––– V/°C Reference to 25°C, ID = 1mA
Conditions
VGS = 0V, ID = 250µA
V
∆V(BR)DSS/∆TJ
RDS(on)
–––
2.0
5.6
7.0
4.0
20
VGS = 10V, ID = 75A
mΩ
V
VGS(th)
–––
VDS = VGS, ID = 250µA
IDSS
Drain-to-Source Leakage Current
––– –––
µA
VDS = 100V, VGS = 0V
––– ––– 250
––– ––– 200
––– ––– -200
V
DS = 100V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Input Resistance
nA VGS = 20V
GS = -20V
f = 1MHz, open drain
V
RG
–––
1.4
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 75A
nC ID = 75A
160 ––– –––
S
––– 170 250
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
–––
–––
–––
46
62
26
–––
–––
–––
V
V
V
DS = 80V
GS = 10V
DD = 65V
ns
––– 110 –––
ID = 75A
td(off)
tf
Turn-Off Delay Time
Fall Time
–––
–––
68
78
–––
–––
RG = 2.6Ω
VGS = 10V
Ciss
Coss
Crss
Input Capacitance
––– 7670 –––
––– 540 –––
––– 280 –––
––– 650 –––
––– 720.1 –––
pF
V
GS = 0V
Output Capacitance
Reverse Transfer Capacitance
VDS = 50V
ƒ = 1.0MHz
Coss eff. (ER)
V
GS = 0V, VDS = 0V to 80V , See Fig.11
GS = 0V, VDS = 0V to 80V , See Fig. 5
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
Coss eff. (TR)
V
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
MOSFET symbol
IS
D
Continuous Source Current
––– –––
A
130
(Body Diode)
Pulsed Source Current
(Body Diode)
showing the
integral reverse
G
ISM
––– ––– 550
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
68
V
TJ = 25°C, IS = 75A, VGS = 0V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 85V,
IF = 75A
di/dt = 100A/µs
–––
–––
–––
45
55
82
ns
83
Qrr
Reverse Recovery Charge
120
nC
––– 120 180
––– 3.3 –––
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Coss eff. (TR) is a fixed capacitance that gives the same charging time
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A
Repetitive rating; pulse width limited by max. junction
temperature.
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
.
Limited by TJmax, starting TJ = 25°C, L = 0.35mH
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 75A, di/dt ≤ 550A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
ꢀ Pulse width ≤ 400µs; duty cycle ≤ 2%.
When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniques refer to
application note #AN-994.
Rθ is measured at TJ approximately 90°C.
2
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IRFB4310GPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
60µs PULSE WIDTH
Tj = 175°C
≤
60µs PULSE WIDTH
Tj = 25°C
≤
4.5V
1
1
0.1
1
10
100
0.1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.0
2.5
2.0
1.5
1.0
0.5
1000
100
10
I
= 75A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
= 50V
J
V
DS
≤ 60µs PULSE WIDTH
1
3.0
4.0
5.0
6.0
7.0
8.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
12000
10000
8000
6000
4000
2000
0
20
V
C
= 0V,
f = 1 MHZ
GS
I = 75A
D
= C + C , C SHORTED
iss
gs
gd ds
V
= 80V
DS
C
= C
rss
gd
16
12
8
VDS= 50V
VDS= 20V
C
= C + C
ds
oss
gd
Ciss
4
Coss
Crss
0
0
40
80
120 160 200 240 280
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB4310GPbF
1000.0
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100.0
10.0
1.0
100µsec
T
= 25°C
J
1
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
10msec
DC
V
= 0V
GS
0.1
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, Source-to-Drain Voltage (V)
1
10
100
1000
V
V
DS
, Drain-toSource Voltage (V)
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
120
115
110
105
100
140
120
100
80
Limited By Package
60
40
20
0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
25
50
75
100
125
150
175
T
, Junction Temperature (°C)
J
T
, Case Temperature (°C)
C
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
2400
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
I
D
TOP
12A
17A
75A
2000
1600
1200
800
400
0
BOTTOM
0
20
V
40
60
80
100
120
25
50
75
100
125
150
175
Drain-to-Source Voltage (V)
Starting T , Junction Temperature (°C)
DS,
J
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFB4310GPbF
1
0.1
D = 0.50
0.20
0.10
0.05
R1
R2
R2
R1
Ri (°C/W) τi (sec)
0.1962 0.00117
τ
0.01
0.02
0.01
J τJ
τ
τ
Cτ
1 τ1
Ci= τi/Ri
τ
2τ2
0.2542 0.016569
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C
and Tstart =25°C (Single Pulse)
Duty Cycle = Single Pulse
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
1000
800
600
400
200
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max)
is exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
BOTTOM 1% Duty Cycle
= 75A
Single Pulse
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
25
50
75
100
125
150
175
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Starting T , Junction Temperature (°C)
J
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB4310GPbF
20
16
12
8
5.0
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250µA
4.0
3.0
2.0
1.0
I
= 30A
= 85V
F
V
T
R
4
= 125°C
= 25°C
J
T
J
0
-75 -50 -25
0
25 50 75 100 125 150 175
100 200 300 400 500 600 700 800 900 1000
T , Temperature ( °C )
J
di / dt - (A / µs)
f
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
500
20
400
300
200
100
0
16
12
8
I
= 30A
= 85V
I
= 45A
= 85V
F
F
V
T
V
T
R
R
4
0
= 125°C
= 25°C
= 125°C
= 25°C
J
J
T
T
J
J
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / µs)
f
di / dt - (A / µs)
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
500
400
300
200
100
0
I
= 45A
= 85V
F
V
T
R
= 125°C
= 25°C
J
T
J
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / µs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFB4310GPbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
LD
VDS
VDS
90%
+
-
VDD
10%
VGS
D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on)
td(off)
tr
tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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7
IRFB4310GPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.10/2008
8
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