IRF3007SPBF [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET
| 型号： | IRF3007SPBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET Power MOSFET |
| 文件： | 总11页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 95494
IRF3007SPbF
AUTOMOTIVE MOSFET IRF3007LPbF
Typical Applications
l
HEXFET® Power MOSFET
42 Volts Automotive Electrical Systems
l
Lead-Free
D
VDSS = 75V
DS(on) = 0.0126Ω
ID = 62A
Features
l
l
l
l
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
R
G
Repetitive Avalanche Allowed up to Tjmax
S
Description
Specifically designed for Automotive applications, this design of
HEXFET® Power MOSFETs utilizes the lastest processing
techniquestoachieveextremelylow on-resistancepersiliconarea.
Additional features of this HEXFET power MOSFET are a 175°C
junction operating temperature, fast switching speed and improved
repetitive avalanche rating. These combine to make this design an
extremely efficient and reliable device for use in Automotive
applications and a wide variety of other applications.
D2Pak
TO-262
IRF3007L
IRF3007S
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
62
44
A
320
PD @TC = 25°C
PowerDissipation
120
W
W/°C
V
LinearDeratingFactor
0.8
VGS
Gate-to-SourceVoltage
± 20
EAS
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
Avalanche Current
290
946
mJ
EAS (6 sigma)
IAR
See Fig.12a, 12b, 15, 16
A
EAR
TJ
Repetitive Avalanche Energy
Operating Junction and
mJ
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
1.25
62
Units
°C/W
RθJC
RθJA
Junction-to-Ambient (PCB Mounted,steady state)**
–––
** This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
www.irf.com
1
07/01/04
IRF3007S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
75 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
––– 0.084 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on)
VGS(th)
gfs
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
––– 10.5 12.6 mΩ VGS = 10V, ID = 48A
2.0
––– 4.0
V
VDS = 10V, ID = 250µA
VDS = 25V, ID = 48A
VDS = 75V, VGS = 0V
VDS = 60V, VGS = 0V, TJ = 150°C
VGS = 20V
Forward Transconductance
180 ––– –––
––– ––– 20
––– ––– 250
––– ––– 200
––– ––– -200
S
IDSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
IGSS
VGS = -20V
Qg
–––
–––
–––
–––
–––
–––
–––
89 130
ID = 48A
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
21
30
32
45
nC VDS = 60V
VGS = 10V
12 –––
80 –––
55 –––
49 –––
VDD = 38V
ID = 48A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 4.6Ω
VGS = 10V
D
Between lead,
4.5
LD
LS
Internal Drain Inductance
Internal Source Inductance
–––
–––
–––
–––
6mm (0.25in.)
nH
G
from package
7.5
and center of die contact
S
Ciss
Input Capacitance
––– 3270 –––
––– 520 –––
VGS = 0V
Coss
Output Capacitance
pF
VDS = 25V
Crss
Reverse Transfer Capacitance
Output Capacitance
–––
78 –––
ƒ = 1.0MHz, See Fig. 5
Coss
––– 3500 –––
––– 340 –––
––– 640 –––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 60V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V
Coss
Output Capacitance
Coss eff.
Effective Output Capacitance ꢀ
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
D
IS
MOSFET symbol
––– –––
80
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
––– ––– 320
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
––– ––– 1.3
––– 85 130
––– 280 420
V
TJ = 25°C, IS = 48A, VGS = 0V
ns
TJ = 25°C, IF = 48A, VDD = 38V
Qrr
ton
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
ꢀ Coss eff. is a fixed capacitance that gives the same charging time
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Starting TJ = 25°C, L = 0.24mH
RG = 25Ω, IAS = 48A, VGS=10V (See Figure 12).
ISD ≤ 48A, di/dt ≤ 330A/µs, VDD ≤ V(BR)DSS
TJ ≤ 175°C
Pulse width ≤ 400µs; duty cycle ≤ 2%.
as Coss while VDS is rising from 0 to 80% VDSS
.
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
,
This value determined from sample failure population. 100%
tested to this value in production.
2
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IRF3007S/LPbF
1000
100
10
1000
100
10
VGS
15V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
TOP
TOP
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM4.5V
BOTTOM4.5V
4.5V
4.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
Tj = 25°C
Tj = 175°C
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
T
= 175°C
J
80
60
40
20
0
100
10
1
T
= 175°C
J
T
= 25°C
J
T
= 25°C
J
V
= 25V
V
= 25V
DS
20µs PULSE WIDTH
DS
20µs PULSE WIDTH
4.0
5.0
6.0
7.0
8.0
9.0
0
40
80
120
160
V
, Gate-to-Source Voltage (V)
GS
I
Drain-to-Source Current (A)
D,
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance
Vs. Drain Current
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3
IRF3007S/LPbF
20
16
12
8
6000
V
= 0V,
= C
f = 1 MHZ
+ C C
GS
V
= 60V
I = 48A
DS
D
C
,
iss
gs
gd
ds
VDS= 38V
VDS= 15V
SHORTED
5000
4000
3000
2000
1000
C
= C
rss
gd
C
= C + C
oss
ds gd
Ciss
4
Coss
Crss
0
0
0
40
G
80
120
160
1
10
100
Q
Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
10000
1000
100
10
1000.0
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
100.0
10.0
1.0
T
= 175°C
J
100µsec
1msec
1
10msec
Tc = 25°C
Tj = 175°C
T
= 25°C
J
Single Pulse
V
= 0V
GS
0.1
0.1
1
10
, Drain-toSource Voltage (V)
DS
100
1000
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
, Source-toDrain Voltage (V)
V
V
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRF3007S/LPbF
70
60
50
40
30
20
10
0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
80A
=
I
D
V
= 10V
GS
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
°
T , Junction Temperature
( C)
T
, Case Temperature (°C)
J
C
Fig 10. Normalized On-Resistance
Fig 9. Maximum Drain Current Vs.
Vs. Temperature
Case Temperature
10
1
0.1
D = 0.50
0.20
0.10
0.05
P
DM
0.02
0.01
t
1
t
2
0.01
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJC
C
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF3007S/LPbF
700
600
500
400
300
200
100
0
15V
I
D
TOP
20A
34A
BOTTOM 48A
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
2
V0GVS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
Starting T , Junction Temperature (°C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
Q
Q
GD
GS
4.0
3.0
2.0
1.0
V
G
I
= 250µA
D
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
V
GS
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
3mA
T
J
I
I
D
G
Current Sampling Resistors
Fig 14. Threshold Voltage Vs. Temperature
Fig 13b. Gate Charge Test Circuit
6
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IRF3007S/LPbF
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
Tj = 25°C due to
∆
0.01
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.05
0.10
1
0.1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
300
TOP
BOTTOM 50% Duty Cycle
= 48A
Single Pulse
I
D
200
100
0
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
25
50
75
100
125
150
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Fig 16. Maximum Avalanche Energy
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Vs. Temperature
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7
IRF3007S/LPbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
-
+
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
RD
VDS
VGS
D.U.T.
RG
+VDD
-
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 18b. Switching Time Waveforms
8
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IRF3007S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
THIS IS AN IRF530S WITH
LOT CODE 8024
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLYLINE "L"
F530S
DAT E CODE
YEAR 0 = 2000
WE E K 02
Note: "P" in assembly line
pos ition indicates "Lead-F ree"
ASSEMBLY
LOT CODE
LINE L
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
F530S
DAT E CODE
P = DE S IGNAT E S L E AD-F R E E
PRODUCT (OPTIONAL)
YEAR 0 = 2000
ASSEMBLY
LOT CODE
WEE K 02
A = ASSEMBLYSITE CODE
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9
IRF3007S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
AS SEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
DATE CODE
YEAR 7 = 1997
WE E K 19
Note: "P" in assembly line
pos ition indicates "L ead-F ree"
AS S E MB L Y
LOT CODE
LINE C
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
AS S E MB L Y
LOT CODE
WE E K 19
A = AS S E MB LY S IT E CODE
10
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IRF3007S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
11.60 (.457)
11.40 (.449)
FEED DIRECTION
TRL
1.85 (.073)
1.65 (.065)
24.30 (.957)
15.42 (.609)
15.22 (.601)
23.90 (.941)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
26.40 (1.039)
24.40 (.961)
4
3
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/04
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11
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