IR3531A-MTRPBF [INFINEON]
41 Phase Dual Output Control IC Pre-bias compatible; 41相双输出控制IC预偏置兼容
| 型号： | IR3531A-MTRPBF |
| 厂家： | 
Infineon |
| 描述： | 41 Phase Dual Output Control IC Pre-bias compatible |
| 文件： | 总39页 (文件大小：1396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IR3531A
4+1 Phase Dual Output Control IC
FEATURES
DESCRIPTION
Integrated 6.8V/0.8A Buck Regulator provides
The IR3531A control IC provides all the necessary control,
communication and protection to support compact dual
output power solutions up to 210W. The IR3531A can be
combined with either discrete IR3535 driver ICs and Direct
FetsTM or our IR35XX family of footprint compatible and
scalable PowIRstagesTM which integrate the MOSFETs and
driver into the same package.
bias to Control and Driver IC(s)
Adjustable switching frequency from 250 KHz up
to 1.5MHz per phase based on the synchronization
SCLK input
Sink and source tracking capability
Margining via SVID for both rails
Pre-bias compatible
The IR3531A provides overall system control and current
sharing while the Driver IC or power stages senses per-
phase current locally and communicates it to the Control
IC. The IR3531A has tri-state PWM outputs to allow diode
emulation during light load events.
Soft Stop capability
0.5% overall system set point accuracy
Voltage Mode Modulation for excellent transient
performance
The IR3531A provides a high performance transient
solution through classic voltage mode control and Body
BrakingTM. Body BrakingTM automatically turns off the low-
side MOSFET to help dissipate stored inductor energy at
load turn-off.
Single NTC thermistor for current reporting, OC
Threshold, and Load Line thermal compensation
Complete protection including over-current,
over-voltage, over-temperature, open remote
sense and open control loop
Thermally enhanced 48L 7mm x 7mm MLPQ
package
RoHS compliant
PIN DIAGRAM
BASIC APPLICATION CIRCUIT
48 47 46 45 44 43 42 41 40 39 38 37
EN
VRHOT#
VRRDY1
VRRDY
VCC
1
2
36
35
34
33
32
31
30
29
28
27
26
25
BBR1#
PWM4
PWM3
TSENS
ROSC/OVP
ADDR
3
4
A
5
IR3531A
SW
6
V12V
7
ICCP
48 Pin 7 x 7 MLPQ
Top View
ALERT#
VCLK
8
SCLK
9
PWM2
PWM1
BBR#
VDIO
10
PHSSHED 11
IMON_R1 12
49 GND
TRACK
13 14 15 16 17 18 19 20 21 22 23 24
Figure 2: IR3531A Package Top View
Figure 1: IR3531A Basic Application Circuit,
showing a 4+1 Configuration
1
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
ORDERING INFORMATION
IR3531A ― M
Package
Tape & Reel Qty
Part Number
48 Lead MLPQ
(7x7 mm body)
100
IR3531A-MPBF
PBF – Lead Free
48 Lead MLPQ
(7x7 mm body)
Note 1: Samples only.
3000
IR3531A-MTRPBF1
TR – Tape and Reel
48 47 46 45 44 43 42 41 40 39 38 37
EN
VRHOT#
VRRDY1
VRRDY
VCC
1
2
36
35
34
33
32
31
30
29
28
27
26
25
BBR1#
PWM4
PWM3
TSENS
ROSC/OVP
ADDR
3
4
5
IR3531A
SW
6
V12V
7
ICCP
48 Pin 7 x 7 MLPQ
Top View
ALERT#
VCLK
8
SCLK
9
PWM2
PWM1
BBR#
VDIO
10
PHSSHED 11
IMON_R1 12
49 GND
TRACK
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3: Package Top View, Enlarged
2
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
FUNCTIONAL BLOCK DIAGRAM
Figure 4: IR3531A Block Diagram
3
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
TYPICAL APPLICATION DIAGRAM
CCP1
RCP1
CFB1
RCFB1
TO IOUT SIGNALS
OF PHASES 3, 4
RFB1
CEA1
TO PWM SIGNALS
OF PHASES 3, 4
RDRP1
BBR1#
VDAC1
RSCALE3
RSCALE2
RSCALE1
RTHERM3
IOUT1
PWM_R1
RHOTSET2
VDAC
1
36
35
34
33
32
31
30
29
28
27
26
25
ENABLE
EN
BBR1#
PWM4
2
VRHOT#
VRRDY1
VRRDY
VRHOT#
RHOTSET1
RTHERM2
RHOTSET3
3
4
VRRDY1
VRRDY
VCC
PWM3
TSENS
ROSC/OVP
ADDR
5
LVCC
ROSC
RICCP1
RICCP2
RADDR1
VDAC
1
2
6
RADDR2
SW
IR3531A
7
12V
ALERT#
VCLK
V12V
ICCP
COUTVCC
8
ALERT#
VCLK
SCLK
9
SCLK
PWM2
10
11
12
VDIO
VDIO
PWM1
TO PWM SIGNALS
OF PHASES 1, 2
PHSSHED
PWM2
PWM1
PHSSHED
IMON_R1
BBR#
TRACK
CIMON1
49
BBR#
GND
TRACK
CIMON
IIN2
IIN1
TO IOUT SIGNALS
OF PHASES 1, 2
RTCMP3
VDAC
CCP
RPSC
RCP
CFB
RCFB
RTCMP1
RTHERM1
CEA
RFB
RTCMP2
RDRP
Figure 5: IR3531A Typical Application Diagram
4
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
Enable input. Grounding this pin shuts down the voltage regulators. Do not float this pin as the
logic state will be undefined.
1
EN
Open collector output of the VRHOT# comparator which drives low if Rail0 temperature exceeds
the programmed threshold. Connect external pull-up to bias.
2
3
4
VRHOT#
VDRRY1
VDRRY
Open collector output that drives low during startup and under any external fault condition for
Rail1 regulator. Connect external pull-up to bias.
Open collector output that drives low during startup and under any external fault condition for
Rail0 regulator. Connect external pull-up to bias.
5
6
7
8
VCC
SW
Bias buck regulator output, feedback pin, and bias input for internal circuitry.
Switching node for bias buck regulator.
V12V
ALERT#
Power Supply input supply rail.
Output pin for SVID Alert# interrupt. Open collector output that drives low to notify the master.
SVID Clock Input. Clock is a high impedance input pin. It is driven by the open collector output of a
microprocessor and requires a pull-up resistor.
9
VCLK
VDIO
SVID Data Input/Output. High impedance input when address, command or data bits are shifted in,
open drain output when acknowledging or sending data back to the microprocessor. Pin requires a
pull up resistor.
10
Analog signal that represents the number of phases to be disabled. 0% to 25% VCC, no phases
disabled. 25% to 50% VCC, disable 1 phase. 50% to 75% VCC, disable 2 phases. 75% to 100% VCC,
disable 3 phases (if available).
11
PHSSHED
Voltage at this pin is proportional to Rail1 load current. It is also the input to the ADC for output
current register.
12
13
IMON_R1
IMON
Voltage at this pin is proportional to Rail0 load current. It is also the input to the ADC for output
current register.
Voltage Regulator Rail 0 reference voltage programmed by SVID. VDAC is also used as the A/D
reference during power up for pins ADDR/PSN, TSENS and ICCP.
14
15
16
VDAC
VN
Node for DCR thermal compensation network.
Buffered, scaled and thermally compensated current signal for Rail0. Connect an external resistor
to FB to program converter output impedance.
VDRP
17
EA
PSC
Output of the error amplifier for Rail0.
18
Node for Power Savings mode compensation input.
Inverting input to the Error Amplifier for Rail0.
19
FB
20
VO
Remote sense amplifier output for Rail0.
21
VOSEN+
VOSEN-
IIN1-4
TRACK
BBR#
Rail0 remote sense amplifier input. Connect to output at the load.
Rail0 remote sense amplifier input. Connect to ground at the load.
Current signals from the driver IC-s of Rail0.
22
23, 24, 37, 38
25
26
External tracking reference for Rail0.
Body-brakingTM bus for Rail0 driver ICs to disable synchronous switches.
PWM outputs for Rail0. Each output is connected to the input of the driver IC. Connecting the
PWMx output to LGND disables the phase, allowing the IR3531A to operate as a 1, 2, 3, or 4 phase
controller.
27, 28,
34, 35
PWM1-4
SCLK
29
Synchronization clock input. Program ROSC using ROSC vs. Frequency to match the SCLK frequency.
5
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
PIN #
PIN NAME
ICCP
PIN DESCRIPTION
Program maximum load current for both Rail0 and Rail1.
Programs SVID address for Rail0 and Rail1.
30
31
ADDR
Connect a resistor to LGND to program oscillator frequency. Oscillator frequency equals switching
frequency per phase. ROSC/OVP pin is pulled up to VCC when an over voltage event occurs.
32
ROSC/OVP
33
36
39
40
41
42
43
44
TSENS
BBR1#
TRACK1
VOSEN1-
VOSEN1+
VO1
Pin for thermal network that senses the temperature of Rail0 and Rail1.
Body-brakingTM bus for Rail1 driver ICs to disable synchronous switches.
External tracking reference for Rail1.
Rail1 remote sense amplifier input. Connect to ground at the load.
Rail1 remote sense amplifier input. Connect to output at the load.
Remote sense amplifier output for Rail1.
FB1
Inverting input to the Error Amplifier for Rail1.
EA1
Output of the error amplifier for Rail1.
Buffered, scaled and thermally compensated current signal for Rail1. Connect an external resistor
to FB1 to program converter output impedance.
45
VDRP1
46
47
48
49
VDAC1
IIN_R1
PWM_R1
GND
Buffered Rail1 reference voltage. Voltage can be margined via SVID.
Current signal from Rail1 driver IC.
PWM output for Rail1.
Local Ground for internal circuitry and IC substrate connection.
6
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Range
Operating Junction Temperature
ESD Rating
-65°C To 150°C
0°C To 150°C
HBM Class 1C JEDEC Standard
MSL Rating
2
Reflow Temperature
260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications are not implied.
PIN Number
PIN NAME
EN
VMAX
3.5V
VCC
VCC
VCC
8V
VMIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-1.0V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
ISOURCE
25mA
1mA
1mA
1mA
1mA
3A
ISINK
1mA
50mA
20mA
20mA
20mA
1mA
1.5A
50mA
1mA
50mA
1mA
1mA
1mA
35mA
1mA
1mA
5mA
1mA
1mA
5mA
1mA
1mA
1mA
1mA
1mA
5mA
5mA
1
2
VRHOT#
VDRRY1
VDRRY
VCC
3
4
5
6
SW
16V
16V
3.5V
3.5V
3.5V
VCC
3.5V
3.5V
3.5V
VCC
VCC
VCC
VCC
VCC
VCC
VCC
1.0V
VCC
VCC
VCC
VCC
VCC
7
V12V
ALERT#
VCLK
1mA
1mA
1mA
1mA
1mA
25mA
25mA
5mA
1mA
35mA
35mA
1mA
1mA
35mA
5mA
5mA
1mA
1mA
1mA
1mA
1mA
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VDIO
PHSSHED
IMON_R1
IMON
VDAC
VN
VDRP
EA
PSC
FB
VO
VOSEN+
VOSEN-
IIN1
IIN2
TRACK
BBR#
PWM1
7
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
PIN Number
PIN NAME
PWM2
SCLK
VMAX
VCC
3.5V
3.5V
3.5V
VCC
3.5V
VCC
VCC
VCC
VCC
VCC
VCC
1.0V
VCC
VCC
VCC
VCC
VCC
3.5V
VCC
VCC
N/A
VMIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
N/A
ISOURCE
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
5mA
5mA
35mA
1mA
35mA
35mA
1mA
1mA
1mA
20mA
ISINK
5mA
5mA
1mA
1mA
1mA
1mA
5mA
5mA
5mA
1mA
1mA
1mA
1mA
1mA
5mA
1mA
5mA
1mA
35mA
1mA
1mA
1mA
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
ICCP
ADDR
ROSC
TSEN
PWM3
PWM4
BBR1#
IIN3
IIN4
TRACK1
VOSEN1-
VOSEN1+
VO1
FB1
EA1
VDRP1
VDAC1
IIN_R1
PWM_R1
GND
8
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
The electrical characteristics table lists the spread of values guaranteed within the recommended operating conditions.
Typical values represent the median values, which are related to 25°C. Unless otherwise specified, these specifications
apply over: -0.3V ≤ VOSEN- ≤ 0.3V, 7.75KΩ ≤ ROSC ≤ 50.0 KΩ
Recommended V12V Range
10.8V
6.6
12
6.8
0
13.2V
7.0
V
V
Recommended VCC Range
VOSEN- and VOSEN1- to LGND offset
ROSC Resistor Programming Range
Recommended Operating Junction Temperature
-0.3
7.75
0
0.3
V
50
KΩ
ºC
TJ
100
ELECTRICAL CHARACTERISTICS
PARAMETER
VDAC Reference
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
System Set-Point Accuracy
SETACC
VID ≥ 1V
-0.5
-5
-
-
0.5
+5
+8
25
6.25
-
%
mV
0.8 ≤ VID < 1V
0.25V ≤ VID < 0.8V
-8
-
mV
Slew Rate – Fast Mode
Slew Rate – Slow Mode
Default VBOOT Rail 0
Default VBOOT Rail 1
Oscillator (Note 4)
ROSC Voltage
VIDFAST
VIDSLOW
VBOOT0
VBOOT1
15
3.75
-
20
5
mV/µs
mV/µs
V
Note 3
Note 3
1.5
1.5
-
-
V
VROSC
ROSC = 24.5 KΩ
ROSC = 50.0 KΩ
ROSC = 24.5 KΩ
ROSC = 7.75 KΩ
0.570
0.595
250
0.620
V
PWM Frequency
FSWMIN
FSWTYP
FSWMAX
-
-
-
-
-
-
kHz
kHz
MHz
500
1.50
VDAC Buffer Amplifier
Input Outset Voltage
DACOFF
V(VDAC, VDAC1) ― VID code +
VID offset, 0.25V ≤
-15
0
15
mV
mA
V(VDAC, VDAC1) ≤ 1.52V,
< 1mA load
Source Current
Sink Current
DACSRC
DACSNK
0.25V ≤ V(VDAC1) ≤ 1.52V
0.25V ≤ V(VDAC) ≤ 1.52V
0.5V ≤ V(VDAC1) ≤ 1.52V
V(VDAC1) = 0.25V
0.3
0.9
2
0.44
1.65
13
0.6
2.4
20
2
0.5
3
1.5
15
mA
0.5V ≤ V(VDAC) ≤ 1.52V
V(VDAC) = 0.25V
30
3
0.5
1.5
9
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
PARAMETER
Unity Gain Bandwidth
SYMBOL
CONDITIONS
MIN
TYP
3.5
1.5
MAX
UNIT
-
-
-
-
MHz
V/µs
Slew Rate
Thermal Compensation Amplifier (VDRP)
Output Offset Voltage
VDRPOUTOFF
0V ≤ V(IIN) – V(VDAC) ≤ 1.52V,
0.25V ≤ V(VDAC) ≤ 1.52V,
Req/R2 = 2
-14
0
14
mV
Source Current
Sink Current
VDRPSRC
VDRPSNK
0.25V ≤ V(VDAC) ≤ 1.52V
0.5V ≤ V(VDRP) ≤ 1.52V
V(VDRP) = 0.25V
3
0.2
0.175
2
8
0.4
0.25
4.5
5.5
0
15
0.7
0.4
7
mA
mA
Unity Gain Bandwidth
Slew Rate
Req/R2 = 2, Note 1
MHz
V/µs
µA
-
-
VN Bias Current
V(VN) = 2 V
-2
2
Power Savings Mode Operation
PS2/PS3 Turn-on Threshold
PS2THRSH
PS2COT0
VID = 250 mV
250
2
350
2.15
151
409
100
358
385
2.26
200
480
200
480
mV
V
VID = 1.52 V
PS2/PS3 Pulse Width Rail0
PS2/PS3 Pulse Width Rail1
PS Mode Enter Delay
VID = 250 mV, SF = 500 kHz
VID = 1.52 V, SF = 500 kHz
VID = 250 mV, SF = 500 kHz
VID = 1.52 V, SF = 500 kHz
PS0 to PS1 only
60
ns
ns
220
50
PS2COTMIN1
PS2COTMAX1
PS1DELAY
220
PWM
Cycle
-
8
-
Enable Input
Rising Threshold
Falling Threshold
Hysteresis
ENRISE
ENFALL
ENHYST
ENBIAS
625
575
25
650
600
50
675
625
75
mV
mV
mV
µA
Bias Current
0V ≤ V(ENABLE) ≤ 3.3V
-5
0
5
Blanking Time
Noise Pulse < 100ns will not
register an ENABLE state change.
Note 1
75
250
400
90
ns
IMONx Current Report Amplifier
Output Offset Voltage
IMONOFF
VDRP–VDAC = 0, 225, 450,
15
50
mV
900mV
Unity Gain Bandwidth
Input Filter Time Constant
Max Output Voltage
Note 1
-
-
1
1
-
MHz
µs
V
-
1.145
2
IMONMAX
IMONACC
1.00
-2
1.09
0
Current Report A/D Accuracy
Rail1 VDRP Amplifier
VDRP–VDAC = 900mV
%
Output Outset Voltage
VDRP1OFF
0V≤ V(IIN_R1) - V(VDAC1) ≤ 0.2V
0.25V ≤ V(IIN_R1) - V(VDAC1) ≤
1.52V
-75
0
75
mV
10
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
PARAMETER
Source Current
SYMBOL
VDRP1SRC
VDRP1SNK
CONDITIONS
0.25V ≤ V(VDAC1) ≤ 1.52V
0.5V≤ V(VDRP1) ≤ 1.52V
V(VDRP1) = 0.25V
Note 1
MIN
TYP
8
MAX
UNIT
3
0.2
0.175
-
15
mA
mA
Sink Current
0.4
0.25
9
0.6
0.375
Closed Loop Gain
Unity Gain Bandwidth
Slew Rate
-
3
-
V/V
MHz
V/µs
Note 1
0.8
-
1.5
5.5
Note 1
Error Amplifier
Input Offset Voltage
FB Bias Current
DC Gain
Note 2 (test mode only)
-
-1
0
0
-
1
mV
µA
Note 1
Note 1
Note 1
100
20
7
110
30
120
40
dB
Unity Gain Bandwidth
Slew Rate
MHz
V/µs
mA
mA
mV
mV
12
20
Sink Current
EASRC
0.40
5
0.85
8
1.35
12
Source Current
Maximum Voltage
Minimum Voltage
EASNK
EAMAX
EAMIN
Measure V(VCC) – V(EA), V(EA1)
500
-
925
120
1100
250
Open Voltage Loop Detection
Threshold
EAOPENTHR
Measure V(VCCx) - V(EA), V(EA1),
Relative to Error Amplifier
maximum voltage
100
300
1100
mV
Open Loop Detection Delay
EAOPENDEL
EAPS2CLMP
V(EA), V(EA1) = V(VCC) to
VRRDY = low
-
8
-
PWM
mV
PS2 Clamp Voltage
Phase Firing Comparators
Input Offset
With respect to VDAC
-240
-70
-10
KEEPOFF
KEEPDEL
-30
-
0
-
30
mV
ns
Propagation Delay
Phase Shedding Comparators
Bias Current
320
PHSDBIAS
PHSDTHRS
-2
0
2
µA
V
Threshold
Comparator 1
Comparator 2
Comparator 3
1.3
3.0
4.8
1.7
3.4
5.1
2.0
3.85
5.55
PWM Comparator
PWM Ramp Slope
PWMSLP
V12V= 12V
mV/
%DC
42
-5
52.5
57
Minimum Pulse Width
Input Offset Voltage
Share Adjust Amplifier
Input Offset Voltage
Gain
PWMMIN
PWMOFF
Note 1
Note 1
55
0
70
5
ns
mV
SAAOFF
Note 1
-3
4
0
3
6
mV
V/V
kHz
SAAGAIN
CSIN+ = CSIN- = DACIN, Note 1
Note 1
5.0
8.5
Unity Gain Bandwidth
4
17
11
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Maximum PWM Ramp
Floor Voltage
MINFLOOR
IOUT = DACIN – 200mV
Measure relative to floor voltage
100
180
22 0
mV
mV
Minimum PWM Ramp
Floor Voltage
MAXFLOOR
IOUT = DACIN + 200mV
Measure relative to floor voltage
-220
-160
-100
Over Voltage Protection (OVP) Comparators
Threshold at Power-up
OVPPUP
1.615
100
1.65
130
1.67
150
V
Threshold during Normal
Operation
OVPTHR
Compare to VID Voltage +
VID offset
mV
Propagation Delay to OVP
OVPPROP
Measure time from V(FB), V(FB1)
> VID voltage + VID offset (250mV
overdrive) to V(PWM) transition
to > 0.5 * V(VCC)
-
90
180
ns
Over-Current Comparator
Input Filter Time Constant
Over-Current Threshold
-
2
-
µs
V
OCTHRSH
OCPSI
VDRP-VDAC, VDRP1-VDAC1
PSI mode, 4ph to 2ph, 2ph to 1ph
PSI mode, 3ph to 1ph
3ph to 2ph
0.94
450
310
640
220
690
225
1.08
540
360
720
270
800
256
1.18
610
410
800
310
900
285
OC Threshold PSI Reduction
Factor
mV
µs
PSI mode, 4ph to 1ph
4ph to 3ph
OC Delay Time
VCC Undervoltage
VCC UVL Start
OCDELAY
Delay to OC shutdown
VCCSTART
VCCSTOP
VCCHYST
5.5
4.85
515
5.85
5.2
6.4
5.65
830
V
V
VCC UVL Stop
VCC UVL Hysteresis
VRRDY Output
650
mV
Output Voltage
VRRDYLO
I(VRRDY, VDRRY1) = 4mA
V(VRRDY, VDRRY1) = 5.5V
-
-
150
0
300
10
mV
µA
Leakage Current
VCC Activation Voltage
VRRDYLEAK
VRRDYVCC
I(VDRRY, VDRRY1) = 4mA,
<300mV
1
2
3.6
V
VO-TRACK Undervoltage
Threshold
VOUVFALL
VOUVRISE
Reference to TRACK
-260
-340
-200
-290
-130
-230
mV
mV
VO-VDAC Undervoltage
Threshold
Reference to VDAC
Open Sense Line Detection
OPENACT
Sense Line Detection Active
Comparator Threshold Voltage
100
25
150
60
200
80
mV
mV
%
OPENOFF
V(VO) < [V(VOSEN+) –
V(LGND)] / 2
Sense Line Detection Active
Comparator Offset Voltage
OPENCOMP+
Compare to V(VCC)
VOSEN+ Open Sense Line
Comparator Threshold
82
90
92
12
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
VOSEN- Open Sense Line
Comparator Threshold
OPENCOMP-
0.36
0.40
0.44
V
Sense Line Detection
Source Currents
OPENSRC
V(VO) = 100mV
200
500
700
µA
VCC Buck Regulator
VCC Output Voltage
Switch Node Rise Time
Switch Node Fall Time
A/D Program Inputs
ADDR Pin Bias Current
ICCP Pin Bias Current
TSENS Pin Bias Current
A/D Comparator Offset
V12V Undervoltage
VCC V12V Start
VCC100
SWRISE
SWFALL
100–400 mA load current
6.5
6.8
5
7.1
V
Note 1
Note 1
-
-
-
-
ns
ns
15
ADDRBIAS
ICCPBIAS
TSENBIAS
ADOFFSET
-2
-2
-2
-5
0
0
0
0
2
2
2
5
µA
µA
µA
mV
VCCSTART
VCCSTOP
VCCHYST
8.8
7.8
0.8
9.6
8.6
1
10.2
9.2
V
V
V
VCC V12V Stop
VCC V12V Hysteresis
SerialVID
1.3
ALERT#, VDIO Buffer On
Resistance
ALERTRES
-
-
14.3
Ω
ALERT#, VDIO Leakage Current
VCLK Bias Current
ALERTLEAK
VCLKBIAS
-10
-1
0
0
10
1
µA
µA
µA
ns
VDIO Bias Current
VDIOBIAS
-1
0
1
Transmit Data Prop Delay
Comparator Threshold
XMITDELAY
SVIDTHRSH
VCLK rising to VDIO change
VCLK, VDIO rising
4
6
12
650
650
-
500
450
50
590
515
75
-
mV
VCLK, VDIO falling
Comparator Hysteresis
Link States Reset Timer
PWMx Outputs
SVIDHYST
SVIDTIME
mV
ns
200
600
Source Resistance
PWMSRCR
PWMSNKR
PWMTRIZ
50
75
2.0
-5
144
117
5.4
0
500
290
7.5
5
Ω
Ω
Sink Resistance
Tri-state Source Impedance
Tri-state Bias Current
Tri-state Active Pull-up
KΩ
µA
PWMTRIBIAS
PWMTRIPUP
V(PWMx) = 1.65V
V(PWMx) while sourcing
100 µA to GND
0.5
0.4
1
1.2
0.9
V
V
Disable Comparator Threshold
PWM High Voltage
PWMDISTHR
PWMHIGH
0.6
I(PWM) = -1mA,
-
-
1
V
measure VCC-PWM
13
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
PARAMETER
PWM Low Voltage
SYMBOL
CONDITIONS
I(PWM) = -1mA
MIN
TYP
MAX
UNIT
PWMLOW
-
-
1
V
Body Braking Comparator
Threshold Voltage with EAIN
Decreasing
BBRTHRFALL
BBRTHRRISE
Measure relative to floor voltage
Measure relative to floor voltage
-300
-200
-110
mV
Threshold Voltage with EAIN
Increasing
-200
70
-100
105
-10
mV
mV
Hysteresis
BBRTHRHYS
BBRDELAY
130
Propagation Delay
VCC = 5V
Measure time from EAIN <
V(DACIN) (200mV overdrive)
to GATEL transition to < 4V.
30
65
90
ns
BBR1# Source Resistance
BBR1# Sink Resistance
BBR1# High Voltage
BBRSRCRES
BBRSNKRES
BBRHIGH
20
10
40
35
75
60
Ω
Ω
I(BBR1#) = -1mA, measure V(VCC)
– V(BBR1#)
0
0
0.4
0.8
0.8
V
V
BBR1# Low Voltage
BBRLOW
I(BBR1#) = 1mA
0.35
Remote Sense Differential Amplifier
Unity Gain Bandwidth
RSABW
RSAOFF
Note 1
1.5
-5
3.2
0
4.5
5
mV
mV
Input Outset Voltage
0.25V≤ V(VOSEN+) - V(VOSEN-)
≤ 1.52V,
0.25V≤ V(VOSEN1+) - V(VOSEN1-)
≤ 1.52V
Sink Current
RSASINK
0.5V≤ V(VOSEN+) - V(VOSEN-)
≤ 1.52V,
0.4
0.225
3
1
0.5
9
2
0.5V≤ V(VOSEN1+) - V(VOSEN1-)
≤ 1.52V
mA
mA
V(VOSEN+) - V(VOSEN-) = 0.25V,
V(VOSEN1+) - V(VOSEN1-) =
0.25V
0.8
20
Source Current
Slew Rate
RSASRC
0.25V≤ V(VOSEN+) - V(VOSEN-)
≤ 1.52V,
0.25V≤ V(VOSEN1+) - V(VOSEN1-)
≤ 1.52V
RSASLEW
0.25V≤ V(VOSEN+) - V(VOSEN-)
≤ 1.52V,
0.25V≤ V(VOSEN1+) - V(VOSEN1-)
≤ 1.52V
2
-
4
8
V/µs
µA
VOSEN+ Bias Current
VOSEN- Bias Current
VOSNS-BIAS
VOSNS+BIAS
0.25 V < V(VOSEN+) < 1.52V,
0.25 V < V(VOSEN1+) < 1.52V
27
27
50
70
-0.3V ≤ VOSEN- ≤ 0.3V, All VID
Codes,
-0.3V ≤ VOSEN1- ≤ 0.3V, All VID
-
µA
Codes
High Voltage
Low Voltage
VOHIGH
VOLOW
V(VCC) – V(VO), V(VCC) – V(VO1)
1.5
-
2
2.5
V
V(VCC) = 7V
60
100
mV
VRHOT# Comparator
14
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
PARAMETER
Output Voltage
SYMBOL
VRHTOUT
CONDITIONS
I(VRHOT#) = 30mA
MIN
TYP
150
0
MAX
400
10
UNIT
-
-
mV
µA
VRHOT# Leakage Current
Platform Test Mode
VRHTLEAK
V(VRHOT#) = 5.5V
Comparator Threshold
PTMTHR
Raise ADDR voltage after VIN
power-up
2.2
20
2.6
-
3.1
24
V
Link States Reset Timer
VR Settled
PTMTIME
µs
Comparator Offset
Delay to ALERT#
VRSTLOFF
Compare FB to VDAC reference
-
-
20
5
-
-
mV
µs
VRSTLDELAY
Delay after DAC settled to within
2 VID steps of final value
Current Inputs
IINx to IINx Impedance
IINx to IINx Leakage Current
TRACK Inputs
IINRES
-
3000
0
-
Ω
IINLEAK
-1
1
µA
Input Leakage
-1
15
-1
0
36
0
1
65
1
µA
mV
mV
TRACK to FB Offset
Release Error Voltage
VO Discharge Comparators
Tri-state Enable Threshold
Error amp in unity gain
TRACK = VDAC+100mV, VDAC-FB
VO when PWM outputs enter
tri-state
200
250
300
mV
SCLK Synchronization Input
Rising Threshold
0.8
1.2
1.3
1.025
5
V
V
Falling Threshold
Input Leakage
Note 1
Note 1
0.625
0.85
-5
-
0
-
µA
ns
pF
Propagation Delay Rising
Input Capacitance
General
60
-
-
10
VCC Supply Current
VCCBIAS
3
7
12
mA
Notes:
1. Guaranteed by design but not tested in production
2. Error Amplifier input offset is trimmed to within ±1% for optimal system set point accuracy.
3. Final test VBOOT options of 0, 0.9, 1.35 and 1.5V are feasible.
Contact International Rectifier Enterprise Power Business Unit for details.
4. Use SCLK input to set PWM frequency.
15
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
The SCLK input frequency provided needs to equal the
desired base switching frequency multiplied by the active
number of phases. Phase shedding is available however
SCLK needs to be adjusted accordingly to match the
number of active phases.
THEORY OF OPERATION
SYSTEM DESCRIPTION
The IR3531A Multiphase Buck power system provides
voltage regulation solutions for two individual supply
outputs. The main output, Rail0, controls up to four phases
and produce up to 200A when paired with appropriate
power stages. The secondary output, Rail1, is a single
phase output capable of up to 50A, again with appropriate
power stage. The IR3531A control IC is specialized to allow
external clock synchronization and tracking capability for
each rail. Features include a serial control and telemetry
bus that can control output voltage settings and slew
rates while allowing monitoring of the system thermals
and load currents. The IR3531A control IC contains all
necessary housekeeping, protection and control functions
and communicates a three-level PWM signal to each
power stage.
The system clock frequency has a programmable range
from 250kHz to 9MHz selected by an external resistor
from the ROSC pin to ground. Phase timing and interleave
spacing is automatically optimized inside the controller
and can accommodate changing phases on the fly (phase
shedding). The PHSSHD pin can be used to dynamically
drop from 1-3 phases while minimizing output voltage
transients. Also, phases can be disabled by grounding the
PWM outputs of the IR3531A. Notice the driver ICs should
be removed since a PWM low signal indicates a 0% duty
cycle state which turns on the low side MOSFETs and
can potentially develop large negative inductor currents.
The control IC detects which PWM pins are grounded
during power up to determine the populated number of
phases and automatically optimizes phase timing for
minimal system ripple.
FREQUENCY AND PHASE TIMING CONTROL
The IR3531A requires external frequency synchronization
which can be used to control input ripple from multiple
paralleled power supply systems. Systems can be forced
to operate out of phase thereby reducing instantaneous
peak input currents and also controlling system noise
signatures. The internal oscillator is used to calibrate the
PWM ramp slopes and other functions at power up
therefore it is desirable for the externally applied
synchronization frequency to be very near the ROSC
programmed internal frequency times the number of
active phases. Calibration can take up to 1ms. This results
in the PWM gain to be near the desired 50mV/% duty
cycle. Furthermore, it is desired the SCLK input be stable
prior to enabling the IR3531A voltage regulator.
TRACK FUNCTIONALITY
Both Rail outputs of the IR3531A can be independently
controlled through their respective TRACK inputs.
TRACK pins override the internal VDAC reference inputs
to the Error Amplifiers allowing users to control power
up and power down VR output voltage characteristics.
The IR3531A is fully soft-stop and pre-bias compatible.
The control loop is full synchronous during soft stop
events thereby preventing COUT capacitor discharge-
induced inductive kicks. The control system allows non-
synchronous buck operation once VO<=250mV ― this
Figure 6: TRACK Operation with Pre-Bias
16
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
Figure 7: TRACK Operation without Pre-Bias
allows outputs to return to their pre-biased operating
points if available.
allowing the MOSFET body diodes to conduct and dissipate
some of the stored inductor energy and also speed up the
inductor current slew rate by introducing a larger voltage
across the inductor. Body BrakingTM reduces the peak
overshoot of the converter.
The TRACK inputs have a typical 36mV offset from the
closed loop feedback operating point to ensure the error
amplifier is in an off state when TRACK=0V. Furthermore,
TRACK must exceed the respective VDAC by at least 100mV
to ensure VDAC has complete control of the Error Amplifier
as shown in Figures 6 and 7.
An error amplifier output voltage greater than the
common mode input range of the PWM comparator
results in 100% duty cycle regardless of the voltage of the
PWM ramp. The resulting PWM control loop is capable of
transitioning from 0% duty cycle to 100% duty cycle with
overlapping phases within a few tens of nanoseconds in
response to a load step decrease. Figure 8 on the next
page depicts PWM operating waveforms under various
conditions.
As a cautionary note the track input provides direct control
of the output PWM duty cycle. The presence of excessive
noise or glitches on TRACK when this input is active can
cause sudden increases in the PWM duty cycle (up to
100%), potentially causing damage to the power converter.
PWM CONTROL METHOD
BODY BRAKINGTM
The steady state control architecture utilized in the
IR3531A is feed-forward voltage mode control with trailing
edge modulation. A high-gain wide-bandwidth voltage type
error amplifier is used to achieve accurate voltage
regulation and ultra-fast transient response. Feed-forward
control is established by varying the PWM ramp slope
proportionally to the input voltage resulting in the error
amplifier operating point being independent of the input
voltage. The input voltage can change due to variations in
the silver box output voltage or due to the wire and
PCB-trace voltage drop related to changes in load current.
All PWM ramp slopes are calibrated at initial power-up.
The PWM pulse is terminated once the PWM ramp
exceeds the Error Amplifier output voltage.
In a conventional synchronous buck converter, the
minimum time required to reduce the current in the
inductor in response to a load-step decrease is:
L*(IMAX IMIN
)
TSLEW
VO
The slew rate of the inductor current can be significantly
increased by turning off the synchronous rectifier in
response to a load-step decrease. The switch node voltage
is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases
the voltage across the inductor from Vout to Vout +
VBODYDIODE. The minimum time required to reduce the
current in the inductor in response to a load transient
decrease is now:
Under dynamic load transitions, the IR3531A utilizes our
patented Body BrakingTM algorithm allows all low-side
MOSFETs to be turned off during a load relaxation event
17
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
Since the voltage drop in the body diode is often
comparable to the output voltage, the inductor current
slew rate can be increased significantly. This patented
L *(IMAX IMIN
VO VBODYDIODE
)
TSLEW
PHASE CLOCK
PULSE
EAIN
PWMRMP
FLOOR
GATEH
GATEL
STEADY-STATE
OPERATION
DUTY CYCLE INCREASE
DUE TO LOAD INCREASE
DUTY CYCLE DECREASE
DUE TO V12V INCREASE
(FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OT FAULT
(VCC UV, OCP, VID FAULT)
STEADY-STATE
OPERATION
Figure 8: PWM Operating Waveforms
technique is referred to as “body braking” and is
accomplished through the “body braking comparator.”
If the error amplifier’s output voltage drops below VDAC,
this comparator turns off the low-side gate driver, enabling
the bottom FET body diode to take over. There is 100mV
upslope and 200mV down slope hysteresis for the body
braking comparator.
LOSSLESS AVERAGE INDUCTOR
CURRENT SENSING
Inductor current can be sensed by connecting a series
resistor and a capacitor network in parallel with the
inductor and measuring the voltage across the capacitor,
as shown in Figure 8. The equation of the sensing network
is:
Figure 9: Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus
high-side or low-side sensing is that actual output current
being delivered to the load is obtained rather than peak
or sampled information about the switch currents.
The output voltage can be positioned to meet a load line
based on real-time information. Except for a sense resistor
in series with the inductor, this is the only sense method
that can support a single cycle transient response.
Other methods provide no information during either load
increase (low-side sensing) or load decrease (high-side
sensing).
1
RL sL
1 sRCSCCS
vC (s) vL(s)
iL(s)
1 sRCSCCS
Usually the resistor Rcs and capacitor Ccs are chosen, such
that, the time constant of Rcs and Ccs equals the time
constant of the inductor, which is the inductance L over
the inductor DCR RL. If the two time constants match, the
voltage across Ccs is proportional to the current through L,
and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the
time constants does not affect the measurement of
inductor DC current, but affects the AC component of the
inductor current.
An additional problem associated with peak or valley
current mode control for voltage positioning is that they
suffer from peak-to-average errors. These errors will
appear in many ways but one example is the effect of
frequency variation. If the frequency of a particular unit is
10% low, the peak-to-peak inductor current will be 10%
larger and the output impedance of the converter will drop
18
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
by about 10%. Variations in inductance, current sense
amplifier bandwidth, PWM prop delay, any added slope
compensation, input voltage, and output voltage are all
additional sources of peak-to-average errors.
and cause OVP conditions. The phase firing order of the
multiphase system is continually being re-assessed and
adjusted if required on a cycle-by-cycle basis to prevent
instantaneous phase currents from deviating from each
other. This also improves transient response by ensuring
all phase currents track each other within a few switching
cycles. Individual switch nodes will appear to be variable
frequency however input and output ripple are unaffected
by the varying phase firing order.
CURRENT SENSE AMPLIFIER
A high speed differential current sense amplifier is located
in our driver ICs, as shown in Figure 9. Its gain is nominally
32.5 over the entire temperature operating range
therefore the 3850 ppm/ºC inductor DCR temperature
coefficient should be compensated in the voltage loop
feedback path. This can be accurately compensated by
using a linearized Negative TC resistor network where
the NTC can be located near the output inductors. The
resulting temperature compensated current information
is used by the control IC for voltage positioning and current
reporting, and over current limit protection.
SVID CONTROL
The SVID bus allows the processor to communicate with
the IR3531A. The processor can program the voltage
regulator output voltage and monitor telemetry data the
IR3531A offers such as temperature and both rail currents.
VCLK, VDIO and ALERT# communication lines are designed
for external 50-75 ohm pull up resistors to 1.0-1.2V bias
voltage and should not be floated. Note that ALERT# may
assert twice for VID transitions of 2 VID steps or less.
Addressing is programmed as a percentage of VDAC as
shown by selecting the appropriate ADDR pin resistor
divider combination and supports up to 14 addresses and
2 all call addresses (refer to Table 1). Table 2 provides a list
of supported SVID commands. Table 3 provides a list of
supported required SVID registers. The SVID communicates
VID codes listed in Table 4a and 4b to program the VDAC
set point.
The input offset of this amplifier is calibrated to within
+/- 450µV (6 sigma limits) with a 200uV typical LSB
calibration bit. This calibration routine is continuous and
occurs at every 56 PWM cycles.
The current sense amplifier can accept positive differential
input up to 50mV and negative up to -10mV before
clipping. The output of the current sense amplifier is
summed with the VDAC voltage and is returned to the
control IC through the IIN pin. The IIN pins in the control IC
are internally tied together through 3 KOhm resistors to
produce a voltage representative of the average phase
inductor current.
The IR3531A can accept changes in the VID code and will
vary the VDAC voltage accordingly. The slew rate of the
voltage at the VDAC pin can be set by the appropriate
command. The slew rate is internally programmed and no
external pins or components are necessary. Digital VID
transitions result in a smooth analog transition of the
VDAC voltage and converter output voltage minimizing
inrush currents, false over current conditions and
overshoot of the output voltage.
AVERAGE CURRENT SHARE LOOP
A current sharing loop is also incorporated in the IR3531A
to ensure balance between the multiphase buck power
stages. Poor current sharing can hamper transient
response and degrade overall system efficiency.
The current information of each phase is compared
against the average phase current through a Share Adjust
Amplifier which then manipulates the respective PWM
ramp start voltage to add or subtract PWM output
duty cycle. The current share amplifier is internally
compensated such that the crossover frequency of the
current share loop is much slower than that of the voltage
loop and the two loops do not interact.
The VID data from the SVID bus is stored in registers and
is sent to the Digital-to-Analog Converter (DAC), whose
output is sent to the VDAC buffer amplifier. The output of
the buffer amplifier is the VDAC pin. To achieve optimal
system setpoint voltage accuracy, first all contributing
offsets of the IR3531A are independently trimmed and
lastly the internal VDAC reference is trimmed to take into
account all sum of all the offset components. Note that the
resulting final VDAC voltage will have a slightly wider
tolerance as it is compensating for the sum of all other
offset components. This results in an overall 0.5% system
set-point accuracy for VID range between 1V to 1.52V.
INSTANTANEOUS CURRENT BALANCE
A form of coarse current sharing is also incorporated into
the IR3531A to protect against Synchronized High Load
Repetition Rate transients which can saturate inductors
19
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
TABLE 1: ADDR A/D VOLTAGE PROGRAMMING (AS % OF VDAC)
TABLE 3: SUPPORTED REGISTER
Register
% of VDAC
6.25%
Address Name
A0/A1
Description
VendorID
Identifies the VR vendor
21.88%
34.38%
46.88%
59.38%
71.88%
84.38%
A2/A3
ProductID
Identifies the product model
Identifies the product revision
Identifies the version of SVID protocol
A4/A5
ProductRev
SVID Protocol ID
VR Capability
A6/A7
A8/A9
Communicates functions the IR3531A
supports
A10/A11
A12/A13
Status1 Reg
Status2 Reg
Temp Zone
Stores VR status data
Stores SVID bus errors
Note: A14/A15 are reserved all-call address.
Temperature zone from Rail0 sensor
Stores output current for Rail0/Rail1
Output Current
SVID COMMAND STRUCTURE
Status2_last_read Stores previous data of status 2
SVID protocol has two main command groups: the Get and
Set commands. The Get commands retrieve data from the
voltage regulator controller, while the Set commands
make changes to voltage regulator operating points and
power states.
ICC Max
Programs the maximum supported
output current
Temp Max
Programs maximum operating
temperature
SR-fast
Stores the fast slew rate value
Stores the slow slew rate value
Overrides the default Vboot value
When the processor (master) issues a Get command, it
transmits the intended controller address and the address
of the register it wants to read. The addressed controller
acknowledges the command and returns the requested
data. Similarly, when the processor issues a Set command,
it transmits the intended controller address and the data it
wants to insert. The only exception is the SetRegADR
command which is used to declare the register address
that SetRegDAT will alter. The controller acknowledges
these commands. Parity checking is not enforced on
SetRegADR/SetRegDAT.
SR-slow
Vboot
Vout Max
Programs the maximum supported
operational Vout
VID Setting
Register contains the current VID setting
Register contains the current power state
Allows margining around the VID setpoint
Power State
VID Offset1
Multi VR Config
Configures other VR-s on the same SVID
bus
SetRegADR
Scratch pad register for temporary
storage of the SetRegADR pointer register
TABLE 2: SUPPORTED COMMAND
Command
SetVIDfast
Description
Note 1: VID Offset commands that attempt to push the VID
above 1.52V or below 0V are not acknowledged.
Slews VOUT to a new Programmed setpoint at
20mV/usec
SetVIDslow
Slews VOUT to a new Programmed setpoint at
5mV/usec
SetPS
Sets power state
SetRegADR
Declares the address of the register to be
written to
SetRegDAT
GetReg
Writes data to the SetRegADR declared register
Read data of a specified register
TestMode
Test mode is used for final test trimming of the
IR3531A and is not available to users.
Note: SetVID Decay is not supported.
20
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
TABLE 4: VID VALUES
VID7:VID0
(Hex)
VID7:VID0
VID7:VID0
(Hex)
VID7:VID0
(Bin)
VID7:VID0
(Hex)
VID7:VID0
Voltage
Voltage
Voltage
(Bin)
(Bin)
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
0
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111
00111000
00111001
00111010
00111011
00111100
00111101
00111110
00111111
01000000
01000001
01000010
01000011
01000100
01000101
01000110
0.435
0.440
0.445
0.450
0.455
0.460
0.465
0.470
0.475
0.480
0.485
0.490
0.495
0.500
0.505
0.510
0.515
0.520
0.525
0.530
0.535
0.540
0.545
0.550
0.555
0.560
0.565
0.570
0.575
0.580
0.585
0.590
0.595
01001100
01001101
01001110
01001111
01010000
01010001
01010010
01010011
01010100
01010101
01010110
01010111
01011000
01011001
01011010
01011011
01011100
01011101
01011110
01011111
01100000
01100001
01100010
01100011
01100100
01100101
01100110
01100111
01101000
01101001
01101010
01101011
01101100
0.625
0.630
0.635
0.640
0.645
0.650
0.655
0.660
0.665
0.670
0.675
0.680
0.685
0.690
0.695
0.700
0.705
0.710
0.715
0.720
0.725
0.730
0.735
0.740
0.745
0.750
0.755
0.760
0.765
0.770
0.775
0.780
0.785
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
0.250
0.255
0.260
0.265
0.270
0.275
0.280
0.285
0.290
0.295
0.300
0.305
0.310
0.315
0.320
0.325
0.330
0.335
0.340
0.345
0.350
0.355
0.360
0.365
0.370
0.375
0.380
0.385
0.390
0.395
0.400
0.405
21
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
VID7:VID0
(Hex)
VID7:VID0
(Bin)
VID7:VID0
(Hex)
VID7:VID0
(Bin)
VID7:VID0
(Hex)
VID7:VID0
Voltage
Voltage
Voltage
(Bin)
00100001
00100010
00100011
00100100
00100101
01110010
01110011
01110100
01110101
01110110
01110111
01111000
01111001
01111010
01111011
01111100
01111101
01111110
01111111
10000000
10000001
10000010
10000011
10000100
10000101
10000110
10000111
10001000
10001001
10001010
10001011
10001100
10001101
10001110
0.410
0.415
0.420
0.425
0.430
0.815
0.820
0.825
0.830
0.835
0.840
0.845
0.850
0.855
0.860
0.865
0.870
0.875
0.880
0.885
0.890
0.895
0.900
0.905
0.910
0.915
0.920
0.925
0.930
0.935
0.940
0.945
0.950
0.955
01000111
01001000
01001001
01001010
01001011
10011001
10011010
10011011
10011100
10011101
10011110
10011111
10100000
10100001
10100010
10100011
10100100
10100101
10100110
10100111
10101000
10101001
10101010
10101011
10101100
10101101
10101110
10101111
10110000
10110001
10110010
10110011
10110100
10110101
0.600
0.605
0.610
0.615
0.620
1.010
1.015
1.020
1.025
1.030
1.035
1.040
1.045
1.050
1.055
1.060
1.065
1.070
1.075
1.080
1.085
1.090
1.095
1.100
1.105
1.110
1.115
1.120
1.125
1.130
1.135
1.140
1.145
1.150
01101101
01101110
01101111
01110000
01110001
11000000
11000001
11000010
11000011
11000100
11000101
11000110
11000111
11001000
11001001
11001010
11001011
11001100
11001101
11001110
11001111
11010000
11010001
11010010
11010011
11010100
11010101
11010110
11010111
11011000
11011001
11011010
11011011
11011100
0.790
0.795
0.800
0.805
0.810
1.205
1.210
1.215
1.220
1.225
1.230
1.235
1.240
1.245
1.250
1.255
1.260
1.265
1.270
1.275
1.280
1.285
1.290
1.295
1.300
1.305
1.310
1.315
1.320
1.325
1.330
1.335
1.340
1.345
21
22
23
24
25
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
47
48
49
4A
4B
99
9A
9B
9C
9D
9E
9F
6D
6E
6F
70
71
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
22
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
VID7:VID0
(Hex)
VID7:VID0
(Bin)
VID7:VID0
(Hex)
VID7:VID0
(Bin)
VID7:VID0
(Hex)
VID7:VID0
Voltage
Voltage
Voltage
(Bin)
10001111
10010000
10010001
10010010
10010011
10010100
10010101
10010110
10010111
10011000
11100111
11101000
11101001
11101010
11101011
11101100
11101101
11101110
11101111
0.960
0.965
0.970
0.975
0.980
0.985
0.990
0.995
1.000
1.005
1.400
1.405
1.410
1.415
1.420
1.425
1.430
1.435
1.440
10110110
10110111
10111000
10111001
10111010
10111011
10111100
10111101
10111110
10111111
11110000
11110001
11110010
11110011
11110100
11110101
11110110
11110111
11111000
1.155
1.160
1.165
1.170
1.175
1.180
1.185
1.190
1.195
1.200
1.445
1.450
1.455
1.460
1.465
1.470
1.475
1.480
1.485
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
F9
FA
FB
FC
FD
FE
FF
11011101
11011110
11011111
11100000
11100001
11100010
11100011
11100100
11100101
11100110
11111001
11111010
11111011
11111100
11111101
11111110
11111111
1.350
1.355
1.360
1.365
1.370
1.375
1.380
1.385
1.390
1.395
1.490
1.495
1.500
1.505
1.510
1.515
1.520
8F
90
91
92
93
94
95
96
97
98
E7
E8
E9
EA
EB
EC
ED
EE
EF
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
F0
F1
F2
F3
F4
F5
F6
F7
F8
23
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
The VDRP pin is connected to the FB pin through the
resistor RDRP. As load current increases, the VDRP voltage
increases proportionally. Since the error amplifier will
force the loop to maintain FB to be equal to the VDAC
reference voltage, the additional RDRP current has to flow
through the RFB resistor which introduces an offset
voltage that is proportional to the load current. The RFB
current is equal to (VDRP-VDAC)/RDRP. The positioning
voltage can be programmed by the resistors RDRP and RFB
so that the droop impedance produces the desired
converter output impedance. The offset and slope of the
converter output impedance are referenced to and
therefore independent of the VDAC voltage.
ADAPTIVE VOLTAGE POSITIONING
Adaptive Voltage Positioning (AVP) is a control algorithm
where the output voltage is reduced as the load current
increases. This may also be referred to as VR output
impedance, Voltage Droop or Load Line. AVP is
implemented to reduce the amount of bulk capacitance
for a given load transient and regulation window and
reduces power dissipation at heavy load. The IR3531A
implementation of voltage positioning for Rail0 and Rail1
is shown in Figure 10. The output voltage is set by the
VDAC or TRACK reference voltage at the positive input of
the error amplifier.
INDUCTOR DCR TEMPERATURE COMPENSATION
CURRENT MONITOR (IMON)
The load current information for all the phases is fed back
to the control IC through the Driver IC IOUT pins where
this information is averaged and buffered to the Thermal
Compensation Amplifier. The gain of the Thermal
Compensation Amplifier is modified by temperature by
introducing a negative temperature coefficient (NTC)
thermistor (RTHERM1) and linearizing resistor network
(RTCMP1 and 2) connected between the VN and VDRP
pins. The thermistor should be placed close to the power
stage to accurately sense the thermal performance of the
inductor DCR.
The control IC generates a current monitor signal IMON
using the VDRP voltage and the VDAC reference, also
shown in Figure 10. The voltage at this pin reports the
average load current information referenced to LGND.
The slope of the IMON signal with respect to the load
current can be adjusted with the resistors RTCMP2 and
RTCMP3. The IMON signal is clamped at 1.09V in order to
facilitate direct interfacing with the master.
Figure 10: Adaptive voltage positioning with thermal compensation
24
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
REMOTE VOLTAGE SENSING
PROTECTION
The remote sense differential amplifier in the IR3531A is a
high speed, low input offset unity gain buffer that provides
accurate voltage sensing and fast transient response.
VOSEN+ and VOSEN- are the remote-sensing Kelvin
connections that are tied directly to the load. Internal
resistors to the differential amplifier produce VOSEN+ and
VOSEN- bias currents of up to 50µA maximum and limits
the size series resistors for acceptable regulation of the
output voltage. Open sense lead detection is also included
in this amplifier and is discussed further in the fault
section.
The Fault Table below describes the different faults that
can occur and how the IR3531A reacts to protect the
supply and the load from possible damage. The fault types
that can occur are listed in row 1. Row 2 has the method
that a fault is cleared. The first 3 faults are latched in the
UV fault latch and the VCC power has to be recycled to
clear. An over voltage fault can be cleared by recycling
either VCC or the Enable signal. The rest of the faults
(except for UVLO VOUT and SVID faults) are temporarily
latched in the SS fault latch until the fault condition clears.
Most faults disable the error amplifier (except for SVID and
VOUT UVLO). Most faults (except SVID) flag VRRDY. VRRDY
returns to active high when all faults are cleared. The delay
row shows reaction time after detecting a fault condition.
Delays are provided to minimize the possibility of nuisance
faults. The table applies for both rails of the IC.
PHASE SHEDDING
IR3531A allows phases to be disabled through the
PHSSHED pin. Shedding can be performed either statically
at power up or can be exercised dynamically during normal
operation. One, two or three phases can be disabled to
help enhance light load efficiency. The internal clock
frequency is automatically adjusted to achieve graceful
transition. Phase shedding is not recommended if an
external synchronization clock is being applied.
TABLE 5: PHASE SHEDDING PROGRAMMING THRESHOLDS
Threshold
PHSSHED < 0.25VCC
Action
No Phases Shed
Shed 1 Phase
0.25VCC < PHSSHED < 0.5VCC
0.5VCC < PHSSHED < 0.75VCC
PHSSHED < 0.75VCC
Shed 2 Phases
Shed 3 Phases
POWER STATES AND HIGH EFFICIENCY MODE
AT LOW LOADS
System processors can request the VR to enter higher
efficiency Power Savings modes. The IR3531A enters single
phase operation when a PS1 command is issued from
the processor. This mode is intended for loads less than
20A. There is an 8 switching cycle delay before the VR
transitions from PS0 to PS1. PS2 mode is not supported.
PLATFORM TEST MODE
Platform test mode allows users to test the VR solution
when the default VBOOT voltage programmed on IR3531A
is 0V and there is no communication capability to send
commands. The address pin needs to be pulled up to 3.3V
for IR3531A to go into platform test mode. IR3531A will
boot to 1V in this mode.
25
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
TABLE 6: FAULT OPERATION
FAULT TYPE
Open
Control Loop
Open
Sense Line
Over
Voltage
Over
Current
Enable
Low
V12V
UVLO
VCC
UVLO
VO
UVLO
SVID
Fault Clearing
Method
Recycle VCC or Enable
Yes
Resume Normal Operation when Condition Clears
Error Amp
Disabled
No
Yes, after SoftStop
No
ROSC/OVP
drives high
No
Yes
No
until OV clears
VRRDY Low?
Yes
No
Yes
VDAC
Response?
No
Change
Transition to 250mV and holds until fault is cleared
If fault occurs
on Rail0 will
Rail1 continue
to operate?
If fault occurs
on Rail1 will
Rail0 continue
to operate?
No
No
No
No
No
No
No
No
No
No
Yes
Yes
No
No
No
No
No
No
No
Yes
Yes
No
No
4 SVID
Clock
Cycles to
send NAK
250 ns
Blank
Time
8 PWM
Cycles
Delay
256µs
ENABLE INPUT
OPEN REMOTE SENSE LINE PROTECTION
The Enable pin has a 0.6V falling threshold that sets the
Fault Latch, a 650mV rising threshold that clears the fault
latch and has a 250ns filter to prevent chatter due to
system noise. When clearing an OC fault latch, it is
recommended to allow sufficient thermal relaxation time
prior to repeat re-enabling to ensure the converter does
not thermally run away. Approximately 4ms thermal
relaxation is recommended for most designs.
The VOSEN+ and VOSEN- remote sense line impedances
are checked prior to power up to verify they are connected
to low impedances. If high impedance is detected, an Open
Sense Line fault is latched and requires VCC to be recycled
to clear. During normal operation, the remote sense amp
operating environment is monitored to ensure the remote
sense lines are connected. Again, if an abnormal mode is
detected, the sense line impedances are again checked.
If high impedance is detected, an Open Sense Line fault is
latched and requires VCC to be recycled to clear.
OPEN VOLTAGE LOOP DETECTION
If for some reason the control loop fails during operation,
the system protects itself by latching an open loop
fault that requires VCC recycling to clear. Detection is
performed by monitoring the output of the error amplifier.
The fault is latched if EAOUT operates above VCC-1.08V for
8 switching cycles indicating the control loop is broken.
V12V AND VCC UNDER VOLTAGE LOCKOUT
(UVLO)
The IR3531A monitors the converter input voltage rails
(V12V and VCC) and issues a UVLO fault if either voltage is
below the desired operating range. The maximum power
up clear thresholds are 10.2V for V12V and 6.2V for VCC.
26
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
Scenario 2: VRRDY is still gated by VDAC reaching
VBOOT since VO is correctly following TRACK.
VOLTAGE REGULATOR READY (VRRDY, VRRDY1)
The VRRDY pins are an open-collector outputs which
require external pull-ups. The pull down device is design to
achieve 400mV while sinking 4mA and can sustain voltages
up to 7.5V. A high VRRDY indicates the output voltage is in
regulation and there are no system faults in the IR3531A.
VRRDY monitors the status of the output voltage with
respect to either the TRACK pin or VDAC.
Scenario 3: VO is unresponsive in this scenario.
VRRDY will flag high as long as VO is within 200mV
of TRACK. Once TRACK exceeds VO by 200mV, VRRDY
will flag low indicating a regulation fault.
Scenario 4: TRACK-VO exceeds 200mV prior to VDAC
reaching BOOT resulting in VRRDY being consistently
held low.
During power up after ENABLE is released, the output
voltage will be monitored with respect to TRACK-200mV.
VRRDY is held low until the internal VDAC reaches its boot
voltage of 1.5V which takes 300usec due to the 5mV/usec
VDAC slew rate. VRRDY is then allowed to go high if VO is
within TRACK -200mV. This is true even if TRACK=0V.
VRRDY will be held low if VO is less than TRACK-200mV.
Scenario 5: A regulation failure occurs during
(or even post) power up resulting in TRACK-VO
exceeds the 200mV UVLO threshold.
The VO UVLO threshold returns to VDAC-290mV once
a valid SVID command slews VDAC and VO regulates within
10mV of the final VDAC transition voltage. TRACK can then
be transitioned to a voltage greater than VO+200mV
without affecting VRRDY.
Figure 11 depicts various power-up scenarios:
Scenario 1: VRRDY is gated by VDAC reaching
VBOOT=1.5V. Track and the regulated output voltage
power up within 300µsec.
VDAC=1.5V
VDAC=1.5V
5mV/usec
5mV/usec
TRACK
VO
TRACK
VRRDY
VO
VRRDY=0
Scenario 1. TRACK VDAC Gates VRRDY
Scenario 4. Unresponsive VO prior to VDAC=1.5V
VDAC=1.5V
VDAC=1.5V
5mV/usec
5mV/usec
TRACK
VO
TRACK
200mV
VO
VRRDY
VRRDY
Scenario 2. TRACK VDAC Gates VRRDY
Scenario 5. VO failure post VDAC=1.5V
VDAC=1.5V
5mV/usec
TRACK
200mV
VO
VRRDY
Scenario 3. Unresponsive VO post VDAC=1.5V
Figure 11 – VRRDY Power-up Scenarios
27
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
Figure 12 shows two different power-up responses where
Enable going high is gating the first VDAC slew and the
calibration routine is gating the second VDAC slew.
The default slew rate is 5mV/µsec. The control loop
ensures the regulator output voltage will track VDAC.
The soft start sequence finishes when VOUT is settled to
the VBOOT set point and VRRDY is asserted.
START-UP AND SHUT-DOWN SEQUENCE
The IR3531A has a programmable, digitally controlled soft-
start function to limit the surge current during the voltage
regulator start-up. The default boot voltage for Rail0 rail is
1.5V, for Rail1 it is 1.5V. Figure 11 depicts an Enable gated
power-up and V12V UVLO shutdown followed by a V12V
UVLO gated power up and an Enable low shutdown.
The IR3531A has soft stop capability which allows the
voltage regulator to power down in a controlled fashion
without producing negative undershoots resulting from
fast discharge of output capacitance. Pre-biased outputs
are also supported as shown in Figure 13.
The IR3531A requires less than 1ms to perform calibration
routines once V12V (VIN) UVLO is cleared. Note VDAC is
forced to 1.52V during calibration and A/D sampling and
settles to 250mV once calibration is complete.
V12V
UVLO Threshold
1.52VDuring Pin Program Sensing
1.52VDuring Pin Program Sensing
VDAC=0.9V
VDAC=0.9V
250mV
0V
ENABLE
tmax=(1.52-0.25)/5mV=254usec
Allow 1msec after VIN UVLO to
allow A/D pin sensing and
internal calibration routines to occur
before attempting power-up.
Figure 12: V12V Power and Enable Cycling
TRACK
VOUT=PREBIAS
VOUT= VDAC
VOUT=>PREBIAS
VDAC
250mV
VDAC
VRRDY
DIODE EMULATION
NOT ALLOWED
DIODE EMULATION
NOT ALLOWED
ENABLE
Figure 13: Enable Power Cycling Under Pre-bias
28
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
ENABLE or VCC UVLO cycling clears the OCP fault latch.
It is recommended to allow sufficient thermal relaxation
time prior to repeat re-enabling to ensure the converter
does not thermally run away. Approximately 4ms thermal
relaxation is recommended for most designs. If ENABLE
is cycled during this relaxation period, the converter will
wait until the internal VDAC has returned to 0V prior to
attempting another power up. The internal VDAC slews at
5mV/µsec and therefore the rise and fall slew durations
are 300µsec for a BOOT of 1.5V. The VDAC pin slews down
to 250mV and does not slew to 0V. This is done to ensure
the current reporting system has enough headroom to
properly operate.
OVER-CURRENT CONTROL
Over current protection (OCP) is a latched event that
requires VCC UVLO or ENABLE cycling to clear. OCP is
performed internally by comparing the VDRP pin voltage
against an OC offset voltage that is added to the respective
VDAC pin voltage. This OC offset voltage is adjusted to
match the active number of phases since VDRP represents
average per-phase current. This ensures that the current
limit is correctly adjusted during phase shedding operation.
An over current condition is registered if the VDRP pin
voltage, which is proportional to the average current plus
VDAC voltage, exceeds the VDAC+ OC offset voltage.
Figure 14 shows the over-current control with delay during
various soft start events. A fixed 256μs OC delay is needed
to protect against nuisance over-current conditions which
can occur as part of normal operation or due to inrush
currents.
If an over-current occurs during soft start, the control IC
will not disable the voltage regulator until the over current
delay time has elapsed. If the over-current condition
persists after delay time is reached, the fault latch will be
set pulling the error amplifier’s output low and inhibiting
switching in the driver ICs.
ENABLE Cycle does not have an effect on VOUT until
VDAC has reset to 0V. User must ensure proper
thermal relaxation has occurred prior to re-enabling.
ENABLE Cycle after a
recommended 4ms
relaxation timeout
ENABLE
VDAC controls VOUT power up
when TRACK remains high
Recommend ~4ms
Relaxation Delay
VDAC Pin
Internal VDAC
TRACK
VOUT
OCP Threshold
IOUT
256us OC Delay
VRRDY
VRRDY momentarily goes high once
VDAC reaches BOOT and then faults
once TRACK-VOUT exceeds 200mV.
VRRDY momentarily goes high once
VDAC reaches BOOT and then faults
once TRACK-VOUT exceeds 200mV.
VRRDY remains low because TRACK-
VOUT exceeds 200mV prior to VDAC
reaching BOOT.
Figure 14: Over Current Waveforms
29
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
ICCP (ICC MAX) PROGRAMMING
TEMPERATURE TELEMETRY
SVID register ICC MAX contains information on the
maximum allowable current supported by the voltage
regulator solution and can be equivalent to the CPU’s
ICC_MAX. The CPU reads this register for platform
compatibility during boot and uses this data in conjunction
with the IOUT register for performance management.
This data is in an 8-bit binary formant equivalent to amps,
i.e. 75A=4Bh.
The maximum temperature TMAX (22h) value is factory
programmed to 110C. This register contains the maximum
temperature the VR supports prior to issuing a thermal
alert or VR_Hot. The master reads this register and uses
this data in conjunction with the Temperature Zones for
performance management. Factory trim options are listed
in Table 8.
TABLE 8: TEMP MAX (PROGRAMMED AT FINAL TEST)
The voltage is programmed by an external resistor divider
string referenced to VDAC. Table 7 lists the available
current thresholds
Binary Code Temperature
Binary Code
100
Temperature
106 Deg C
110 Deg C
114 Deg C
118 Deg C
000
001
010
011
90 Deg C
94 Deg C
98 Deg C
102 Deg C
101
TABLE 7: ICCP (ICC MAX) A/D VOLTAGE PROGRAMMING
(AS % OF VDAC)
110
111
%VDAC
1.5
4.7
7.8
11
Binary Code
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Current Level
60A/25A
60A/35A
70A/25A
70A/35A
80A/25A
80A/35A
90A/25A
90A/35A
THERMAL MONITORING (VRHOT#)
The IR3531A provides two methods of thermal monitoring:
a VRHOT# pin which flags an over temperature event and
temperature telemetry is available through the SVID bus
and the Temperature Zone register.
14
17.2
20.3
23.4
26.5
29.7
32.8
36
A thermal sense network which includes an NTC thermistor
provides board temperature information at TSENS pin
as shown in Figure 15. The thermistor is usually placed in
a temperature sensitive region of the converter and is
linearized by a resistor network. VRHOT# will be active
low once the voltage on TSENS crosses Zone 7, or 56.3%
of VDAC. VRHOT# will de-assert once TSENS falls below
Zone 5. The VRHOT# pin is an open-collector output and
should be pulled up to a voltage source through a resistor.
100A/25A
100A/35A
110A/25A
110A/35A
120A/25A
120A/35A
130A/25A
130A/35A
140A/25A
140A/35A
150A/25A
150A/35A
160A/25A
160A/35A
170A/25A
170A/35A
180A/25A
180A/35A
190A/25A
190A/35A
200A/25A
200A/35A
225A/25A
225A/35A
39
42.2
45.3
48.4
51.5
54.7
57.8
61
VDAC
RTHERM2
Control IC
RHOTSET1
VRHOT#
64
TSENS
+
-
67.2
70.3
73.4
76.6
79.7
82.8
86
RHOTSET3
Zone 5: 53.1%
Zone 7: 56.3%
VDAC
Figure 15: Over Temperature Detection Circuit
The IR3531A compares the TSENS pin voltage against fixed
percentages of VDAC thresholds as indicated in Table 9.
The user can program the external TSENS network to
achieve a desired offset and slope to associate a zone
(stored in register 12h) with a desired temperature.
89
92.2
95.3
98.4
30
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
Zones correspond to the bit number of this 8-bit register,
i.e. Zone 0=bit 0 and Zone 3=bit3 and therefore register
12h behaves like a thermometer. Notice that the zones 1
through 7 thresholds are equally spaced (~1.6% between
thresholds) and the separation between Zone0 and Zone1
is approximately double. Since these zone thresholds are
fixed and equally separated, the respective zone
indicated in Table 9. These warning flags may be used by
the system to reduce the load, increase airflow, and
prevent the system from entering thermal shutdown.
The VRHOT# pin is asserted as zones 6 and 7 are crossed
and can be used as a thermal shutdown flag.
TMAX is merely a reference point to communicate with
downstream system monitors what temperature a zone
equates to. For example, the TMAX register is defaulted in
the IR3531A as 110°C. The micro processor can perform a
GetReg on TMAX and is now able to associate a Zone 4
declaration by the IR3531A to equate to 100.1°C
temperature values will also be equally separated for a
TSENS voltage which has a linear slope vs. temperature.
The SVID status register bit#1 and the ALERT# serve as
thermal warning flags when zones 5 and 6 are crossed as
TABLE 9: TEMPERATURE ZONES
Temperature Zone
Zone 0
TSENS Threshold % VDAC
% of TMAX
75%
Degrees C based on 110°C TMAX
43.8%
46.9%
48.4%
50%
82.5C
90.2
93.5
96.8
Zone 1
82%
Zone 2
85%
Zone 3
88%
100.1 Falling,
Status bit 1 de-asserted, ALERT#.
Zone 4
Zone 5
51.6%
53.1%
91%
94%
103.4 Falling, VRHOT#
de-asserted
106.7 Rising,
Status bit 1 asserted, ALERT#.
Zone 6
Zone 7
54.7%
56.3%
97%
100%
110 Rising, VRHOT# asserted
overrides the normal PWM operation and will regulate the
output voltage by modulating the low side MOSFET within
approximately 150ns to prevent the FB pin from exceeding
the OVP threshold. The OVP fault condition can only be
cleared by cycling VCC UVLO or ENABLE.
OVER VOLTAGE PROTECTION (OVP)
The IR3531A offers multilevel output over-voltage
protection to ensure no conflicts occur during pre-biased
conditioned power-up or no/light load soft stop. OVP is
sensed through the FB which allows users to externally use
FB resistor dividers if output voltages greater than 1.52V
are desired. The OVP threshold is set to 1.65V during
power up until VR Settled is reached, then the threshold
is reduced to VDAC+130mV. This OVP threshold is
maintained during normal operation and remains until
VO, the output of the remote sense amplifier, reaches
250mV with respect to ground. This ensures OVP
protection during soft stop events or down tracking
events. The OVP threshold then returns to 1.65V on the
FB pin to allow pre-bias startup.
OV
VDAC + 130mV
THRESHOLD
VDAC + 130mV
VDAC
NORMAL
OPERATION
NORMAL
OPERATION
VID DOWN
VID LOW
VID UP
Figure 16: Over Voltage Protection during SETVID Fast/Slow
IR3531A drives the ROSC/OVP pin above V(VCC)–1V to
indicate an over voltage event has occurred. This ROSC/
OVP flag can be used by the system designer to shut the
input if desired.
The over voltage condition also sets the over voltage fault
latch which ensures the voltage regulator is off. OVP
31
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
%VDAC
1
DESIGN PROCEDURES
100
RICCP1
*100* RICCP2
%VDAC
IR3531A EXTERNAL COMPONENTS
where, %VDAC is the desired percentage of VDAC found in
Table 7.
Switching Frequency Setting
Use the SCLK input to set PWM frequency. ROSC should
be present, and selected for the per phase switching
frequency in use. The chart below shows the relationship
between the per-phase switching frequency and the ROSC
value.
PHASE SHEDDING IMPLEMENTATION CIRCUITS
The following is a proposed circuit to implement phase
shedding. Two signals (S1 and S2) drive logic level
MOSFETs to produce a four level PHSSHED signal.
The operation is described in Table 6.
Figure 17: RROSC vs. Per-phase Switching Frequency
Figure 18: Phase Shedding Implementation
TABLE 10: PHASE SHEDDING CONTROL
ADDRESS AND PHASE NUMBER PROGRAMMING
RESISTORS RADDR1 AND RADDR2
The ADDR pin allows for the selection of the SVID address
for Rail0 and Rail1. Choose RADDR2 and apply the
following equation to determine RADDR1.
S1
0
S2
0
V(PHSSHED)
VCC
Phases
Drop 3 Phases
Drop 2 Phases
Drop 1 Phases
Drop 0 Phases
0
1
0.625* VCC
0.31* VCC
0V
%VDAC
1
1
0
100
RADDR1
*100* RADDR2
1
1
%VDAC
where, %VDAC is the desired percentage of VDAC found
in Table 1.
IMON AND IMON1 CAPACITORS
Use 100nF for CIMON and CIMON1 to provide an
approximate 1ms filtered time constant for current
reporting data.
ICCP PROGRAMMING RESISTORS
RICCP1 AND RICCP2
The ICCP programming resistors are used to program the
maximum currents Rail0 and Rail1 can support. Choose
RICCP2 and follow the equation below to calculate RICCP1.
VCC BIAS REGULATOR POWER STAGE
COMPONENTS
Use a 10 µH inductor with a current rating no less than 2 A.
Use a Schottky diode with operating current of 1 A or
higher and capable of withstanding 2 A for short periods of
time. A 10 µF capacitor ceramic capacitor rated for 16V is
recommended for charge storage and filtering.
32
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
The goal is to keep VDRP-VDAC at 900 mV for all
temperatures at the maximum current. Thus, the equation
below has to be satisfied.
TEMPERATURE SENSING
The TSENS pin is used to provide temperature information
of the voltage regulator by providing temperature zone
information to the microprocessor through the SVID.
This information is also used to flag VRHOT#. Temperature
is sensed via a linearized NTC resistor network. Tempera-
ture sensing and temperature zones are represented as
a percentage of the reference voltage VDAC as required by
the processor specification. A properly designed network
will get the TSENS voltage very close to the required target.
1% thermistors are highly recommended to achieve the
specified accuracy. Thermistor Beta is the biggest factor
in attaining accuracy. The target and TSENS voltages are
calculated from the equations below. The analysis is done
at VDAC of 1.5, because that is where the biggest error
occurs.
1
VDRP VDAC *(
3
DCR*Gcs
RTCeq
)*(1
)*Imax 900mV
n
RTCMP3
RTCMP2*(RTCMP1 RTHERM1)
RTCMP1 RTCMP2 RTHERM1
RTCeq
1
1
RTHERM1 RTHERM1ROOM *exp(beta(
))
T
TROOM
DCR DCRROOM *(13850e 6*(T TROOM ))
where RTHERM1ROOM is the thermistor value at room
temperature, beta is the thermistor coefficient, Tmax and
Tmin are the temperatures of the highest and lowest
temperature zone respectively, Gcs is the typical current
sense amplifier gain of 32.5, and DCRROOM is the inductor
series resistance at room temperature. The temperature
sensing components are chosen by finding an approximate
solution that results in VDRP-VDAC=900mV over the entire
temperature operating range. This can be done using an
optimization routine of your choice such as the IR3531A
excel design tool.
0.11*1.5
0.11*1.5
VTARGET
*T 0.453*1.5
*T min
T maxT min
T maxT min
RHOTSET3
VTSENSE
*1.5
RHOTSET3 RTSeq
(RHOTSET1 RTHERM 2)* RHOTSET2
RHOTSET1 RHOTSET2 RTHERM 2
RTSeq
1
1
RTHERM 2 RTHERM 2ROOM *exp(beta(
))
RAIL0 DROOP RESISTOR CALCULATION
T
TROOM
RDRP in combination with the feedback resistor RFB sets
the load line of Rail0. RFB is first chosen with a typical
suggested value of 2kOhm. The following equation
calculates RDRP.
where RTHERM2ROOM is the thermistor value at room
temperature, beta is the thermistor coefficient, Tmax and
Tmin are the temperatures of the highest and lowest
temperature zone respectively. The temperature sensing
components are chosen by finding an approximate
solution that brings the target and TSENS as close to each
other as possible. This can be done using an optimization
routine of your choice such as the IR3531A excel design
tool.
RFB * DCRROOM *Gcs
3* Ro *n
RTCeqROOM
RDRP
*(1
)
RTCMP3
where Ro is the load line, DCRROOM is the inductor series
resistance at room temperature, Gcs is the typical current
sense amplifier gain of 32.5, n is the number of phases and
RTCeqROOM is the same as RTCeq in section Rail0 Thermal
Compensation with RTHERM1 value at room temperature.
RAIL0 THERMAL COMPENSATION
Thermal compensation is required to counter the effect of
the inductor DCR positive temperature coefficient. Failure
to compensate results in large current reporting errors and
poor load line regulation. Thermal compensation is done
using a NTC thermistor and a linearizing resistor network.
A properly design network is necessary to achieve the
required accuracy targets. 1% thermistors are highly
recommended to achieve the specified accuracy.
Thermistor Beta is the biggest factor in attaining accuracy.
33
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
RAIL1 THERMAL COMPENSATION
COMPENSATION NETWORKS
IR3531A utilizes voltage mode control for small signal loop
regulation. The compensation scheme is a classic type 3
system consisting of components RFB(1), CFB(1), RCFB(1),
CEA(1), CCP(1) and RCP(1).
RSCALE1, RSCALE2, RSCALE3 and RTHERM3 are used to
provide current reporting thermal compensation for Rail1.
The purpose is to keep VDRP1-VDAC1 equal to 900mV for
all temperatures at the maximum load current. This is
expressed mathematically in the following equation.
The system dynamics can change significantly when
transitioning from 4 phases to 1 phase. Loop 0 has an
additional component, RPSC, that is inserted in the loop
when in PS1 mode (single phase) to optimize phase
margin. RPSC adds to RCP thereby reducing the system
bandwidth if desired. To disable this feature, place RPSC
as a zero ohm resistor. The IR3531A excel design tool can
be used to calculate an initial starting point.
VDRP1VDAC1 9 * DCR *Gcs * Imax *
(RSCALE1 RTHERM3) * RSCALE2
RSCALE1 RTHERM3 RSCALE3
(RSCALE1 RTHERM3) * RSCALE3
RSCALE2
RSCALE1 RTHERM3 RSCALE3
900mV
Note RDRP needs to be recalculated if RFB is changed.
where DCR and RTHERM3 are expressed in section Rail0
Thermal Compensation. Imax is the maximum current for
Rail1 and Gcs is the typical current sense amplifier gain of
32.5. The temperature sensing components are chosen by
finding an approximate solution that results in VDRP1-
VDAC1=900mV over the entire temperature operating
range. This can be done using an optimization routine of
your choice such as the IR3531A excel design tool.
LAYOUT GUIDELINES
VCC bias inductor LVCC must be close to SW pin.
VCC bias bulk cap COUTVCC must be located near
LVCC and connections for COUTVCC must be as
short as possible.
For both rails, all components connected to EA,
FB, VDRP, and VO pins must be located on the
same layer as the IR3531A as close to these pins
as possible.
RAIL 1 DROOP RESISTOR CALCULATION
RDRP1 in combination with the feedback resistor RFB1
sets the load line of Rail1. RFB1 is first chosen with a
typical suggested value of 2kOhm. The equation below
calculates RDRP1.
Insert 9 equally spaced connection vias to GND
tab of IR3531A.
V12V decoupling cap must be near pin of IR3531A
with GND connection as short as possible.
RFB1* DCRROOM *Gcs
RDRP1 9 *
*
Ro
(RSCALE1 RTHERM 3ROOM ) * RSCALE3
RSCALE1 RTHERM 3ROOM RSCALE3
RSCALE1 RTHERM 3ROOM ) * RSCALE3
ROSC must be located close to pin of IR3531A.
RTHERM1 and RTHERM3 must be located close to
inductor of associated voltage regulator. Locate
RTHERM2 to provide overall temperature reading
of the power converter.
RSCALE2
RSCALE1 RTHERM 3ROOM RSCALE3
where Ro is the load line, DCRROOM is the inductor series
resistance at room temperature, Gcs is the typical current
sense amplifier gain of 32.5, RTHERM3ROOM value at room
temperature.
34
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
METAL AND COMPONENT PLACEMENT
Center pad land length and width should be
equal to maximum part pad length and width.
However, the minimum metal to metal spacing
should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for
1 oz. Copper and ≥ 0.23mm for 3 oz. Copper)
Lead land width should be equal to nominal part
lead width. The minimum lead to lead spacing
should be ≥ 0.2mm to minimize prevent shorting.
Lead land length should be equal to maximum
part lead length + 0.3 mm outboard extension +
0.05mm inboard extension. The outboard
extension ensures a large and inspectable toe fillet,
and the inboard extension will accommodate any
part misalignment and ensure a fillet.
A single 0.30mm diameter via shall be placed in the
center of the pad land and connected to ground to
minimize the noise effect on the IC.
No PCB traces should routed nor Vias placed under
any of the 4 corners of the IC package. Doing so
can cause the IC to rise up from the PCB resulting
in poor solder joints to the IC leads.
Figure 19: Metal and Component Placement
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format.
35
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
SOLDER RESIST
The land pad should be Solder Mask Defined (SMD),
with a minimum overlap of the solder resist onto the
copper of 0.06mm to accommodate solder resist
miss-alignment. In 0.5mm pitch cases it is allowable
to have the solder resist opening for the land pad to
be smaller than the part pad.
The solder resist should be pulled away from
the metal lead lands by a minimum of 0.06mm.
The solder resist misalignment is a maximum
of 0.05mm and it is recommended that the lead
lands are all Non Solder Mask Defined (NSMD).
Therefore pulling the S/R 0.06mm will always
ensure NSMD pads.
Ensure that the solder resist in-between the lead
lands and the pad land is ≥ 0.15mm due to the high
aspect ratio of the solder resist strip separating the
lead lands from the pad land.
The minimum solder resist width is 0.13mm.
At the inside corner of the solder resist where
the lead land groups meet, it is recommended
to provide a fillet so a solder resist width of
≥ 0.17mm remains.
The vias in the large center pad should be tented or
plugged from bottom board side with solder resist.
Figure 20: Solder Resist
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format.
36
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
STENCIL DESIGN
The land pad aperture should be approximately 70%
area of solder on the center pad. If too much solder
is deposited on the center pad the part will float and
the lead lands will be open.
The stencil apertures for the lead lands should be
approximately 80% of the area of the lead lands.
Reducing the amount of solder deposited will
minimize the occurrence of lead shorts. Since for
0.5mm pitch devices the leads are only 0.25mm
wide, the stencil apertures should not be made
narrower; openings in stencils < 0.25mm wide
are difficult to maintain repeatable solder
release.
The maximum length and width of the land pad
stencil aperture should be equal to the solder resist
opening minus an annular 0.2mm pull back to
decrease the incidence of shorting the center land
to the lead lands when the part is pushed into the
solder paste.
The stencil lead land apertures should therefore
be shortened in length by 80% and centered on
the lead land.
.
Figure 21: Stencil Design
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format.
37
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
MARKING INFORMATION
3531A
?YWW?
XXXXX
SITE/DATE/MARKING CODE
LOT CODE
Figure 22: Package Marking
PACKAGE INFORMATION
48L MLPQ (7 x 7 mm Body) θJA = 23.5 ºC/W, θJC = 1 ºC/W
Figure 23: Package Dimensions
38
March 22, 2012 | FINAL | V1.11
IR3531A
4+1 Phase Dual Output Control IC
Data and specifications subject to change without notice.
This product will be designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com
39
March 22, 2012 | FINAL | V1.11
相关型号：
IR3536MTRPBF
Digital Multi-Phase Buck Controller 6-phase 8-phase dual output PWM Controller
INFINEON
IR3536MTYPBF
Digital Multi-Phase Buck Controller 6-phase 8-phase dual output PWM Controller
INFINEON
IR3536MXXYYTRP
Digital Multi-Phase Buck Controller 6-phase 8-phase dual output PWM Controller
INFINEON
©2020 ICPDF网 联系我们和版权申明