IR1175SS [INFINEON]
Buffer/Inverter Based MOSFET Driver, 2A, CMOS, PDSO20, MS-013AC, SOIC-20;
| 型号： | IR1175SS |
| 厂家： | 
Infineon |
| 描述： | Buffer/Inverter Based MOSFET Driver, 2A, CMOS, PDSO20, MS-013AC, SOIC-20 驱动器 |
| 文件： | 总9页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
Data Sheet PD 60178A
IR1175
Synchronous Rectifier Driver
Features
n Provides constant and proper gate drive to power
Product Summary
MOSFETs regardless of transformer output
V
dd
5Vdc
Minimizes loss due to power MOSFET body
n
drain diode conduction
Stand alone operation - no ties to primary side
I
2A/2A
2MHz
O+/-
n
n Schmitt trigger input with double pulse suppress-
ion allows operation in noisy environments
n High current drive capability - 2A
F
max
Max lead time
500nsec
n High speed operation - 2MHz
n Adaptable to multiple topologies (such as single-
ended forward, double-ended forward)
Package
Description
The IR1175 is a high speed CMOS controller designed
to drive N-channel power MOSFETs used as synchro-
nous rectifiers in high current, high frequency forward
converters with output voltages equal or below 5VDC.
Schmitt trigger inputs with double pulse suppression
allow the controller to operate in noisy environments.
The circuit does not require any ties to the primary
side and derives its operating power directly from
the secondary. The circuit functions by anticipating
transformer output transitions, then turns the power
MOSFETs on or off before the transitions of the trans-
former to minimize body drain diode conduction and
reduce associated losses. Turn on/off lead time can
be adjusted to accommodate a variety of power
MOSFET sizes and circuit conditions. The IR1175 also
provides gate drive overlap/dead-time control via
external components to further minimize diode con-
duction by nulling effects of secondary loop and de-
vice package inductance.
20 Lead Surface Mount (SSOP-20)
ADVANCE INFORMATION
IR1175
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur.
Symbol
Definition
Min.
—
Max.
7
Units
VDC
mADC
mW
°C/W
°C/W
°C
V
Supply voltage
dd
I
Input clamp current
—
+/- 10
400
28.5
90.5
150
150
300
in
P
Power dissipation (SSOP-20)
Thermal resistance (SSOP-20) junction-to-case
Thermal resistance (SSOP-20) junction-to-ambient
Junction temperature
—
D
Rth
Rth
—
JC
—
JA
T
—
J
T
Storage temperature
-55
—
°C
S
L
T
Lead temperature (soldering, 10 seconds)
°C
Recommended Operating Conditions
Symbol
Definition
Min.
—
Typ.
Max.
—
Units
VDC
°C
Vdd
Supply voltage operating range
Ambient temperature
5
—
T
A
-40
250
—
85
Freq
Rbias
UV
Operating frequency
—
500
—
KHz
KW
Required bias resistor (+/- 1%)
Voltage at UVSET pin
69.8
—
1.75
—
2.25
5.6
22
VDC
VDC
pF
Xin
Maximum voltage at X1 and X2 inputs
Capacitance at pins DTIN1 and DTIN2
Loop filter bypass capacitor
—
Cd1/Cd2
Cf
—
—
470
—
—
KW
www.irf.com
2
ADVANCE INFORMATION
IR1175
Dynamic Electrical Characteristics
Vdd=5V, T = 25oC, Rbias = 69.8K unless otherwise specified.
A
Symbol
Vdd
Definition
Min.
4.0
—
Typ.
—
Max.
Units
VDC
mADC
KHz
V
Supply voltage operating range
Vdd quiescent current (Vin=0 or 5V, Iout=0)
Operating frequency
5.5
Iqdd
3
5
Freq
100
1.10
0.8
—
—
2000
1.4
1.1
—
UVSET+
UVSET-
Vxth+
Vxth-
Tadv
UVSET positive going threshold
UVSET negative going threshold
X1/X2 Input positive going threshold
X1/X2 Input negative going threshold
Externally adjustable lead time (advance)
Externally adjustable dead-time for Q1 and Q2
Q1,Q2 output sink current (Vdd=5.0V,
pulsed, 10 usec)
—
—
V
1.4
1.0
—
VDC
VDC
nsec
nsec
A
—
—
—
500
—
Td
20
—
Isink
—
—
2
Isource
tio
Q1,Q2 output source current (Vdd=5.0V,
pulsed, 10 usec)
—
—
—
2
A
Input to output delay (PLL bypassed, cross coupled
mode)
20
—
nsec
tr
tf
Gate turn-on rise time (C1=1000pf, Vdd=5V)
Gate turn-off fall time (C1=1000pf, Vdd=5V)
Cross-over voltage (Vdd=5Vdc, DTIN shorted to
DTOUT, C1=1000pf) Fig. 3
—
—
—
20
20
—
—
—
nsec
nsec
VDC
Vtr
2.5
Rbias
Vbias
Required bias resistor
68
—
—
1.25
—
71
—
KW
Voltage at Rbias pin
VDC
Tjitter
Phase-lock loop output jitter
-20
—
20
—
nsec
mADC
VDC
Ichgpump
Vchgpump
Kvco_dc
Charge pump output current (at VFLTR pin)
Charge pump output voltage (at VFLTR pin)
PLL Vco DC gain
50
1.3
—
1.5
62
1.7
—
KHz/
www.irf.com
3
ADVANCE INFORMATION
IR1175
Lead Definitions and Assignments
Symbol Description
AVDD
Power - + 5 VDC to MOSFET drivers
Q1
Output - gate drive for Q1 power MOSFET
DTOUT1 Output - sets dead time for Q1 output - used with DTIN1
DTIN1
Input - sets dead time for Q1 - used with DTOUT1
Output - sets lead time (advance) for Q1
RADV1
VFLTR1 Output - PLL loop filter for Q1 output
RVCO1
X1
Output - sets PLL center frequency for Q1 output
Input - transformer input for Q1
VDD
Power - +5 Vdc for internal logic
UVSET
Input - sets UVLO+
If this pin is pulled below 1.25VDC externally, then both Q1 and Q2
outputs will be at Vss (disabled)
RBIAS
AVSS
X2
Output - connected to 249K +/- 1% resistor - sets operating current
Ground for logic supply (AVDD)
Input - transformer input for Q2
RVCO2
Output - sets PLL center frequency for Q2 output
VFLTR2 Output - PLL loop filter for Q2
RADV2
DTIN2
Output - sets lead time (advance) for Q2
Input - sets dead time for Q2 - used with DTOUT2
DTOUT2 Output - sets dead time for Q2 - used with DTIN2
VSS
Q2
Ground for MOSFET driver supply (VDD)
Output - gate drive for Q2 power MOSFET
20 Lead SSOP
IR1175
www.irf.com
4
ADVANCE INFORMATION
IR1175
Fig. 1 Typical application circuit when supply Vout < 5.0V
DC
Fig. 2 Typical application circuit when supply Vout = 5.0V
DC
www.irf.com
5
ADVANCE INFORMATION
IR1175
Fig. 3 Gate drive characteristics and definitions
Phase Lock Loop Design Equations:
1 - Resistor to set VCO Ceter Frequency:
Rvco (KW ) = 143 x [Vchgpump(V ) / fvco(KHz)] x Kvco _ dc(KHz/mA)
DC
Example (A): Choose Vchgpump = 1.5V, desired frequency (fvco) = 300KHz
Rvco = 143 x [1.5 /300] x 62 Hz/mA = 44.33 KW
2 - Small Signal gain for VCO:
Kvco_ac (KHz/Volt) = 1E3 x Kvco_dc (KHz/mA)/(7 x Rvco(KW )
Example (B): Choosing same conditions as in example A:
Kvco_ac = 1E3 x 62 / (7 x 44.33) = 199.9 KHz/volt
www.irf.com
6
ADVANCE INFORMATION
IR1175
3 - PLL Natural frequency:
√
ωn =2πfn(KHz)= Ichpump(uA) x Kvco_ac(KHz/V) / C(nF)
Choose Cf such that Cf=C/16 (Minimum value for Cf=470pF)
4 - PLL Damping factor calculations:
P = πE-3 x Rf (KOhms) x C(nF) x fn(KHz)
Typical value for P is 0.707. (Critically damped)
5 - Advance timing:
Tadv(nsec) = RADV (KOhms)*10 - 10
Where RADV is resistance from RADV1 or RADV2 to ground.
Example C: RADV=10Kohms will result in Tadv=10*10 - 10 =90 nsec .
6- Dead time calculations:
Td(nsec)=0.69*Rdt(KOhms)*Cdt(pF) + 5 (For Vdd=5 V)
Where Rdt is resistance between pins DTIN1 and DTOUT1 or DTIN2 and
DTOUT2. Cdt iscapacitance fromDTIN1or DTIN2 toground.
Example D: Rdt=10Kohms and Cdt=22pF will result in: Td=156.8 nsec
Fig. 4 PLL loop filter component definitions
www.irf.com
7
ADVANCE INFORMATION
IR1175
Fig. 5 IR1175 Block Diagram
www.irf.com
8
ADVANCE INFORMATION
IR1175
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo, Japan 171-0021 Tel: 8133 983 0086
IR HONG KONG: Unit 308, #F, New East Ocean Centre, No. 9 Science Museum Road, Tsimshatsui East, Kowloon,
Hong Kong Tel: (852) 2803-7380
Data and specifications subject to change without notice. 1/27/2000
www.irf.com
9
相关型号：
©2020 ICPDF网 联系我们和版权申明