IR1210 [INFINEON]
DUAL LOW SIDE DRIVER; 双通道低侧驱动器
| 型号： | IR1210 |
| 厂家： | 
Infineon |
| 描述： | DUAL LOW SIDE DRIVER |
| 文件： | 总5页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD60165-C
The IR1210 part number has
been updated and changed to
IR4426/IR4427/IR4428
IR1210
Please see new data sheet
DUAL LOW SIDE DRIVER
Features
Product Summary
• Gate drive supply range from 6 to 20V
• CMOS Schmitt-triggered inputs with pull-up
• Matched propagation delay for both channels
• Outputs out of phase with inputs
I +/-
1.5A / 1.5A
6V - 20V
O
V
OUT
Description
t
(typ.)
85 & 65 ns
on/off
The IR1210 is a low voltage, high speed power
MOSFET and IGBT driver. Proprietary latch immune
CMOS technologies enable ruggedized monolithic
construction. Logic inputs are compatible with stan-
dard CMOS or LSTTL outputs. The output drivers
feature a high pulse current buffer stage designed
for minimum driver cross-conduction. Propagation
delays between two channels are matched.
Package
8 Lead SOIC
Block Diagram
1
2
3
4
8
7
6
5
N C
N C
TO
INA
OUTA
INA
INB
LOAD
IR1210
G N D
INB
Vs
OUTB
ADVANCED INFORMATION
IR1210
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to GND. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
V
Fixed supply voltage
-0.3
25
S
V
V
O
Output voltage
-0.3
V + 0.3
S
V
Logic input voltage (INA/N & INB/N)
-0.3
V + 0.3
S
IN
P
Package power dissipation @T ≤ +25°C
—
—
0.625
200
W
D
A
Rth
Thermal resistance, junction to ambient
Junction temperature
°C/W
JA
T
—
150
J
°C
T
Storage temperature
-55
—
150
S
T
Lead temperature (soldering, 10 seconds)
300
L
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute voltages referenced to GND.
Symbol
Definition
Min.
Max.
Units
V
V
Fixed supply oltage
6
20
S
V
O
Output voltage
0
V
V
S
S
V
Logic input voltage (INA/N & INB/N)
Ambient temperature
0
IN
°C
T
-40
125
A
DC Electrical Characteristics
V
(V ) = 15V, T = 25°C unless otherwise specified. The V , and I parameters are referenced to GND and are
S A IN IN
BIAS
applicable to input leads: INA/N and INB/N. The V and I parameters are referenced to GND and are applicable to the
O
O
output leads: OUTA and OUTB.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
V
Logic “0” input voltage (OUT=LO)
2.7
—
—
0.8
1.2
0.1
15
IH
V
Logic “1” input voltage (OUT=HI)
—
—
IL
V
µA
A
V
OH
High level output voltage, V
-V
O
—
—
BIAS
V
Low level output voltage, V
—
—
OL
O
I
Logic “1” input bias current (OUT=HI)
Logic “0” input bias current (OUT=LO)
Quiescent Vs supply current
—
5
V
V
= 0V
IN+
IN
I
—
-10
100
2.3
-30
200
—
= V
S
IN-
IN
I
—
V
= 0V or V
IN S
QS
I
Output high short circuit pulsed current
1.5
V = 0V, V = 0
O IN
O+
PW ≤ 10 µs
I
O-
Output low short circuit pulsed current
1.5
3.3
—
V
= 15V, V = V
IN S
O
PW ≤ 10 µs
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2
ADVANCED INFORMATION
IR1210
Dynamic Electrical Characteristics
V
(V ) = 15V, C = 1000 pF, T = 25°C unless otherwise specified.
BIAS
S
L
A
Symbol
Definition
Min. Typ. Max. Units Test Conditions
t
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
—
—
—
—
85
65
15
10
160
150
35
d1
d2
t
figures 2 & 3
ns
t
r
f
t
Turn-off fall time
25
Functional Block Diagram
5V
Vs
INA
OUTA
PREDRV
D R V
5V
Vs
INB
OUTB
GND
PREDRV
D R V
Lead Assignment and Definitions
Symbol Description
V
Supply voltage
S
GND
INA
Ground
OUTA
INA
Logic input for gate driver output (OUTA), out of phase
Logic input for gate driver output (OUTB), out of phase
Gate drive output A
V
S
GND
INB
INB
OUTB
OUTA
OUTB
Gate drive output B
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3
ADVANCED INFORMATION
IR1210
8 Lead SOIC
01-0021 08
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4
ADVANCED INFORMATION
IR1210
5 0 %
INA
5 0 %
INA
INB
INB
t d2
t f
t d1
t r
O U T A
O U T B
9 0 %
O U T A
O U T B
9 0 %
1 0 %
1 0 %
Figure 1. Timing Diagram
Figure 2. Switching Time Waveforms
V
S
= 15V
6
4.7UF
0.1UF
7
2
4
INA
OUTA
C
C
L
=
=
1000PF
5
INB
OUTB
L
1000PF
3
Figure 3. Switching Time Test Circuit
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 12/20/2000
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5
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