IPD100N04S402ATMA1 [INFINEON]

Power Field-Effect Transistor, 100A I(D), 40V, 0.002ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, GREEN, PLASTIC PACKAGE-3/2;
IPD100N04S402ATMA1
型号: IPD100N04S402ATMA1
厂家: Infineon    Infineon
描述:

Power Field-Effect Transistor, 100A I(D), 40V, 0.002ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, GREEN, PLASTIC PACKAGE-3/2

脉冲 晶体管
文件: 总9页 (文件大小:155K)
中文:  中文翻译
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IPD100N04S4-02  
OptiMOS®-T2 Power-Transistor  
Product Summary  
VDS  
40  
2.0  
100  
V
R DS(on),max  
I D  
m  
A
Features  
• N-channel - Enhancement mode  
PG-TO252-3-313  
• AEC qualified  
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
• Green Product (RoHS compliant)  
• 100% Avalanche tested  
Type  
Package  
Marking  
IPD100N04S4-02  
PG-TO252-3-313 4N0402  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol  
Conditions  
Unit  
Continuous drain current1)  
I D  
T C=25°C, VGS=10V  
100  
100  
A
T C=100°C, VGS=10V2)  
Pulsed drain current2)  
I D,pulse  
EAS  
I AS  
T C=25°C  
400  
440  
Avalanche energy, single pulse2)  
Avalanche current, single pulse  
Gate source voltage  
I D=50A  
mJ  
A
-
100  
VGS  
Ptot  
-
±20  
V
T C=25°C  
Power dissipation  
150  
W
°C  
T j, T stg  
-
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-
-
-55 ... +175  
55/175/56  
Rev. 1.0  
page 1  
2010-04-13  
IPD100N04S4-02  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics2)  
R thJC  
R thJA  
R thJA  
Thermal resistance, junction - case  
-
-
-
-
-
-
1.0  
62  
K/W  
Thermal resistance, junction -  
ambient, leaded  
SMD version, device on PCB  
minimal footprint  
-
-
-
-
62  
40  
6 cm2 cooling area3)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V(BR)DSS  
VGS(th)  
V
V
GS=0V, I D= 1mA  
DS=VGS, I D=95µA  
Drain-source breakdown voltage  
Gate threshold voltage  
40  
-
-
V
2.0  
3.0  
4.0  
V
DS=40V, VGS=0V,  
I DSS  
Zero gate voltage drain current  
-
-
0.04  
1
1
µA  
T j=25°C  
V
DS=18V, VGS=0V,  
20  
T j=85°C2)  
I GSS  
V
V
GS=20V, VDS=0V  
GS=10V, I D=100A  
Gate-source leakage current  
-
-
-
100 nA  
R DS(on)  
Drain-source on-state resistance  
1.7  
2.0  
mΩ  
Rev. 1.0  
page 2  
2010-04-13  
IPD100N04S4-02  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics2)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
7250  
1630  
55  
9430 pF  
2120  
V
GS=0 V, VDS=25 V,  
f =1 MHz  
127  
23  
-
-
-
-
ns  
12  
V
DD=20V, VGS=10V,  
I D=100A, R G=3.5Ω  
t d(off)  
t f  
Turn-off delay time  
Fall time  
26  
24  
Gate Charge Characteristics2)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
39  
12  
91  
5.8  
51  
28  
118  
-
nC  
Q gd  
V
V
DD=32V, I D=100A,  
GS=0 to 10V  
Q g  
Vplateau  
Gate plateau voltage  
V
A
Reverse Diode  
Diode continous forward current2)  
Diode pulse current2)  
I S  
-
-
-
-
100  
400  
T C=25°C  
I S,pulse  
V
GS=0V, I F=100A,  
VSD  
Diode forward voltage  
Reverse recovery time2)  
Reverse recovery charge2)  
-
-
-
0.9  
53  
65  
1.3  
V
T j=25°C  
VR=20V, I F=50A,  
diF/dt =100A/µs  
t rr  
-
-
ns  
nC  
Q rr  
1) Current is limited by bondwire; with an R thJC = 1.0K/W the chip is able to carry 206A at 25°C.  
2) Defined by design. Not subject to production test.  
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev. 1.0  
page 3  
2010-04-13  
IPD100N04S4-02  
1 Power dissipation  
2 Drain current  
P
tot = f(T C); VGS 6 V  
I D = f(T C); VGS 6 V  
160  
140  
120  
100  
80  
100  
80  
60  
40  
20  
0
60  
40  
20  
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
C [°C]  
T
C [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
thJC = f(t p)  
I D = f(VDS); T C = 25 °C; D = 0  
parameter: t p  
Z
parameter: D =t p/T  
101  
1000  
100  
10  
1 µs  
100  
10 µs  
0.5  
0.1  
10-1  
100 µs  
0.05  
0.01  
1 ms  
10-2  
single pulse  
10-3  
1
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
0.1  
1
10  
100  
t p [s]  
V
DS [V]  
Rev. 1.0  
page 4  
2010-04-13  
IPD100N04S4-02  
5 Typ. output characteristics  
I D = f(VDS); T j = 25 °C  
parameter: VGS  
6 Typ. drain-source on-state resistance  
DS(on) = f(I D); T j = 25 °C  
R
parameter: VGS  
400  
8
10 V  
6.5 V  
7 V  
5.5 V  
360  
6 V  
7
6
5
4
3
2
1
320  
280  
240  
200  
160  
120  
80  
6 V  
5.5 V  
5 V  
6.5 V  
7 V  
40  
10 V  
0
0
1
2
3
4
0
40  
80  
120  
160  
200  
V
DS [V]  
I
D [A]  
7 Typ. transfer characteristics  
I D = f(VGS); VDS = 6V  
parameter: T j  
8 Typ. drain-source on-state resistance  
R
DS(on) = f(T j); I D = 100 A; VGS = 10 V  
400  
350  
300  
250  
200  
150  
3.5  
3
2.5  
2
175 °C  
100  
1.5  
1
25 °C  
50  
-55 °C  
0
3
4
5
6
7
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
V
GS [V]  
Rev. 1.0  
page 5  
2010-04-13  
IPD100N04S4-02  
9 Typ. gate threshold voltage  
GS(th) = f(T j); VGS = VDS  
10 Typ. capacitances  
V
C = f(VDS); VGS = 0 V; f = 1 MHz  
parameter: I D  
4
104  
103  
102  
Ciss  
3.5  
3
Coss  
950 µA  
95 µA  
2.5  
2
Crss  
1.5  
101  
1
0
5
10  
15  
20  
25  
30  
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
V
DS [V]  
11 Typical forward diode characteristicis  
12 Avalanche characteristics  
A S= f(t AV  
IF = f(VSD)  
I
)
parameter: T j  
parameter: Tj(start)  
103  
100  
25 °C  
100 °C  
102  
150 °C  
25°C  
10  
175C  
101  
100  
1
1
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
10  
100  
1000  
V
SD [V]  
t
AV [µs]  
Rev. 1.0  
page 6  
2010-04-13  
IPD100N04S4-02  
13 Avalanche energy  
AS = f(T j)  
14 Drain-source breakdown voltage  
E
V
BR(DSS) = f(T j); I D = 1 mA  
parameter: I D  
44  
1000  
900  
25 A  
800  
700  
600  
42  
40  
38  
500  
50 A  
400  
300  
100 A  
200  
100  
0
-55  
-15  
25  
65  
105  
145  
25  
75  
125  
175  
T j [°C]  
T j [°C]  
15 Typ. gate charge  
16 Gate charge waveforms  
V
GS = f(Q gate); I D = 100 A pulsed  
parameter: VDD  
10  
9
8
7
6
5
4
3
2
1
V GS  
8 V  
32 V  
Q g  
V gs(th)  
Q g(th)  
Q sw  
Q gd  
Q gate  
Q gs  
0
0
20  
40  
Q
60  
gate [nC]  
80  
100  
Rev. 1.0  
page 7  
2010-04-13  
IPD100N04S4-02  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© Infineon Technologies AG 2010  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics. With respect to any examples or hints given herein, any typical values stated  
herein and/or any information regarding the application of the device, Infineon Technologies hereby  
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties  
of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices, please contact  
the nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances.  
For information on the types in question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably be  
expected to cause the failure of that life-support device or system or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be implanted  
in the human body or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.  
Rev. 1.0  
page 8  
2010-04-13  
IPD100N04S4-02  
Revision History  
Version  
Date  
Changes  
13.04.2010 Final Data Sheet  
Revision 1.0  
Rev. 1.0  
page 9  
2010-04-13  

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