IPD110N12N3GBUMA1 [INFINEON]
Power Field-Effect Transistor, 75A I(D), 120V, 0.011ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, GREEN, PLASTIC, TO-252, 3 PIN;
| 型号： | IPD110N12N3GBUMA1 |
| 厂家： | 
Infineon |
| 描述： | Power Field-Effect Transistor, 75A I(D), 120V, 0.011ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, GREEN, PLASTIC, TO-252, 3 PIN 开关 脉冲 晶体管 |
| 文件： | 总11页 (文件大小：580K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET
MetalꢀOxideꢀSemiconductorꢀFieldꢀEffectꢀTransistor
OptiMOS™ꢀPower-Transistor,ꢀ120V
OptiMOS™ꢀ3ꢀPower-Transistor
IPD_S110N12N3ꢀG
DataꢀSheet
Rev.ꢀ2.4
Final
Industrialꢀ&ꢀMultimarket
IPD110N12N3 G
IPS110N12N3 G
OptiMOSTM3Power-Transistor
Features
Product Summary
VDS
120
11
V
ꢀ N-channel, normal level
RDS(on),max
mΩ
ꢀ Excellent gate charge x R DS(on) product (FOM)
ꢀ Very low on-resistance R DS(on)
ID
75
A
ꢀ 175 °C operating temperature
ꢀ Pb-free lead plating; RoHS compliant
ꢀ Qualified according to JEDEC1) for target application
ꢀ Halogen free according to IEC61249-2-21 *
ꢀ Ideal for high-frequency switching and synchronous rectification
Type
IPS110N12N3 G
IPD110N12N3 G
Package
Marking
PG-TO251-3
110N12N
PG-TO252-3
110N12N
Maximum ratings, at T j=25 °C, unless otherwise specified
Value
Parameter
Symbol Conditions
Unit
I D
T C=25 °C
Continuous drain current
75
54
A
T C=100 °C
Pulsed drain current2)
I D,pulse
E AS
T C=25 °C
300
I D=75 A, R GS=25 Ω
Avalanche energy, single pulse
120
mJ
V
Gate source voltage3)
V GS
±20
P tot
T C=25 °C
136
W
°C
T j, T stg
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
-55 ... 175
55/175/56
1)J-STD20 and JESD22
2) see figure 3
3)
T
=150°C and duty cycle D=0.01 for Vgs<-5V
jmax
* Except package TO251-3
Rev. 2.4
page 1
2015-06-24
IPD110N12N3 G
IPS110N12N3 G
Values
Parameter
Symbol Conditions
Unit
min.
typ.
max.
Thermal characteristics
R thJC
Thermal resistance, junction - case
-
-
-
-
-
-
1.1
75
50
K/W
R thJA
minimal footprint
Thermal resistance, junction -
ambient
6 cm2 cooling area4)
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
V (BR)DSS V GS=0 V, I D=1 mA
V GS(th) V DS=V GS, I D=83 µA
Drain-source breakdown voltage
Gate threshold voltage
120
2
-
-
V
3
4
V DS=100 V, V GS=0 V,
T j=25 °C
I DSS
Zero gate voltage drain current
-
0.1
1
µA
V
DS=100 V, V GS=0 V,
-
-
10
1
100
T j=125 °C
I GSS
V GS=20 V, V DS=0 V
Gate-source leakage current
Drain-source on-state resistance
Gate resistance
100 nA
R DS(on) V GS=10 V, I D=75 A
-
9.2
1.5
83
11
-
mΩ
Ω
R G
-
|V DS|>2|I D|R DS(on)max
I D=75 A
,
g fs
Transconductance
42
-
S
4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 2.4
page 2
2015-06-24
IPD110N12N3 G
IPS110N12N3 G
Values
Parameter
Symbol Conditions
Unit
min.
typ.
max.
Dynamic characteristics6)
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
C iss
-
-
-
-
-
-
-
3240
408
22
4310 pF
V GS=0 V, V DS=60 V,
f =1 MHz
C oss
C rss
t d(on)
t r
543
-
16
-
-
-
-
ns
16
V
DD=60 V, V GS=10 V,
I D=75 A, R G,ext=1.6 Ω
t d(off)
t f
Turn-off delay time
Fall time
24
8
Gate Charge Characteristics5)
Gate to source charge
Gate to drain charge
Q gs
-
-
-
-
-
-
18
12
20
49
5.6
56
-
-
nC
Q gd
V
V
DD=60 V, I D=75 A,
GS=0 to 10 V
Q sw
Q g
Switching charge
-
Gate charge total6)
65
-
V plateau
Q oss
Gate plateau voltage
V
Output charge6)
V DD=60 V, V GS=0 V
75
nC
Reverse Diode
I S
Diode continous forward current
Diode pulse current
-
-
-
-
75
A
T C=25 °C
I S,pulse
300
V GS=0 V, I F=75 A,
T j=25 °C
V SD
Diode forward voltage
-
1
1.2
V
t rr
-
-
90
ns
V R=60 V, I F=I S,
di F/dt =100 A/µs
Q rr
Reverse recovery charge
249
nC
5) See figure 16 for gate charge parameter definition
6) Defined by design. Not subject to production test
Rev. 2.4
page 3
2015-06-24
IPD110N12N3 G
IPS110N12N3 G
1 Power dissipation
2 Drain current
P tot=f(T C)
I D=f(T C); V GS≥10 V
140
120
100
80
80
70
60
50
40
30
20
10
0
60
40
20
0
0
50
100
150
200
0
50
100
150
200
TC [°C]
TC [°C]
3 Safe operating area
I D=f(V DS); T C=25 °C; D =0
parameter: t p
4 Max. transient thermal impedance
Z thJC=f(t p)
parameter: D =t p/T
103
101
1 µs
10 µs
102
100 µs
100
1 ms
0.5
DC
101
10 ms
0.2
0.1
10-1
0.05
0.02
100
0.01
single pulse
10-1
10-2
10-1
100
101
102
103
10-5
10-4
10-3
10-2
10-1
100
VDS [V]
tp [s]
Rev. 2.4
page 4
2015-06-24
IPD110N12N3 G
IPS110N12N3 G
5 Typ. output characteristics
I D=f(V DS); T j=25 °C
6 Typ. drain-source on resistance
R DS(on)=f(I D); T j=25 °C
parameter: V GS
parameter: V GS
250
30
10 V
8 V
5 V
4.5 V
7 V
25
20
15
10
5
200
150
5.5 V
6.5 V
6 V
100
6 V
10 V
5.5 V
50
5 V
4.5 V
0
0
0
1
2
3
4
5
0
20
40
60
80
VDS [V]
ID [A]
7 Typ. transfer characteristics
I D=f(V GS); |V DS|>2|I D|R DS(on)max
parameter: T j
8 Typ. forward transconductance
g fs=f(I D); T j=25 °C
200
150
100
50
100
80
60
40
20
0
175 °C
25 °C
0
0
2
4
6
8
0
20
40
60
80
VGS [V]
ID [A]
Rev. 2.4
page 5
2015-06-24
IPD110N12N3 G
IPS110N12N3 G
9 Drain-source on-state resistance
10 Typ. gate threshold voltage
V GS(th)=f(T j); V GS=V DS
parameter: I D
R DS(on)=f(T j); I D=75 A; V GS=10 V
25
20
4
3.5
3
830 µA
83 µA
2.5
15
98 %
2
1.5
1
typ
10
5
0
0.5
0
-60
-20
20
60
100
140
180
-60
-20
20
60
100
140
180
Tj [°C]
Tj [°C]
11 Typ. capacitances
12 Forward characteristics of reverse diode
I F=f(V SD
C =f(V DS); V GS=0 V; f =1 MHz
)
parameter: T j
104
103
Ciss
25 °C
175 °C
175 °C, 98%
103
102
101
102
Coss
25 °C, 98%
101
Crss
100
0
0
20
40
60
80
100
0.5
1
1.5
2
VDS [V]
VSD [V]
Rev. 2.4
page 6
2015-06-24
IPD110N12N3 G
IPS110N12N3 G
13 Avalanche characteristics
14 Typ. gate charge
V GS=f(Q gate); I D=67 A pulsed
parameter: V DD
I AS=f(t AV); R GS=25 Ω
parameter: T j(start)
103
10
96 V
60 V
8
102
24 V
6
25 °C
4
100 °C
150 °C
101
2
100
0
100
101
102
103
0
10
20
30
40
50
tAV [µs]
Qgate [nC]
15 Drain-source breakdown voltage
16 Gate charge waveforms
V BR(DSS)=f(T j); I D=1 mA
135
130
125
120
115
110
105
V GS
Q g
V gs(th)
Q g(th)
Q sw
Q gd
Q gate
Q gs
-60
-20
20
60
100
140
180
Tj [°C]
Rev. 2.4
page 7
2015-06-24
IPD110N12N3 G
IPS110N12N3 G
PG-TO-251SL : Outline
Rev. 2.4
page 8
2015-06-24
IPD110N12N3 G
IPS110N12N3 G
PG-TO252-3: Outline
Rev. 2.4
page 9
2015-06-24
OptiMOS™ꢀ3ꢀPower-Transistor
IPD_S110N12N3ꢀG
RevisionꢀHistory
IPD_S110N12N3 G
Revision:ꢀ2015-07-16,ꢀRev.ꢀ2.4
Previous Revision
Revision Date
2.4
Subjects (major changes since last revision)
Update VGS(th) and package outline TO252-3
2015-07-16
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11
Rev.ꢀ2.4,ꢀꢀ2015-07-16
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