HYS64T128021HDL-3-B [INFINEON]
DDR DRAM Module, 128MX64, 0.45ns, CMOS, GREEN, SODIMM-200;
| 型号： | HYS64T128021HDL-3-B |
| 厂家： | 
Infineon |
| 描述： | DDR DRAM Module, 128MX64, 0.45ns, CMOS, GREEN, SODIMM-200 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总62页 (文件大小：3352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev 1.00, Jun. 2005
HYS64T32000HDL–[2.5/…/5]–B
HYS64T64020HDL–[2.5/…/5]–B
HYS64T128021HDL–[2.5/…/5]–B
200-Pin SO-DIMM DDR2 SDRAM Modules
DDR2 SDRAM
SO-DIMM SDRAM
RoHS Compliant
Memory Products
N e v e r s t o p t h i n k i n g .
Edition 2005-06
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
HYS64T32000HDL–[2.5/…/5]–B HYS64T64020HDL–[2.5/…/5]–B HYS64T128021HDL–[2.5/…/5]–B
Revision History: 2005-06, Rev 1.00
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Template: mp_a4_s_rev314 / 3 / 2005-05-02
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
2.1
2.2
Pin Configurations and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
I
DD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.1
3.4.2
I
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Data Sheet
4
Rev 1.00, 2005-06
05122005-2TKP-OM7N
200-Pin SO-DIMM DDR2 SDRAM Modules
DDR2 SDRAM
HYS64T32000HDL–[2.5/…/5]–B
HYS64T64020HDL–[2.5/…/5]–B
HYS64T128021HDL–[2.5/…/5]–B
1
Overview
This chapter gives an overview of the 200-Pin SO-DIMM DDR2 SDRAM Modules product family and describes its
main characteristics.
1.1
Features
•
200-Pin PC2–6400, PC2–5300, PC2–4200 and
PC2–3200 DDR2 SDRAM memory modules for use
as main memory when installed in systems such as
mobile personal computers.
32M × 64, 64M × 64 and 128M × 64 module
organization,and 32M × 16, 64M × 8 chip
organization
Standard Double-Data-Rate-Two Synchronous
DRAMs (DDR2 SDRAM) with a single + 1.8 V
(± 0.1 V) power supply
•
•
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2
settings
•
•
•
DCC enabling via EMRS2 setting
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and
On-Die Termination (ODT)
•
•
•
•
Serial Presence Detect with E2PROM
UDIMM and EDIMM Dimensions (nominal):
30 mm high, 133.35 mm wide
•
•
•
Built with 512-Mbit DDR2 SDRAMs in P-TFBGA-84
and P-TFBGA-60 chipsize packages
Programmable CAS Latencies (3, 4 and 5), Burst
Length (8 & 4) and Burst Type
•
Based on standard reference layouts Raw Card “A”,
“C”,”E”
•
•
RoHS compliant products1)
All speed grades faster than DDR400 comply with
DDR400 timing specifications.
Auto Refresh (CBR) and Self Refresh
Table 1
Performance
Product Type Speed Code
Speed Grade
–2.5
–3
–3S
Unit
PC2–6400 6–6–6 PC2–5300 4–4–4 PC2–5300 5–5–5 —
max. Clock Frequency
@CL6
fCK6
fCK5
fCK4
fCK3
tRCD 15
tRP 15
tRAS 45
tRC 60
400
333
266
200
333
333
333
200
12
12
45
57
333
333
266
200
15
15
45
60
@CL5
@CL4
@CL3
MHz
MHz
MHz
ns
ns
ns
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.
Data Sheet
5
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Overview
Table 2
Performance
Product Type Speed Code
Speed Grade
–3.7
–5
Unit
—
PC2–4200 4–4–4
PC2–3200 3–3–3
max. Clock Frequency @CL5 fCK5 266
@CL4 fCK4 266
200
200
200
15
15
40
MHz
MHz
MHz
ns
ns
ns
@CL3 fCK3 200
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
tRCD 15
tRP 15
tRAS 45
tRC 60
55
ns
1.2
Description
The INFINEON HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B module family are small outline DIMM modules “SO-
DIMMs” with 30,0 mm height based on DDR2 technology. DIMMs are available as non-ECC modules in
32M × 64 (256 MB), 64M × 64 (512 MB) and 128M × 64(1 GB) organization and density, intended for mounting
into 200-pin connector sockets.
The memory array is designed with 512-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write
protected; the second 128 bytes are available to the customer.
Table 3
Ordering Information for RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM
Technology
PC2–6400
HYS64T32000HDL–2.5–B 256 MB 1R×16 PC2–6400S–666–12–C0 1 Rank, Non-ECC
HYS64T64020HDL–2.5–B 512 MB 2R×16 PC2–6400S–666–12–A0 2 Rank, Non-ECC
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
HYS64T128021HDL–2.5–B 1 GB 2Rx8 PC2-6400S–666–12–E0
2 Rank, Non-ECC
PC2–5300
HYS64T32000HDL–3–B
HYS64T64020HDL–3–B
HYS64T128021HDL–3–B
PC2–5300
256 MB 1R×16 PC2–5300S–444–12–C0 1 Rank, Non-ECC
512 MB 1R×16 PC2–5300S–444–12–A0 2 Rank, Non-ECC
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
1 GB 2Rx8 PC2-5300S–444–12–E0
2 Rank, Non-ECC
HYS64T32000HDL–3S–B
HYS64T64020HDL–3S–B
HYS64T128021HDL–3S–B 1 GB 2Rx8 PC2-5300S–555–12–E0
256 MB 1R×16 PC2–5300S–555–12–C0 1 Rank, Non-ECC
512 MB 1R×16 PC2–5300S–555–12–A0 2 Rank, Non-ECC
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
2 Rank, Non-ECC
PC2–4200
HYS64T32000HDL–3.7–B 256 MB 1R×16 PC2–4200S–444–12–C0 1 Rank, Non-ECC
HYS64T64020HDL–3.7–B 512 MB 1R×16 PC2–4200S–444–12–A0 2 Rank, Non-ECC
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
HYS64T128021HDL–3.7–B 1 GB 2Rx8 PC2-4200S–444–12–E0
2 Rank, Non-ECC
PC2–3200
HYS64T32000HDL–5–B
256 MB 1R×16 PC2–3200S–333–12–C0 1 Rank, Non-ECC
512 Mbit (×16)
Data Sheet
6
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Overview
Table 3
Ordering Information for RoHS Compliant Products (cont’d)
Product Type1)
Compliance Code2)
Description
SDRAM
Technology
HYS64T64020HDL–5–B
HYS64T128021HDL–5–B
512 MB 1R×16 PC2–3200S–333–12–A0 2 Rank, Non-ECC
1 GB 2Rx8 PC2-3200S–333–12–E0 2 Rank, Non-ECC
512 Mbit (×16)
512 Mbit (×8)
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS64T16000HU–5–A, indicating
Rev. “B” dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see
Chapter 6 of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200U–444–11–
A0”, where 4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column
Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the
latest JEDEC SPD Revision 1.1 and produced on the Raw Card “C”.
Table 4
Address Format
DIMM
Module
Memory
Ranks
1
2
2
ECC/
# of
# of row/bank/column Raw
Density
Organization
Non-ECC
SDRAMs
bits
Card
C
256 MByte
512 MByte
1 GByte
32M × 64
64M × 64
128M × 64
Non-ECC
Non-ECC
Non-ECC
4
8
16
13/2/10
13/2/10
14/2/10
A
E
Table 5
Components on Modules 1)
Product Type2)
DRAM Components2)
HYB18T512160BF
HYB18T512160BF
HYB18T512800BF
DRAM Density
512 Mbit
512 Mbit
DRAM Organisation
HYS64T32000HU
HYS64T64020HU
HYS64T128021HU
32M × 16
64M × 16
64M × 8
512 Mbit
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
2) Green Product
Data Sheet
7
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Pin Configurations and Block Diagrams
2
Pin Configurations and Block Diagrams
2.1
Pin Configuration
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 6 (200 pins). The
abbreviations used in columns Pin and Buffer Type are explained in Table 7 and Table 8 respectively. The pin
numbering is depicted in Figure 1
Table 6
Pin Configuration of SO-DIMM
Pin or Ball No.
Name Pin
Buffer Function
Type Type
Clock Signals
30
164
32
CK0
CK1
CK0
CK1
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Clock Signals 2:0, Complement Clock Signals 2:0
The system clock inputs. All address and command
lines are sampled on the cross point of the rising edge
of CK and the falling edge of CK. A Delay Locked
Loop (DLL) circuit is driven from the clock inputs and
output timing for read operations is synchronized to
the input clock.
166
79
80
CKE0
CKE1
I
I
SSTL
SSTL
Clock Enable Rank 1:0
Activates the DDR2 SDRAM CK signal when HIGH
and deactivates the CK signal when LOW. By
deactivating the clocks, CKE LOW initiates the Power
Down Mode or the Self Refresh Mode.
Note:2 Ranks module
Not Connected
NC
NC
—
Note:1-rank module
Control Signals
110
115
S0
S1
I
I
SSTL
SSTL
Chip Select Rank 1:0
Enables the associated DDR2 SDRAM command
decoder when LOW and disables the command
decoder when HIGH. When the command decoder is
disabled, new commands are ignored but previous
operations continue. Rank 0 is selected by S0; Rank
1 is selected by S1. Ranks are also called "Physical
banks".2 Ranks module
NC
NC
I
—
Not Connected
Note:1-rank module
Row Address Strobe
108
RAS
SSTL
When sampled at the cross point of the rising edge of
CK,and falling edge of CK, RAS, CAS and WE define
the operation to be executed by the SDRAM.
113
109
CAS
WE
I
I
SSTL
SSTL
Column Address Strobe
Write Enable
Data Sheet
8
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Pin Configurations and Block Diagrams
Table 6
Pin Configuration of SO-DIMM (cont’d)
Pin or Ball No.
Name Pin
Buffer Function
Type Type
Address Signals
107
106
BA0
BA1
I
I
SSTL
SSTL
Bank Address Bus 2:0
Selects which DDR2 SDRAM internal bank of four or
eight is activated.
85
BA2
I
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Less than 1Gb DDR2 SDRAMS
Address Bus 12:0
102
101
100
99
98
97
94
92
93
91
I
I
I
I
I
I
I
I
I
I
I
I
I
During a Bank Activate command cycle, defines the
row address when sampled at the crosspoint of the
rising edge of CK and falling edge of CK. During a
Read or Write command cycle, defines the column
address when sampled at the cross point of the rising
edge of CK and falling edge of CK. In addition to the
column address, AP is used to invoke autoprecharge
operation at the end of the burst read or write cycle. If
AP is HIGH, autoprecharge is selected and BA0-BAn
defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge
command cycle, AP is used in conjunction with BA0-
BAn to control which bank(s) to precharge. If AP is
HIGH, all banks will be precharged regardless of the
state of BA0-BAn inputs. If AP is LOW, then BA0-BAn
are used to define which bank to precharge.
105
90
89
A12
A13
NC
I
SSTL
SSTL
—
Address Signal 12
Note:Module based on 256 Mbit or larger dies
Address Signal 13
Note:1 Gbit based module
Not Connected
116
I
NC
Note:Module based on 512 Mbit or smaller dies
Data Signals
5
7
17
19
4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Note:Data Input/Output pins
6
14
16
23
25
35
37
Data Sheet
9
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Pin Configurations and Block Diagrams
Table 6
Pin Configuration of SO-DIMM (cont’d)
Pin or Ball No.
Name Pin
Buffer Function
Type Type
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Input/Output pins
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
Data Sheet
10
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Pin Configurations and Block Diagrams
Table 6
Pin Configuration of SO-DIMM (cont’d)
Pin or Ball No.
Name Pin
Buffer Function
Type Type
158
160
174
176
179
181
189
191
180
182
192
194
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Strobe Signals
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186
DQS0 I/O
DQS0 I/O
DQS1 I/O
DQS1 I/O
DQS2 I/O
DQS2 I/O
DQS3 I/O
DQS3 I/O
DQS4 I/O
DQS4 I/O
DQS5 I/O
DQS5 I/O
DQS6 I/O
DQS6 I/O
DQS7 I/O
DQS7 I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobe Bus 7:0
The data strobes, associated with one data byte,
sourced with data transfers. In Write mode, the data
strobe is sourced by the controller and is centered in
the data window. In Read mode the data strobe is
sourced by the DDR2 SDRAM and is sent at the
leading edge of the data window. DQS signals are
complements, and timing is relative to the crosspoint
of respective DQS and DQS. If the module is to be
operated in single ended strobe mode, all DQS
signals must be tied on the system board to VSS and
DDR2 SDRAM mode registers programmed
appropriately.
Data Mask Signals
10
26
52
67
130
147
170
185
EEPROM
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Mask Bus 7:0
The data write masks, associated with one data byte.
In Write mode, DM operates as a byte mask by
allowing input data to be written if it is LOW but blocks
the write operation if it is HIGH. In Read mode, DM
lines have no effect.
Data Sheet
11
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Pin Configurations and Block Diagrams
Table 6
Pin Configuration of SO-DIMM (cont’d)
Pin or Ball No.
Name Pin
Buffer Function
Type Type
197
SCL
SDA
I
CMOS Serial Bus Clock
This signal is used to clock data into and out of the
SPD EEPROM.
195
I/O
OD
Serial Bus Data
This is a bidirectional pin used to transfer data into or
out of the SPD EEPROM. A resistor must be
connected from SDA to VDDSPD on the motherboard to
act as a pull-up.
198
200
SA0
SA1
I
I
CMOS Serial Address Select Bus 2:0
CMOS
Address pins used to select the Serial Presence
Detect base address.
Power Supplies
1
VREF
AI
—
—
I/O Reference Voltage
Reference voltage for the SSTL-18 inputs.
199
VDDSPD PWR
EEPROM Power Supply
Power supplies for core, I/O, Serial Presence Detect,
and ground for the module.
81,82,87,88,95,96,103,104,
111,112,117,118
VDD
PWR
GND
—
—
Power Supply
Power supplies for core, I/O, Serial Presence Detect,
and ground for the module.
2,3,8,9,12,15,18,21,24,27,28, VSS
33,34,39,40,41,42,47,48,53,
54,59,60,65,66,71,72,77,78,
121,122,127,128,132,133,138,
139,144,145,149,150,155,156,
, 161,162,165,171,172,177,
178,183,184,187,190,193,196
Ground Plane
Power supplies for core, I/O, Serial Presence Detect,
and ground for the module.
Other Pins
114
119
ODT0
ODT1
I
I
SSTL
SSTL
On-Die Termination Control 1:0
On-Die Termination Control 1
Asserts on-die termination for DQ, DM, DQS, and
DQS signals if enabled via the DDR2 SDRAM mode
register.
Note:2 Rank modules
Not Connected
Note:1 Rank modules
Not connected
Pins not connected on Infineon SO-DIMMs
NC
NC
NC
NC
—
—
50,69,83,84,120,163,168
Table 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
I/O
Output. Digital levels.
I/O is a bidirectional input/output signal.
Data Sheet
12
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Pin Configurations and Block Diagrams
Table 7
Abbreviations for Pin Type (cont’d)
Abbreviation
AI
PWR
GND
NC
Description
Input. Analog levels.
Power
Ground
Not Connected
Table 8
Abbreviation
SSTL
Abbreviations for Buffer Type
Description
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
CMOS
Low Voltage CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and
tristate, and allows multiple devices to share as a wire-OR.
Data Sheet
13
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Pin Configurations and Block Diagrams
62%& ꢇ 0IN ꢀꢀꢁ
$1ꢀ ꢇ 0IN ꢀꢀꢈ
633 ꢇ 0IN ꢀꢀꢊ
0IN ꢀꢀꢃ ꢇ
0IN ꢀꢀꢄ ꢇ
0IN ꢀꢁꢀ ꢇ
0IN ꢀꢁꢂ ꢇ
0IN ꢀꢁꢅ ꢇ
0IN ꢀꢃꢃ ꢇ
0IN ꢀꢃꢄ ꢇ
0IN ꢀꢆꢀ ꢇ
0IN ꢀꢆꢂ ꢇ
0IN ꢀꢆꢅ ꢇ
633
633 ꢇ 0IN ꢀꢀꢆ
$1ꢁ ꢇ 0IN ꢀꢀꢉ
$13ꢀ ꢇ 0IN ꢀꢁꢁ
633 ꢇ 0IN ꢀꢁꢈ
0IN ꢀꢀꢂ ꢇ
$1ꢂ
$1ꢈ
$-ꢀ
$1ꢄ
633
0IN ꢀꢀꢅ ꢇ 633
0IN ꢀꢁꢃ ꢇ 633
0IN ꢀꢁꢄ ꢇ $1ꢉ
0IN ꢀꢃꢀ ꢇ $1ꢁꢃ
0IN ꢀꢃꢂ ꢇ 633
0IN ꢀꢃꢅ ꢇ 633
0IN ꢀꢆꢃ ꢇ #+ꢀ
0IN ꢀꢆꢄ ꢇ $1ꢁꢂ
0IN ꢀꢂꢀ ꢇ 633
$13ꢀ ꢇ 0IN ꢀꢁꢆ
$1ꢃ ꢇ 0IN ꢀꢁꢉ
633 ꢇ 0IN ꢀꢃꢁ
$1ꢆ ꢇ 0IN ꢀꢁꢊ
$1ꢅ ꢇ 0IN ꢀꢃꢆ
633 ꢇ 0IN ꢀꢃꢉ
$1ꢁꢆ
$-ꢁ
#+ꢀ
633
$1ꢊ ꢇ 0IN ꢀꢃꢈ
$13ꢁ ꢇ 0IN ꢀꢃꢊ
633 ꢇ 0IN ꢀꢆꢆ
$13ꢁ ꢇ 0IN ꢀꢆꢁ
$1ꢁꢀ ꢇ 0IN ꢀꢆꢈ
633 ꢇ 0IN ꢀꢆꢊ
$1ꢁꢁ ꢇ 0IN ꢀꢆꢉ
$1ꢁꢈ
633 ꢇ 0IN ꢀꢂꢁ
$1ꢁꢉ ꢇ 0IN ꢀꢂꢈ
$13ꢃ ꢇ 0IN ꢀꢂꢊ
633 ꢇ 0IN ꢀꢈꢆ
0IN ꢀꢂꢃ ꢇ 633
0IN ꢀꢂꢄ ꢇ $1ꢃꢁ
0IN ꢀꢈꢀ ꢇ .#
$1ꢁꢄ ꢇ 0IN ꢀꢂꢆ
633 ꢇ 0IN ꢀꢂꢉ
$13ꢃ ꢇ 0IN ꢀꢈꢁ
$1ꢁꢅ ꢇ 0IN ꢀꢈꢈ
633 ꢇ 0IN ꢀꢈꢊ
$1ꢃꢈ ꢇ 0IN ꢀꢄꢆ
$-ꢆ ꢇ 0IN ꢀꢄꢉ
633 ꢇ 0IN ꢀꢉꢁ
$1ꢃꢉ ꢇ 0IN ꢀꢉꢈ
#+%ꢀ ꢇ 0IN ꢀꢉꢊ
.# ꢇ 0IN ꢀꢅꢆ
0IN ꢀꢂꢂ ꢇ $1ꢃꢀ
0IN ꢀꢂꢅ ꢇ 633
0IN ꢀꢈꢃ ꢇ $-ꢃ
0IN ꢀꢈꢄ ꢇ $1ꢃꢃ
0IN ꢀꢄꢀ ꢇ 633
0IN ꢀꢈꢂ ꢇ 633
0IN ꢀꢈꢅ ꢇ $1ꢃꢆ
0IN ꢀꢄꢃ ꢇ $1ꢃꢅ
0IN ꢀꢄꢄ ꢇ 633
0IN ꢀꢉꢀ ꢇ $13ꢆ
0IN ꢀꢉꢂ ꢇ $1ꢆꢀ
0IN ꢀꢉꢅ ꢇ 633
$1ꢁꢊ ꢇ 0IN ꢀꢈꢉ
$1ꢃꢂ ꢇ 0IN ꢀꢄꢁ
633 ꢇ 0IN ꢀꢄꢈ
0IN ꢀꢄꢂ ꢇ $1ꢃꢊ
0IN ꢀꢄꢅ ꢇ $13ꢆ
0IN ꢀꢉꢃ ꢇ 633
.# ꢇ 0IN ꢀꢄꢊ
$1ꢃꢄ ꢇ 0IN ꢀꢉꢆ
633 ꢇ 0IN ꢀꢉꢉ
0IN ꢀꢉꢄ ꢇ $1ꢆꢁ
0IN ꢀꢅꢀ ꢇ .#ꢋ#+%ꢁ
0IN ꢀꢅꢂ ꢇ .#
0IN ꢀꢅꢅ ꢇ 6$$
0IN ꢀꢊꢃ ꢇ !ꢉ
6$$ ꢇ 0IN ꢀꢅꢁ
.#ꢋ"!ꢃ ꢇ 0IN ꢀꢅꢈ
0IN ꢀꢅꢃ ꢇ 6$$
0IN ꢀꢅꢄ ꢇ .#ꢋ!ꢁꢂ
6$$ ꢇ 0IN ꢀꢅꢉ
!ꢊ ꢇ 0IN ꢀꢊꢁ
!ꢁꢃ ꢇ 0IN ꢀꢅꢊ
!ꢅ ꢇ 0IN ꢀꢊꢆ
0IN ꢀꢊꢀ ꢇ !ꢁꢁ
0IN ꢀꢊꢂ ꢇ !ꢄ
6$$ ꢇ 0IN ꢀꢊꢈ
!ꢆ ꢇ 0IN ꢀꢊꢊ
0IN ꢀꢊꢄ ꢇ 6$$
0IN ꢁꢀꢀ ꢇ !ꢃ
!ꢈ ꢇ 0IN ꢀꢊꢉ
!ꢁ ꢇ 0IN ꢁꢀꢁ
0IN ꢀꢊꢅ ꢇ !ꢂ
0IN ꢁꢀꢃ ꢇ !ꢀ
6$$ ꢇ 0IN ꢁꢀꢆ
"!ꢀ ꢇ 0IN ꢁꢀꢉ
6$$ ꢇ 0IN ꢁꢁꢁ
0IN ꢁꢀꢂ ꢇ 6$$
0IN ꢁꢀꢅ ꢇ 2!3
0IN ꢁꢁꢃ ꢇ 6$$
0IN ꢁꢁꢄ ꢇ .#ꢋ!ꢁꢆ
0IN ꢁꢃꢀ ꢇ .#
!ꢁꢀꢋ!0 ꢇ 0IN ꢁꢀꢈ
7% ꢇ 0IN ꢁꢀꢊ
#!3 ꢇ 0IN ꢁꢁꢆ
6$$ ꢇ 0IN ꢁꢁꢉ
633 ꢇ 0IN ꢁꢃꢁ
0IN ꢁꢀꢄ ꢇ "!ꢁ
0IN ꢁꢁꢀ ꢇ 3ꢀ
0IN ꢁꢁꢂ ꢇ /$4ꢀ
0IN ꢁꢁꢅ ꢇ 6$$
0IN ꢁꢃꢃ ꢇ 633
0IN ꢁꢃꢄ ꢇ $1ꢆꢉ
0IN ꢁꢆꢀ ꢇ $-ꢂ
0IN ꢁꢆꢂ ꢇ $1ꢆꢅ
0IN ꢁꢆꢅ ꢇ 633
0IN ꢁꢂꢃ ꢇ $1ꢂꢈ
0IN ꢁꢂꢄ ꢇ $13ꢈ
0IN ꢁꢈꢀ ꢇ 633
0IN ꢁꢈꢂ ꢇ $1ꢂꢉ
0IN ꢁꢈꢅ ꢇ $1ꢈꢃ
0IN ꢁꢄꢃ ꢇ 633
0IN ꢁꢄꢄ ꢇ #+ꢁ
0IN ꢁꢉꢀ ꢇ $-ꢄ
0IN ꢁꢉꢂ ꢇ $1ꢈꢂ
.#ꢋ3ꢁ ꢇ 0IN ꢁꢁꢈ
.#ꢋ/$4ꢁ ꢇ 0IN ꢁꢁꢊ
$1ꢆꢃ ꢇ 0IN ꢁꢃꢆ
633 ꢇ 0IN ꢁꢃꢉ
0IN ꢁꢃꢂ ꢇ $1ꢆꢄ
0IN ꢁꢃꢅ ꢇ 633
0IN ꢁꢆꢃ ꢇ 633
0IN ꢁꢆꢄ ꢇ $1ꢆꢊ
0IN ꢁꢂꢀ ꢇ $1ꢂꢂ
0IN ꢁꢂꢂ ꢇ 633
0IN ꢁꢂꢅ ꢇ $13ꢈ
0IN ꢁꢈꢃ ꢇ $1ꢂꢄ
0IN ꢁꢈꢄ ꢇ 633
0IN ꢁꢄꢀ ꢇ $1ꢈꢆ
0IN ꢁꢄꢂ ꢇ #+ꢁ
0IN ꢁꢄꢅ ꢇ 633
0IN ꢁꢉꢃ ꢇ 633
0IN ꢁꢉꢄ ꢇ $1ꢈꢈ
$1ꢆꢆ ꢇ 0IN ꢁꢃꢈ
$13ꢂ ꢇ 0IN ꢁꢃꢊ
633 ꢇ 0IN ꢁꢆꢆ
$13ꢂ ꢇ 0IN ꢁꢆꢁ
$1ꢆꢂ ꢇ 0IN ꢁꢆꢈ
633 ꢇ 0IN ꢁꢆꢊ
$1ꢆꢈ ꢇ 0IN ꢁꢆꢉ
$1ꢂꢀ ꢇ 0IN ꢁꢂꢁ
633 ꢇ 0IN ꢁꢂꢈ
$1ꢂꢁ ꢇ 0IN ꢁꢂꢆ
$-ꢈ ꢇ 0IN ꢁꢂꢉ
$1ꢂꢃ ꢇ 0IN ꢁꢈꢁ
633 ꢇ 0IN ꢁꢈꢈ
633 ꢇ 0IN ꢁꢂꢊ
$1ꢂꢆ ꢇ 0IN ꢁꢈꢆ
$1ꢂꢅ ꢇ 0IN ꢁꢈꢉ
633 ꢇ 0IN ꢁꢄꢁ
$1ꢂꢊ ꢇ 0IN ꢁꢈꢊ
.# ꢇ 0IN ꢁꢄꢆ
633 ꢇ 0IN ꢁꢄꢈ
$13ꢄ ꢇ 0IN ꢁꢄꢉ
633 ꢇ 0IN ꢁꢉꢁ
$13ꢄ ꢇ 0IN ꢁꢄꢊ
$1ꢈꢀ ꢇ 0IN ꢁꢉꢆ
$1ꢈꢁ ꢇ 0IN ꢁꢉꢈ
633 ꢇ 0IN ꢁꢉꢉ
$1ꢈꢉ ꢇ 0IN ꢁꢅꢁ
0IN ꢁꢉꢅ ꢇ 633
0IN ꢁꢅꢃ ꢇ $1ꢄꢁ
$1ꢈꢄ ꢇ 0IN ꢁꢉꢊ
633 ꢇ 0IN ꢁꢅꢆ
0IN ꢁꢅꢀ ꢇ $1ꢄꢀ
0IN ꢁꢅꢂ ꢇ 633
$-ꢉ ꢇ 0IN ꢁꢅꢈ
$1ꢈꢅ ꢇ 0IN ꢁꢅꢊ
633 ꢇ 0IN ꢁꢊꢆ
0IN ꢁꢅꢄ ꢇ $13ꢉ
0IN ꢁꢊꢀ ꢇ 633
633 ꢇ 0IN ꢁꢅꢉ
$1ꢈꢊ ꢇ 0IN ꢁꢊꢁ
3$! ꢇ 0IN ꢁꢊꢈ
0IN ꢁꢅꢅ ꢇ $13ꢉ
0IN ꢁꢊꢃ ꢇ $1ꢄꢃ
0IN ꢁꢊꢄ ꢇ 633
0IN ꢁꢊꢂ ꢇ $1ꢄꢆ
0IN ꢁꢊꢅ ꢇ 3!ꢀ
3#, ꢇ 0IN ꢁꢊꢉ
6$$ 30$ ꢇ 0IN ꢁꢊꢊ
0IN ꢃꢀꢀ ꢇ 3!ꢁ
-004ꢀꢁꢂꢀ
Figure 1
Pin Configuration SO-DIMM (200 Pin)
Data Sheet
14
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Pin Configurations and Block Diagrams
2.2
Block Diagrams
"!ꢀ ꢋ "!ꢁ
"!ꢀ ꢋ "!ꢁꢌ 3$2!-S $ꢀ ꢋ $ꢇ
6$$ꢍ30$
6$$ꢊ6$$1
6$$ꢌ 30$ %%02/- %ꢀ
6$$ꢊ6$$1ꢌ 3$2!-S $ꢀ ꢋ $ꢇ
62%&ꢌ 3$2!-S $ꢀ ꢋ $ꢇ
633ꢌ 3$2!-S $ꢀ ꢋ $ꢇ
!ꢀ ꢋ !N
2!3
#!3
7%
!ꢀ ꢋ !Nꢌ 3$2!-S $ꢀ ꢋ $ꢇ
2!3ꢌ 3$2!-S $ꢀ ꢋ $ꢇ
#!3ꢌ 3$2!-S $ꢀ ꢋ $ꢇ
7%ꢌ 3$2!-S $ꢀ ꢋ $ꢇ
62%&
633
#+%ꢀ
#+%ꢁ
/$4ꢀ
/$4ꢁ
#+ꢀ
#+ꢀ
#+ꢁ
#+ꢁ
#+%ꢀꢌ 3$2!-S $ꢀ ꢋ $ꢄ
#+%ꢁꢌ 3$2!-S $ꢅ ꢋ $ꢇ
/$4ꢀꢌ 3$2!-S $ꢀ ꢋ $ꢄ
/$4ꢁꢌ 3$2!-S $ꢅ ꢋ $ꢇ
%ꢀ
3#,
3$!
!ꢀ
3#,
3$!
3!ꢀ
3!ꢁ
!ꢁ
ꢅ LOADS
ꢅ LOADS
!ꢃ
70
6SS
3ꢀ
3ꢁ
$ꢃ
$ꢀ
$ꢅ
$ꢂ
$-ꢀ
$13ꢀ
$13ꢀ
$1ꢀ
,$- #3
,$13
,$13
)ꢊ/ ꢀ
,$- #3
,$13
,$13
)ꢊ/ ꢀ
$-ꢅ
$13ꢅ
$13ꢅ
$1ꢄꢃ
$1ꢄꢄ
$1ꢄꢅ
$1ꢄꢆ
$1ꢄꢂ
$1ꢄꢇ
$1ꢄꢈ
$1ꢄꢉ
$-ꢆ
$13ꢆ
$13ꢆ
$1ꢅꢀ
$1ꢅꢁ
$1ꢅꢃ
$1ꢅꢄ
$1ꢅꢅ
$1ꢅꢆ
$1ꢅꢂ
$1ꢅꢇ
,$- #3
,$- #3
,$13
,$13
)ꢊ/ ꢀ
,$13
,$13
)ꢊ/ ꢀ
)ꢊ/ ꢁ
)ꢊ/ ꢃ
)ꢊ/ ꢄ
)ꢊ/ ꢅ
)ꢊ/ ꢆ
)ꢊ/ ꢂ
)ꢊ/ ꢇ
5$-
5$13
5$13
)ꢊ/ꢈ
$1ꢁ
)ꢊ/ ꢁ
)ꢊ/ ꢁ
)ꢊ/ ꢁ
$1ꢃ
)ꢊ/ ꢃ
)ꢊ/ ꢃ
)ꢊ/ ꢃ
$1ꢄ
)ꢊ/ ꢄ
)ꢊ/ ꢄ
)ꢊ/ ꢄ
$1ꢅ
)ꢊ/ ꢅ
)ꢊ/ ꢅ
)ꢊ/ ꢅ
$1ꢆ
)ꢊ/ ꢆ
)ꢊ/ ꢆ
)ꢊ/ ꢆ
$1ꢂ
)ꢊ/ ꢂ
)ꢊ/ ꢂ
)ꢊ/ ꢂ
$1ꢇ
)ꢊ/ ꢇ
)ꢊ/ ꢇ
)ꢊ/ ꢇ
$-ꢁ
5$-
5$13
5$13
)ꢊ/ꢈ
5$-
5$13
5$13
)ꢊ/ꢈ
5$-
5$13
5$13
)ꢊ/ꢈ
$13ꢁ
$13ꢁ
$1ꢈ
$1ꢉ
)ꢊ/ꢉ
)ꢊ/ꢉ
)ꢊ/ꢉ
)ꢊ/ꢉ
$1ꢁꢀ
$1ꢁꢁ
$1ꢁꢃ
$1ꢁꢄ
$1ꢁꢅ
$1ꢁꢆ
)ꢊ/ꢁꢀ
)ꢊ/ꢁꢁ
)ꢊ/ꢁꢃ
)ꢊ/ꢁꢄ
)ꢊ/ꢁꢅ
)ꢊ/ꢁꢆ
)ꢊ/ꢁꢀ
)ꢊ/ꢁꢁ
)ꢊ/ꢁꢃ
)ꢊ/ꢁꢄ
)ꢊ/ꢁꢅ
)ꢊ/ꢁꢆ
)ꢊ/ꢁꢀ
)ꢊ/ꢁꢁ
)ꢊ/ꢁꢃ
)ꢊ/ꢁꢄ
)ꢊ/ꢁꢅ
)ꢊ/ꢁꢆ
)ꢊ/ꢁꢀ
)ꢊ/ꢁꢁ
)ꢊ/ꢁꢃ
)ꢊ/ꢁꢄ
)ꢊ/ꢁꢅ
)ꢊ/ꢁꢆ
$ꢁ
$ꢆ
$ꢄ
$ꢇ
$-ꢃ
$13ꢃ
$13ꢃ
$1ꢁꢂ
$1ꢁꢇ
$1ꢁꢈ
$1ꢁꢉ
$1ꢃꢀ
$1ꢃꢁ
$1ꢃꢃ
$1ꢃꢄ
$-ꢄ
$13ꢄ
$13ꢄ
$1ꢃꢅ
$1ꢃꢆ
$1ꢃꢂ
$1ꢃꢇ
$1ꢃꢈ
$1ꢃꢉ
$1ꢄꢀ
$1ꢄꢁ
,$- #3
,$13
,$13
)ꢊ/ ꢀ
,$- #3
,$13
,$13
)ꢊ/ ꢀ
$-ꢂ
$13ꢂ
$13ꢂ
$1ꢅꢈ
$1ꢅꢉ
$1ꢆꢀ
$1ꢆꢁ
$1ꢆꢃ
$1ꢆꢄ
$1ꢆꢅ
$1ꢆꢆ
$-ꢇ
$13ꢇ
$13ꢇ
$1ꢆꢂ
$1ꢆꢇ
$1ꢆꢈ
$1ꢆꢉ
$1ꢂꢀ
$1ꢂꢁ
$1ꢂꢃ
$1ꢂꢄ
,$- #3
,$13
,$13
)ꢊ/ ꢀ
,$- #3
,$13
,$13
)ꢊ/ ꢀ
)ꢊ/ ꢁ
)ꢊ/ ꢁ
)ꢊ/ ꢁ
)ꢊ/ ꢁ
)ꢊ/ ꢃ
)ꢊ/ ꢃ
)ꢊ/ ꢃ
)ꢊ/ ꢃ
)ꢊ/ ꢄ
)ꢊ/ ꢄ
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Figure 2
Block Diagram Raw Card A SO-DIMM (×64, 2 Ranks, ×16)
Notes
2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
1. DQ, DQS, DM resistors are 22 Ω ±5 %
Data Sheet
15
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Pin Configurations and Block Diagrams
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Figure 3
Block Diagram Raw Card C SO-DIMM (×64, 1Rank, ×16)
Note:
2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
1. DQ, DQS, DM resistors are 22 Ω ±5 %
Data Sheet
16
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Pin Configurations and Block Diagrams
Figure 4
Block Diagram Raw Card E SO-DIMM (×64, 2 Ranks, ×8)
Notes
2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
1. DQ, DQS, DM resistors are 22 Ω ±5 %
Data Sheet
17
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
3
Electrical Characteristics
3.1
Absolute Maximum Ratings
Table 9
Parameter
Absolute Maximum Ratings
Symbol
Values
Min.
– 0.5
– 1.0
– 0.5
5
Unit
Note/Test
Condition
1)
Max.
2.3
2.3
2.3
95
Voltage on any pins relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
VIN, VOUT
VDD
VDDQ
V
V
V
%
1)
1)
1)
Storage Humidity (without condensation) HSTG
1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
3.2
DC Operating Conditions
Table 10
Operating Conditions
Parameter
Symbol
Values
Min.
0
Unit
Notes
Max.
+65
+95
+100
+105
90
Operating temperature (ambient)
DRAM Case Temperature
Storage Temperature
Barometric Pressure (operating & storage)
Operating Humidity (relative)
TOPR
TCASE
TSTG
PBar
HOPR
°C
°C
°C
kPa
%
1)2)3)4)
5)
0
– 50
+69
10
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs
4) For Self Refresh Operation above 85°C it is necessary to set extended mode register 2 (EMR(2)) Bit A7 to "1" to enable
the High Temperature Self Refresh option.
5) Up to 3000 m.
Data Sheet
18
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 11
Symbol
Recommended DC Operating Conditions (SSTL_18)
Parameter
Rating
Min.
Unit
Notes
Typ.
1.8
Max.
1.9
1.9
1.9
0.51 × VDDQ
1)
VDD
Supply Voltage
1.7
V
V
V
V
V
1)
VDDDL
VDDQ
VREF
VTT
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.7
0.49 × VDDQ
1.8
1.8
0.5 × VDDQ
VREF
1)
2)3)
4)
V
REF – 0.04
VREF + 0.04
1) VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
2) The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF
is expected to be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
.
3) Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc)
4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in die dc level of VREF
.
3.3
AC Characteristics
3.3.1
Speed Grade Definitions
All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications(tCK = 5ns with
t
RAS = 40ns).
List of Speed Grade Definition tables:
•
•
•
Table 12 “Speed Grade Definition Speed Bins DDR2-800E” on Page 19
Table 13 “Speed Grade Definition Speed Bins for DDR2–667” on Page 20
Table 14 “Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400” on Page 20
Table 12
Speed Grade Definition Speed Bins DDR2-800E
Speed Grade
DDR2–800E
Unit
Note
IFX Sort Name
CAS-RCD-RP latencies
Parameter
–2.5
6–6–6
Min.
5
3.75
3
2.5
45
60
tCK
—
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
tCK
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
Max.
8
8
8
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
70000
—
—
15
15
Row Precharge Time
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode
Data Sheet
19
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI
.
Table 13
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade
DDR2–667C
–3
4–4–4
DDR2–667D
–3S
5–5–5
Unit
Note
IFX Sort Name
CAS-RCD-RP latencies
Parameter
tCK
—
ns
ns
ns
ns
ns
ns
ns
Symbol
tCK
tCK
Min.
5
Max.
8
Min.
5
Max.
8
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
3
8
3.75
3
8
8
tCK
3
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
45
57
12
12
70000
—
—
45
60
15
15
70000
—
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI
.
Table 14
Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400
Speed Grade
DDR2–533C
–3.7
4–4–4
DDR2–400B
–5
3–3–3
Unit
Note
IFX Sort Name
CAS-RCD-RP latencies
Parameter
tCK
—
ns
ns
ns
ns
ns
ns
ns
Symbol
tCK
tCK
Min.
5
Max.
8
Min.
5
Max.
8
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
3.75
3.75
45
8
8
5
8
tCK
5
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
40
55
15
15
70000
—
—
60
15
—
15
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode
Data Sheet
20
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI
.
3.3.2
AC Timing Parameters
List of Timing Parameters for DDR2-800, DDR2-667(Table 15), and DDR2-533, DDR2-400(Table 16)
Table 15
Parameter
Timing Parameter by Speed Grade - DDR2-800 & DDR2–667
Symbol
DDR2–800
Min.
DDR2–667
Min.
Unit Notes1)
Max.
Max.
DQ output access time from CK / tAC
–400
+400
–450
+450
ps
CK
CAS A to CAS B command period tCCD
2
0.45
3
—
0.55
—
2
0.45
3
—
0.55
—
tCK
tCK
tCK
CK, CK high-level width
tCH
CKE minimum high and low pulse tCKE
width
CK, CK low-level width
Auto-Precharge write recovery +
precharge time
tCL
tDAL
0.45
WR + tRP
0.55
—
0.45
WR + tRP
0.55
—
tCK
tCK
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
tDELAY
tIS + tCK
+
––
tIS + tCK
+
—
ns
tIH
tIH
DQ and DM input hold time
(differential data strobe)
tDH(base) 125
––
175
––
––
ps
ps
tCK
ps
tCK
ps
DQ and DM input hold time (single tDH1(base) ––
—
—
ended data strobe)
DQ and DM input pulse width (each tDIPW
0.35
—
0.35
–400
0.35
—
—
input)
DQS output access time from CK / tDQSCK
–350
0.35
—
+350
—
+400
—
CK
DQS input low (high) pulse width
(write cycle)
DQS-DQ skew (for DQS &
associated DQ signals)
tDQSL,H
tDQSQ
200
240
Write command to 1st DQS latching tDQSS
WL –
0.25
WL + 0.25 WL – 0.25 WL + 0.25 tCK
transition
DQ and DM input setup time
(differential data strobe)
tDS(base) 50
—
—
—
—
100
––
—
—
—
—
ps
ps
tCK
tCK
DQ and DM input setup time (single tDS1(base) ––
ended data strobe)
DQS falling edge hold time from CK tDSH
0.2
0.2
0.2
0.2
(write cycle)
DQS falling edge to CK setup time tDSS
(write cycle)
Clock half period
Data Sheet
tHP
MIN. (tCL, tCH)
MIN. (tCL, tCH)
21
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 15
Parameter
Timing Parameter by Speed Grade - DDR2-800 & DDR2–667 (cont’d)
Symbol
DDR2–800
Min.
DDR2–667
Min.
Unit Notes1)
Max.
Max.
Data-out high-impedance time from tHZ
—
tAC.MAX
—
tAC.MAX
ps
CK / CK
Address and control input hold time tIH(base) 250
—
—
275
0.6
—
—
ps
tCK
Address and control input pulse
width
tIPW
0.6
(each input)
Address and control input setup
time
tIS(base) 175
—
200
—
ps
ps
DQ low-impedance time from CK / tLZ(DQ)
2 ×
tAC.MIN
tAC.MAX
2 ×
tAC.MIN
tAC.MAX
CK
DQS low-impedance from CK / CK tLZ(DQS)
tAC.MIN
2
tAC.MAX
—
tAC.MIN
2
tAC.MAX
—
ps
tCK
Mode register set command cycle tMRD
time
OCD drive mode output delay
Data output hold time from DQS
tOIT
tQH
0
12
—
0
12
—
ns
tHP–tQHS
tHPQ
–
tQHS
Data hold skew factor
Average periodic refresh Interval
tQHS
tREFI
—
—
—
300
7.8
3.9
—
—
—
—
105
340
7.8
3.9
—
ps
µs
µs
ns
2)
3)
Auto-Refresh to Active/Auto-
Refresh command period
tRFC
105
Precharge-All (4 banks) command tRP
t
RP + 1tCK
—
tRP + 1tCK
—
ns
period
Read preamble
Read postamble
Active bank A to Active bank B
command period
tRPRE
tRPST
tRRD
0.9
0.40
7.5
10
7.5
1.1
0.60
—
—
—
0.9
0.40
7.5
10
1.1
0.60
—
—
—
tCK
tCK
ns
ns
ns
Internal Read to Precharge
command delay
tRTP
7.5
Write preamble
Write postamble
tWPRE
tWPST
0.35 x tCK
0.40
15
—
0.60
—
0.35 x tCK
0.40
15
—
0.60
—
tCK
tCK
ns
Write recovery time for write without tWR
Auto-Precharge
4)
Write recovery time for write with
Auto-Precharge
WR
t
WR/tCK
tWR/tCK
tCK
Internal Write to Read command
delay
Exit power down to any valid
command
(other than NOP or Deselect)
tWTR
tXARD
7.5
2
—
—
7.5
2
—
—
ns
tCK
Exit active power-down mode to
Read command (slow exit, lower
power)
tXARDS
8 – AL
—
7 – AL
—
tCK
Data Sheet
22
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 15
Parameter
Timing Parameter by Speed Grade - DDR2-800 & DDR2–667 (cont’d)
Symbol
DDR2–800
DDR2–667
Unit Notes1)
Min.
Max.
Min.
Max.
Exit precharge power-down to any tXP
valid command (other than NOP or
Deselect)
2
—
2
—
tCK
Exit Self-Refresh to non-Read
command
Exit Self-Refresh to Read
command
tXSNR
t
RFC +10
—
—
t
RFC +10
—
—
ns
tXSRD
200
200
tCK
1) For details and notes see the relevant INFINEON component data sheet
2) 0 ≤ TCASE ≤ 85 °C
3) 85 °C < TCASE ≤ 95 °C
4) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where
WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not
already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR
parameter stored in the MRS.
Data Sheet
23
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 16
Parameter
Timing Parameter by Speed Grade - DDR2-400 & DDR2-533
Symbol
DDR2–533
Min.
DDR2–400
Min.
Unit Notes1)
Max.
Max.
DQ output access time from CK / tAC
–500
+500
–600
+600
ps
CK
CAS A to CAS B command
period
tCCD
2
—
2
—
tCK
CK, CK high-level width
CKE minimum high and low
pulse width
tCH
tCKE
0.45
3
0.55
—
0.45
3
0.55
—
tCK
tCK
CK, CK low-level width
tCL
0.45
WR + tRP
0.55
—
0.45
WR + tRP
0.55
—
tCK
tCK
Auto-Precharge write recovery + tDAL
precharge time
Minimum time clocks remain ON tDELAY
after CKE asynchronously drops
LOW
tIS + tCK + tIH ––
tIS + tCK + tIH ––
ns
DQ and DM input hold time
(differential data strobe)
DQ and DM input hold time
(single ended data strobe)
DQ and DM input pulse width
(each input)
tDH(base) 225
––
275
–25
0.35
–500
0.35
—
––
ps
ps
tCK
ps
tCK
ps
t
DH1(base) –25
—
—
tDIPW
0.35
–450
0.35
—
—
—
DQS output access time from CK tDQSCK
+450
—
+500
—
/ CK
DQS input low (high) pulse width tDQSL,H
(write cycle)
DQS-DQ skew (for DQS &
associated DQ signals)
Write command to 1st DQS
latching transition
DQ and DM input setup time
(differential data strobe)
DQ and DM input setup time
(single ended data strobe)
tDQSQ
tDQSS
tDS(base) 100
DS1(base) –25
300
350
WL – 0.25 WL + 0.25 WL – 0.25
WL + 0.25 tCK
—
—
—
—
150
–25
0.2
0.2
—
—
—
—
ps
ps
tCK
tCK
t
DQS falling edge hold time from tDSH
0.2
0.2
CK (write cycle)
DQS falling edge to CK setup
time (write cycle)
tDSS
Clock half period
Data-out high-impedance time
from CK / CK
tHP
tHZ
MIN. (tCL, tCH)
—
MIN. (tCL, tCH)
—
tAC.MAX
tAC.MAX
ps
ps
tCK
Address and control input hold
time
tIH(base) 375
—
475
0.6
—
Address and control input pulse tIPW
0.6
—
—
width
(each input)
Data Sheet
24
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 16
Parameter
Timing Parameter by Speed Grade - DDR2-400 & DDR2-533 (cont’d)
Symbol
DDR2–533
Min.
DDR2–400
Min.
Unit Notes1)
Max.
Max.
Address and control input setup tIS(base) 250
—
350
—
ps
ps
ps
tCK
ns
time
DQ low-impedance time from CK tLZ(DQ)
2 ×
tAC.MIN
tAC.MAX
tAC.MAX
—
2 ×
tAC.MIN
tAC.MIN
tAC.MAX
tAC.MAX
—
/ CK
DQS low-impedance from CK / tLZ(DQS)
tAC.MIN
CK
Mode register set command
cycle time
OCD drive mode output delay
tMRD
tOIT
2
2
0
12
0
12
Data output hold time from DQS tQH
t
—
—
—
HP –tQHS
—
t
—
—
—
HP –tQHS
—
Data hold skew factor
tQHS
400
7.8
3.9
—
450
7.8
3.9
—
ps
µs
µs
ns
2)
Average periodic refresh Interval tREFI
3)
Auto-Refresh to Active/Auto-
Refresh command period
Precharge-All (4 banks)
command period
tRFC
tRP
105
105
tRP + 1tCK
—
t
RP + 1tCK
—
ns
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.40
7.5
10
7.5
1.1
0.60
—
—
—
0.9
0.40
7.5
10
1.1
0.60
—
—
—
tCK
tCK
ns
ns
ns
Active bank A to Active bank B tRRD
command period
Internal Read to Precharge
command delay
tRTP
7.5
Write preamble
Write postamble
Write recovery time for write
without Auto-Precharge
tWPRE
tWPST
tWR
0.25 x tCK
0.40
15
—
0.60
—
0.25 x tCK
0.40
15
—
0.60
—
tCK
tCK
ns
4)
Write recovery time for write with WR
Auto-Precharge
tWR/tCK
t
WR/tCK
tCK
Internal Write to Read command tWTR
7.5
2
—
—
10
2
—
—
ns
delay
Exit power down to any valid
command
tXARD
tCK
(other than NOP or Deselect)
Exit active power-down mode to tXARDS
Read command (slow exit, lower
power)
6 – AL
2
—
—
6 – AL
2
—
—
tCK
Exit precharge power-down to
any valid command (other than
NOP or Deselect)
tXP
tCK
Data Sheet
25
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 16
Parameter
Timing Parameter by Speed Grade - DDR2-400 & DDR2-533 (cont’d)
Symbol
DDR2–533
Min.
DDR2–400
Min.
Unit Notes1)
Max.
Max.
Exit Self-Refresh to non-Read
command
Exit Self-Refresh to Read
command
tXSNR
tXSRD
t
RFC +10
—
t
RFC +10
—
ns
200
—
200
—
tCK
1) For details and notes see the relevant INFINEON component data sheet
2) 0 ≤ TCASE ≤ 85 °C
3) 85 °C < TCASE ≤ 95 °C
4) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where
WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not
already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR
parameter stored in the MRS.
3.3.3
ODT AC Electrical Characteristics
List of ODT tables.
•
Table 17 “ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 and DDR2-800”
on Page 26
Table 18 “ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400” on Page 26
•
Table 17
ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 and DDR2-800
Symbol Parameter / Condition
Values
Min.
2
Unit
Note
Max.
2
tAOND
tAON
tAONPD
tAOFD
tAOF
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
tCK
ns
ns
tCK
ns
1)
tAC.MIN
t
AC.MAX + 0.7 ns
AC.MAX + 1 ns
t
AC.MIN + 2 ns 2 tCK +
t
2.5
tAC.MIN
2.5
2)
ODT turn-off
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency 3
ODT Power Down Exit Latency
tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns
—
—
tCK
tCK
8
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
max is when the ODT resistance is fully on. Both are measure from tAOND
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high
impedance. Both are measured from tAOFD
.
.
Table 18
ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400
Symbol Parameter / Condition
Values
Min.
2
Unit
Note
Max.
2
tAOND
tAON
tAONPD
tAOFD
tAOF
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
tCK
ns
ns
tCK
ns
1)
tAC.MIN
t
AC.MAX + 1 ns
AC.MAX + 1 ns
t
AC.MIN + 2 ns 2 tCK +
t
2.5
tAC.MIN
2.5
2)
ODT turn-off
tAC.MAX + 0.6 ns
tAOFPD
ODT turn-off (Power-Down Modes)
t
AC.MIN + 2 ns 2.5 tCK +
tAC.MAX + 1 ns ns
Data Sheet
26
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 18
ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400 (cont’d)
Symbol Parameter / Condition
Values
Min.
Unit
Note
Max.
—
—
tANPD
tAXPD
ODT to Power Down Mode Entry Latency 3
ODT Power Down Exit Latency
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
tCK
tCK
8
max is when the ODT resistance is fully on. Both are measure from tAOND
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high
impedance. Both are measured from tAOFD
.
.
3.4
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions.
•
•
•
•
•
•
Table 19 “IDD Measurement Conditions” on Page 27
Table 21 “IDD Specification for HYS64T[32/64/128]xxxHDL–2.5–B” on Page 30
Table 22 “IDD Specification for HYS64T[32/64/128]xxxHDL–3–B” on Page 31
Table 23 “IDD Specification for HYS64T[32/64/128]xxxHDL–3S–B” on Page 32
Table 24 “IDD Specification for HYS64T[32/64/128]xxxHDL–3.7–B” on Page 33
Table 25 “IDD Specification for HYS64T[32/64/128]xxxHDL–5–B” on Page 34
Table 19
I
DD Measurement Conditions 1)2)3)4)5)6)
Parameter
Symbol
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH
between valid commands. Address and control inputs are SWITCHING, Databus inputs are
SWITCHING.
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING.
Precharge Power-Down Current
IDD2P
IDD2Q
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Standby Current
IDD3N
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Active Power-Down Current
IDD3P(0)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
IDD3P(1)
Data Sheet
27
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 19
I
DD Measurement Conditions (cont’d)1)2)3)4)5)6)
Parameter
Symbol
Operating Current
IDD4W
urst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
IDD5B
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
IDD5D
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
28
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 19
I
DD Measurement Conditions (cont’d)1)2)3)4)5)6)
Parameter
Symbol
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 20
4) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to
HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6) For details and notes see the relevant INFINEON component data sheet
Table 20
Parameter
LOW
Definitions for IDD
Description
V
IN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
STABLE
FLOATING
inputs are stable at a HIGH or LOW level
inputs are VREF = VDDQ /2
SWITCHING inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address
and control signals, and inputs changing between HIGH and LOW every other data transfer (once
per cycle) for DQ signals not including mask or strobes
Data Sheet
29
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 21
Product Type
IDD Specification for HYS64T[32/64/128]xxxHDL–2.5–B
Unit
Note1)
Organization
256 MB
1 Rank
×64
–2.5
Max.
400
460
30
512 MB
2 Ranks
×64
–2.5
Max.
430
490
60
1 GB
2 Ranks
×64
–2.5
Max.
700
Symbol
IDD0
IDD1
2)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
820
110
3)
IDD2P
3)
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
200
180
160
40
240
720
800
580
40
410
360
310
70
480
750
830
610
70
820
720
620
140
3)
3)
3)
3)
960
2)
1300
1300
1220
140
2)
2)
3)4)
3)4)
2)
IDD6
20
1020
40
1050
80
1340
IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) These values are for 0°C ≤ TCase ≤ 85°C
Data Sheet
30
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 22
Product Type
IDD Specification for HYS64T[32/64/128]xxxHDL–3–B
Unit
Note1)
Organization
256 MB
1 Rank
×64
–3
512 MB
2 Ranks
×64
–3
1 GB
2 Ranks
×64
–33
Symbol
IDD0
IDD1
IDD2P
IDD2N
Max.
380
420
30
180
160
130
40
200
620
680
560
40
Max.
410
450
60
360
320
260
70
400
650
710
590
70
Max.
660
780
110
720
640
530
140
800
1100
1100
1180
140
80
1340
2)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
3)
3)
3)
IDD2Q
3)
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
3)
3)
2)
2)
2)
3)4)
3)4)
2)
20
1010
40
1040
IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) These values are for 0 °C ≤ TCase ≤ 85 °C.
Data Sheet
31
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 23
Product Type
IDD Specification for HYS64T[32/64/128]xxxHDL–3S–B
Unit
Note1)
Organization
256 MB
1 Rank
×64
–3S
Max.
360
400
30
512 MB
2 Ranks
×64
–3S
Max.
390
430
60
1 GB
2 Ranks
×64
–3S
Max.
620
Symbol
IDD0
IDD1
2)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
740
110
3)
IDD2P
3)
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
180
160
130
40
200
620
680
560
40
360
320
260
70
400
650
710
590
70
720
640
530
140
3)
3)
3)
3)
800
2)
1100
1100
1180
140
2)
2)
3)4)
3)4)
2)
IDD6
20
960
40
990
80
1270
IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) These values are for 0 °C ≤ TCase ≤ 85 °C.
Data Sheet
32
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 24
Product Type
IDD Specification for HYS64T[32/64/128]xxxHDL–3.7–B
Unit
Note1)
Organization
256 MB
1 Rank
×64
–3.7
Max.
320
360
30
512 MB
2 Ranks
×64
–3.7
Max.
350
390
60
1 GB
2 Ranks
×64
–3.7
Max.
580
Symbol
IDD0
IDD1
2)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
660
110
3)
IDD2P
3)
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
150
140
110
40
170
520
580
520
40
300
280
220
70
340
550
610
550
70
610
560
450
140
690
940
940
1100
140
3)
3)
3)
3)
2)
2)
2)
3)4)
3)4)
2)
IDD6
20
920
40
950
80
1220
IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2)The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) These values are for 0 °C ≤ TCase ≤ 85 °C
Data Sheet
33
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 25
Product Type
IDD Specification for HYS64T[32/64/128]xxxHDL–5–B
Unit
Note1)
Organization
256 MB
1 Rank
×64
–5
512 MB
2 Ranks
×64
–5
1 GB
2 Ranks
×64
–5
Symbol
IDD0
IDD1
IDD2P
IDD2N
Max.
300
330
30
140
130
100
40
160
460
520
500
40
Max.
330
360
60
270
260
190
70
310
490
550
530
70
Max.
540
620
110
540
510
380
140
620
820
820
1060
140
80
2)
2)
3)
3)
3)
3)
3)
3)
2)
2)
2)
3)4)
3)
2)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
20
880
40
910
IDD7
1180
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) These values are for 0 °C ≤ TCase ≤ 85 °C.
Data Sheet
34
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
3.4.1
IDD Test Conditions
For testing the IDD parameters, the timing parameters as shown in the tables below are used.
•
•
•
•
•
Table 26 “IDD Measurement Test Condition for DDR2–800E” on Page 35
Table 27 “IDD Measurement Test Condition for DDR2–667C” on Page 35
Table 28 “IDD Measurement Test Condition for DDR2–667D” on Page 36
Table 29 “IDD Measurement Test Condition for DDR2–533C” on Page 36
Table 30 “IDD Measurement Test Condition for DDR2–400B” on Page 36
Table 26
IDD Measurement Test Condition for DDR2–800E
Parameter
Symbol
–2.5
Unit Notes
DDR2–800E
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay
CLIDD
6
tCK
ns
ns
ns
ns
ns
tCK.IDD
tRCD.IDD
tRC.IDD
tRRD.IDD
2.5
15
60
7.5
10
1)
2)
Active to Precharge Command
tRAS.MIN.IDD 45
tRAS.MAX.IDD 70000
ns
ns
ns
ns
µs
µs
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command period
Average periodic Refresh interval
tRP.IDD
tRFC.IDD
tREFI
15
105
7.8
3.9
0°C ≤ TCASE ≤ 85°C
85°C ≤ TCASE ≤ 95°C tREFI
1) ×4 & ×8 (1 kB page size)
2) ×16 (2 kB page size)
Table 27
IDD Measurement Test Condition for DDR2–667C
Parameter
Symbol
–3
Unit Notes
DDR2–667C
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay
CLIDD
4
3
12
57
7.5
10
tCK
ns
ns
ns
ns
ns
tCK.IDD
tRCD.IDD
tRC.IDD
tRRD.IDD
1)
2)
Active to Precharge Command
tRAS.MIN.IDD 45
tRAS.MAX.IDD 70000
ns
ns
ns
ns
µs
µs
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command period
Average periodic Refresh interval
tRP.IDD
tRFC.IDD
tREFI
12
105
7.8
3.9
0°C ≤ TCASE ≤ 85°C
85°C ≤ TCASE ≤ 95°C tREFI
1) ×4 & ×8 (1 kB page size)
2) ×16 (2 kB page size)
Data Sheet
35
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 28
IDD Measurement Test Condition for DDR2–667D
Parameter
Symbol
–3S
Unit Notes
DDR2–667D
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay
CLIDD
5
3
15
60
7.5
10
tCK
ns
ns
ns
ns
ns
tCK.IDD
tRCD.IDD
tRC.IDD
tRRD.IDD
1)
2)
Active to Precharge Command
tRAS.MIN.IDD 45
tRAS.MAX.IDD 70000
ns
ns
ns
ns
µs
µs
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command period
Average periodic Refresh interval
tRP.IDD
tRFC.IDD
tREFI
15
105
7.8
3.9
0°C ≤ TCASE ≤ 85°C
85°C ≤ TCASE ≤ 95°C tREFI
1) ×4 & ×8 (1 kB page size)
2) ×16 (2 kB page size)
Table 29
IDD Measurement Test Condition for DDR2–533C
Parameter
Symbol
–3.7
Unit Notes
DDR2–533C
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay
CLIDD
4
tCK
ns
ns
ns
ns
ns
tCK.IDD
tRCD.IDD
tRC.IDD
tRRD.IDD
3.75
15
60
7.5
10
1)
2)
Active to Precharge Command
tRAS.MIN.IDD 45
tRAS.MAX.IDD 7000
ns
ns
ns
ns
µs
µs
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command period
Average periodic Refresh interval
tRP.IDD
tRFC.IDD
tREFI
15
105
7.8
3.9
0°C ≤ TCASE ≤ 85°C
85°C ≤ TCASE ≤ 95°C tREFI
1) ×4 & ×8 (1 kB page size)
2) ×16 (2 kB page size)
Table 30
IDD Measurement Test Condition for DDR2–400B
Parameter
Symbol
–5
Unit Notes
DDR2–400B
CAS Latency
Clock Cycle Time
Active to Read or Write delay
CLIDD
tCK.IDD
tRCD.IDD
3
5
15
tCK
ns
ns
Data Sheet
36
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Electrical Characteristics
Table 30
IDD Measurement Test Condition for DDR2–400B
Parameter
Symbol
–5
Unit Notes
DDR2–400B
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay
tRC.IDD
tRRD.IDD
55
7.5
10
ns
ns
ns
1)
2)
Active to Precharge Command
tRAS.MIN.IDD 40
tRAS.MAX.IDD 7000
ns
ns
ns
ns
µs
µs
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command period
Average periodic Refresh interval
tRP.IDD
tRFC.IDD
tREFI
15
105
7.8
3.9
0°C ≤ TCASE ≤ 85°C
85°C ≤ TCASE ≤ 95°C tREFI
1) ×4 & ×8 (1 kB page size)
2) ×16 (2 kB page size)
3.4.2
On Die Termination (ODT) Current
The ODT function adds additional current consumption current consumption for any terminated input pin,
to the DDR2 SDRAM when enabled by the EMRS(1). depends on the input pin is in tri-state or driving 0 or 1,
Depending on address bits A[6,2] in the EMRS(1) a as long a ODT is enabled during a given period of time.
“weak” or “strong” termination can be selected. The
Table 31
ODT current per terminated pin
Parameter
Symbol Min.
Typ.
Max. Unit
EMRS(1) State
Enabled ODT current per DQ
IODTO
IODTT
5
6
3
12
6
7.5
mA/DQ A6 = 0, A2 = 1
ODT is HIGH; Data Bus inputs are FLOATING
2.5
10
5
3.75 mA/DQ A6 = 1, A2 = 0
15
7.5
Active ODT current per DQ
ODT is HIGH; worst case of Data Bus inputs are
STABLE or SWITCHING.
mA/DQ A6 = 0, A2 = 1
mA/DQ A6 = 1, A2 = 0
Note:For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
37
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet.
SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined
during production.
List of SPD Code Tables
•
•
•
•
•
Table 32 “SPD Codes for HYS64T[32/64/128]xxxHDL–2.5–B” on Page 38
Table 33 “SPD Codes for HYS64T[32/64/128]xxxHDL–3–B” on Page 42
Table 34 “SPD Codes for HYS64T[32/64/128]xxxHDL–3S–B” on Page 46
Table 35 “SPD Codes for HYS64T[32/64/128]xxxHDL–3.7–B” on Page 50
Table 36 “SPD Codes for HYS64T[32/64/128]xxxHDL–5–B” on Page 54
Table 32
SPD Codes for HYS64T[32/64/128]xxxHDL–2.5–B
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–
666
PC2–6400S–
666
PC2–6400S–
666
JEDEC SPD Revision
Rev. 1.2
HEX
80
08
08
0D
0A
60
Rev. 1.2
HEX
80
08
08
0D
0A
61
Rev. 1.2
HEX
80
08
08
0E
0A
61
Byte#
0
Description
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
1
2
3
4
5
6
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
25
25
25
10
11
12
13
14
15
t
AC SDRAM @ CLMAX (Byte 18) [ns]
40
00
82
10
00
00
40
00
82
10
00
00
40
00
82
08
00
00
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Data Sheet
38
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 32
SPD Codes for HYS64T[32/64/128]xxxHDL–2.5–B (cont’d)
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–
666
PC2–6400S–
666
PC2–6400S–
666
JEDEC SPD Revision
Rev. 1.2
HEX
0C
04
70
01
04
00
07
30
45
3D
50
3C
28
3C
2D
40
15
22
05
12
Rev. 1.2
HEX
0C
04
70
01
04
00
07
30
45
3D
50
3C
28
3C
2D
40
15
22
05
12
Rev. 1.2
HEX
0C
04
70
01
04
00
07
30
45
3D
50
3C
1E
3C
2D
80
15
22
05
12
Byte#
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Description
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
3C
1E
1E
00
00
3C
69
3C
1E
1E
00
00
3C
69
3C
1E
1E
00
00
3C
69
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
Data Sheet
39
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 32
SPD Codes for HYS64T[32/64/128]xxxHDL–2.5–B (cont’d)
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–
666
PC2–6400S–
666
PC2–6400S–
666
JEDEC SPD Revision
Rev. 1.2
HEX
80
14
1E
00
55
72
6F
Rev. 1.2
HEX
80
14
1E
00
55
72
6F
37
33
2B
54
27
62
1F
37
00
00
00
00
Rev. 1.2
HEX
80
14
1E
00
Byte#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
Description
t
t
t
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / ∆T4R4W Delta
50
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 37
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2)
JEDEC ID Code of Infineon (3)
JEDEC ID Code of Infineon (4)
JEDEC ID Code of Infineon (5)
JEDEC ID Code of Infineon (6)
7A
5B
3B
36
2E
5A
2A
5A
22
25
00
00
00
00
12
26
C1
00
00
00
00
00
33
2B
54
27
62
1F
37
00
00
00
00
12
0B
C1
00
00
00
00
00
12
0C
C1
00
00
00
00
00
Data Sheet
40
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 32
SPD Codes for HYS64T[32/64/128]xxxHDL–2.5–B (cont’d)
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–
666
PC2–6400S–
666
PC2–6400S–
666
JEDEC SPD Revision
Rev. 1.2
HEX
00
00
xx
36
34
54
33
32
30
30
30
48
44
4C
32
2E
35
42
20
20
20
1x
xx
xx
xx
Rev. 1.2
HEX
00
00
xx
36
34
54
36
34
30
32
30
48
44
4C
32
2E
35
42
20
20
20
1x
xx
xx
xx
Rev. 1.2
HEX
00
00
xx
36
34
54
31
32
38
30
32
31
48
44
4C
32
2E
35
42
20
20
1x
xx
xx
xx
Byte#
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Description
JEDEC ID Code of Infineon (7)
JEDEC ID Code of Infineon (8)
Module Manufacturer Location
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
xx
00
xx
00
xx
00
Data Sheet
41
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 33
SPD Codes for HYS64T[32/64/128]xxxHDL–3–B
Product Type
Organization
Label Code
256 MB
×64
1 Rank (×16)
PC2–5300S–
444
512 MB
×64
2 Ranks (×16)
PC2–5300S–
444
1 GByte
×64
2 Ranks (×8)
PC2–5300S–
444
JEDEC SPD Revision
Byte# Description
Rev. 1.2
HEX
80
Rev. 1.2
HEX
80
Rev. 1.2
HEX
80
0
Programmed SPD Bytes in EEPROM
1
2
3
4
5
6
Total number of Bytes in EEPROM
Memory Type (DDR2)
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
08
08
0D
0A
60
08
08
0D
0A
61
08
08
0E
0A
61
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
t
t
CK @ CLMAX (Byte 18) [ns]
AC SDRAM @ CLMAX (Byte 18) [ns]
30
45
00
82
10
00
00
0C
04
38
01
04
00
07
30
45
50
30
45
00
82
10
00
00
0C
04
38
01
04
00
07
30
45
50
30
45
00
82
08
00
00
0C
04
38
01
04
00
07
30
45
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
60
60
60
Data Sheet
42
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 33
SPD Codes for HYS64T[32/64/128]xxxHDL–3–B (cont’d)
Product Type
Organization
Label Code
256 MB
×64
1 Rank (×16)
PC2–5300S–
444
512 MB
×64
2 Ranks (×16)
PC2–5300S–
444
1 GByte
×64
2 Ranks (×8)
PC2–5300S–
444
JEDEC SPD Revision
Byte# Description
Rev. 1.2
HEX
30
28
30
2D
40
20
27
10
Rev. 1.2
HEX
30
28
30
2D
40
20
27
10
Rev. 1.2
HEX
30
1E
30
2D
80
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
00
50
7A
53
34
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
t
t
t
t
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
17
17
3C
1E
1E
00
00
39
69
80
18
22
3C
1E
1E
00
00
39
69
80
18
22
00
54
72
67
31
33
24
47
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 31
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
00
54
72
67
CASE.MAX Delta / ∆T4R4W Delta
33
24
47
36
27
4C
Data Sheet
43
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 33
SPD Codes for HYS64T[32/64/128]xxxHDL–3–B (cont’d)
Product Type
Organization
Label Code
256 MB
×64
1 Rank (×16)
PC2–5300S–
444
512 MB
×64
2 Ranks (×16)
PC2–5300S–
444
1 GByte
×64
2 Ranks (×8)
PC2–5300S–
444
JEDEC SPD Revision
Byte# Description
Rev. 1.2
HEX
27
54
1E
37
00
00
00
00
Rev. 1.2
HEX
27
54
1E
37
00
00
00
00
Rev. 1.2
HEX
2A
4C
20
25
00
00
00
00
12
FA
C1
00
00
00
00
00
00
00
xx
36
34
54
31
32
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2)
JEDEC ID Code of Infineon (3)
JEDEC ID Code of Infineon (4)
JEDEC ID Code of Infineon (5)
JEDEC ID Code of Infineon (6)
JEDEC ID Code of Infineon (7)
JEDEC ID Code of Infineon (8)
Module Manufacturer Location
Product Type, Char 1
12
12
E1
C1
00
00
00
00
00
00
00
xx
36
34
54
33
32
30
30
E2
C1
00
00
00
00
00
00
00
xx
36
34
54
36
34
30
32
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
38
30
32
30
30
Data Sheet
44
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 33
SPD Codes for HYS64T[32/64/128]xxxHDL–3–B (cont’d)
Product Type
Organization
Label Code
256 MB
×64
1 Rank (×16)
PC2–5300S–
444
512 MB
×64
2 Ranks (×16)
PC2–5300S–
444
1 GByte
×64
2 Ranks (×8)
PC2–5300S–
444
JEDEC SPD Revision
Byte# Description
Rev. 1.2
HEX
48
44
4C
33
42
20
20
20
20
20
1x
xx
xx
xx
Rev. 1.2
HEX
48
44
4C
33
42
20
20
20
20
20
1x
xx
xx
xx
Rev. 1.2
HEX
31
48
44
4C
33
42
20
20
20
20
2x
xx
xx
xx
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
xx
xx
xx
99 -
127
Not used
00
00
00
Data Sheet
45
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 34
SPD Codes for HYS64T[32/64/128]xxxHDL–3S–B
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16) 2 Ranks (×8)
Label Code
PC2–5300S–
555
PC2–5300S–
555
PC2–5300S–
555
JEDEC SPD Revision
Rev. 1.2
HEX
80
08
08
0D
0A
60
Rev. 1.2
HEX
80
08
08
0D
0A
61
Rev. 1.2
HEX
80
08
08
0E
0A
61
Byte#
0
Description
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
1
2
3
4
5
6
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
t
t
CK @ CLMAX (Byte 18) [ns]
AC SDRAM @ CLMAX (Byte 18) [ns]
30
45
00
82
10
00
00
0C
04
38
01
04
00
07
3D
50
30
45
00
82
10
00
00
0C
04
38
01
04
00
07
3D
50
30
45
00
82
08
00
00
0C
04
38
01
04
00
07
3D
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
50
50
50
Data Sheet
46
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 34
SPD Codes for HYS64T[32/64/128]xxxHDL–3S–B (cont’d)
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16) 2 Ranks (×8)
Label Code
PC2–5300S–
555
PC2–5300S–
555
PC2–5300S–
555
JEDEC SPD Revision
Rev. 1.2
HEX
60
3C
28
3C
2D
40
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
00
Rev. 1.2
HEX
60
3C
28
3C
2D
40
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
00
Rev. 1.2
HEX
60
3C
1E
3C
2D
80
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
00
Byte#
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Description
t
t
t
t
t
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
T
CASE.MAX Delta / ∆T4R4W Delta
54
72
5F
54
72
5F
31
33
50
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 31
∆T2P (DT2P)
∆T3N (DT3N)
7A
4B
34
36
27
33
24
24
Data Sheet
47
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 34
SPD Codes for HYS64T[32/64/128]xxxHDL–3S–B (cont’d)
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16) 2 Ranks (×8)
Label Code
PC2–5300S–
555
PC2–5300S–
555
PC2–5300S–
555
JEDEC SPD Revision
Rev. 1.2
HEX
47
27
54
1E
34
00
00
00
00
12
09
C1
00
00
00
00
00
00
00
xx
36
34
54
33
32
Rev. 1.2
HEX
47
27
54
1E
34
00
00
00
00
12
0A
C1
00
00
00
00
00
00
00
xx
36
34
54
36
34
Rev. 1.2
HEX
4C
2A
4C
20
23
00
00
00
00
12
23
C1
00
00
00
00
00
00
00
xx
36
34
54
31
32
Byte#
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
Description
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2)
JEDEC ID Code of Infineon (3)
JEDEC ID Code of Infineon (4)
JEDEC ID Code of Infineon (5)
JEDEC ID Code of Infineon (6)
JEDEC ID Code of Infineon (7)
JEDEC ID Code of Infineon (8)
Module Manufacturer Location
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
30
30
30
32
38
30
Data Sheet
48
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 34
SPD Codes for HYS64T[32/64/128]xxxHDL–3S–B (cont’d)
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16) 2 Ranks (×8)
Label Code
PC2–5300S–
555
PC2–5300S–
555
PC2–5300S–
555
JEDEC SPD Revision
Rev. 1.2
HEX
30
48
44
4C
33
53
42
20
20
20
20
2x
xx
xx
xx
Rev. 1.2
HEX
30
48
44
4C
33
53
42
20
20
20
20
2x
xx
xx
xx
Rev. 1.2
HEX
32
31
48
44
4C
33
53
42
20
20
20
2x
xx
xx
xx
Byte#
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Description
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 89 Module Serial Number
99 - 127 Not used
xx
00
xx
00
xx
00
Data Sheet
49
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 35
SPD Codes for HYS64T[32/64/128]xxxHDL–3.7–B
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–
444
PC2–4200S–
444
PC2–4200S–
444
JEDEC SPD Revision
Rev. 1.2
HEX
80
08
08
0D
0A
60
Rev. 1.2
HEX
80
08
08
0D
0A
61
Rev. 1.2
HEX
80
08
08
0E
0A
61
Byte#
0
Description
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
1
2
3
4
5
6
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
t
CK @ CLMAX (Byte 18) [ns]
3D
50
00
82
10
00
00
0C
04
38
01
04
00
07
3D
50
50
3D
50
00
82
10
00
00
0C
04
38
01
04
00
07
3D
50
50
3D
50
00
82
08
00
00
0C
04
38
01
04
00
07
3D
50
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
Data Sheet
50
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 35
SPD Codes for HYS64T[32/64/128]xxxHDL–3.7–B (cont’d)
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–
444
PC2–4200S–
444
PC2–4200S–
444
JEDEC SPD Revision
Rev. 1.2
HEX
60
3C
28
3C
2D
40
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
00
54
Rev. 1.2
HEX
60
3C
28
3C
2D
40
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
00
54
Rev. 1.2
HEX
60
3C
1E
3C
2D
80
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
00
50
Byte#
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Description
t
t
t
t
t
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 29
∆T2P (DT2P)
∆T3N (DT3N)
72
53
72
53
29
33
7A
43
2C
36
33
1F
1F
21
Data Sheet
51
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 35
SPD Codes for HYS64T[32/64/128]xxxHDL–3.7–B (cont’d)
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–
444
PC2–4200S–
444
PC2–4200S–
444
JEDEC SPD Revision
Rev. 1.2
HEX
3D
27
46
1C
32
00
00
00
00
12
18
C1
00
00
00
00
00
00
Rev. 1.2
HEX
3D
27
46
1C
32
00
00
00
00
12
19
C1
00
00
00
00
00
00
Rev. 1.2
HEX
41
2A
40
1E
22
00
00
00
00
12
37
C1
00
00
00
00
00
00
00
Byte#
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
Description
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2)
JEDEC ID Code of Infineon (3)
JEDEC ID Code of Infineon (4)
JEDEC ID Code of Infineon (5)
JEDEC ID Code of Infineon (6)
JEDEC ID Code of Infineon (7)
JEDEC ID Code of Infineon (8)
Module Manufacturer Location
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
00
xx
36
34
54
33
32
30
00
xx
36
34
54
36
34
30
xx
36
34
54
31
32
38
30
30
32
Data Sheet
52
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 35
SPD Codes for HYS64T[32/64/128]xxxHDL–3.7–B (cont’d)
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–
444
PC2–4200S–
444
PC2–4200S–
444
JEDEC SPD Revision
Rev. 1.2
HEX
30
48
44
4C
33
2E
37
42
20
20
20
2x
xx
xx
xx
Rev. 1.2
HEX
30
48
44
4C
33
2E
37
42
20
20
20
2x
xx
xx
xx
Rev. 1.2
HEX
32
31
48
44
4C
33
2E
37
42
20
20
2x
xx
xx
xx
Byte#
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Description
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
xx
00
xx
00
xx
00
Data Sheet
53
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 36
SPD Codes for HYS64T[32/64/128]xxxHDL–5–B
Product Type
Organization
Label Code
256 MB
×64
1 Rank (×16)
PC2–3200S–
333
512 MB
×64
2 Ranks (×16)
PC2–3200S–
333
1 GByte
×64
2 Ranks (×8)
PC2–3200S–
333
JEDEC SPD Revision
Byte# Description
Rev. 1.2
HEX
80
Rev. 1.2
HEX
80
Rev. 1.2
HEX
80
0
Programmed SPD Bytes in EEPROM
1
2
3
4
5
6
Total number of Bytes in EEPROM
Memory Type (DDR2)
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
08
08
0D
0A
60
08
08
0D
0A
61
08
08
0E
0A
61
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
t
t
CK @ CLMAX (Byte 18) [ns]
AC SDRAM @ CLMAX (Byte 18) [ns]
50
60
00
82
10
00
00
0C
04
38
01
04
00
07
50
60
50
50
60
00
82
10
00
00
0C
04
38
01
04
00
07
50
60
50
50
60
00
82
08
00
00
0C
04
38
01
04
00
07
50
60
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
60
60
60
Data Sheet
54
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 36
SPD Codes for HYS64T[32/64/128]xxxHDL–5–B (cont’d)
Product Type
Organization
Label Code
256 MB
×64
1 Rank (×16)
PC2–3200S–
333
512 MB
×64
2 Ranks (×16)
PC2–3200S–
333
1 GByte
×64
2 Ranks (×8)
PC2–3200S–
333
JEDEC SPD Revision
Byte# Description
Rev. 1.2
HEX
3C
28
3C
28
40
35
47
15
27
3C
28
1E
00
00
37
69
80
23
Rev. 1.2
HEX
3C
28
3C
28
40
35
47
15
27
3C
28
1E
00
00
37
69
80
23
2D
00
54
72
4B
25
33
1C
34
Rev. 1.2
HEX
3C
1E
3C
28
80
35
47
15
27
3C
28
1E
00
00
37
69
80
23
2D
00
50
7A
3B
27
36
1E
38
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
t
t
t
t
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
2D
00
54
72
4B
PLL Relock Time
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 25
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
CASE.MAX Delta / ∆T4R4W Delta
33
1C
34
Data Sheet
55
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 36
SPD Codes for HYS64T[32/64/128]xxxHDL–5–B (cont’d)
Product Type
Organization
Label Code
256 MB
×64
1 Rank (×16)
PC2–3200S–
333
512 MB
×64
2 Ranks (×16)
PC2–3200S–
333
1 GByte
×64
2 Ranks (×8)
PC2–3200S–
333
JEDEC SPD Revision
Byte# Description
Rev. 1.2
HEX
27
3E
1B
30
00
00
00
00
Rev. 1.2
HEX
27
3E
1B
30
00
00
00
00
12
70
C1
00
00
00
00
00
00
00
xx
36
34
54
36
34
30
Rev. 1.2
HEX
2A
38
1D
21
00
00
00
00
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2)
JEDEC ID Code of Infineon (3)
JEDEC ID Code of Infineon (4)
JEDEC ID Code of Infineon (5)
JEDEC ID Code of Infineon (6)
JEDEC ID Code of Infineon (7)
JEDEC ID Code of Infineon (8)
Module Manufacturer Location
Product Type, Char 1
12
12
6F
C1
00
00
00
00
00
00
00
xx
36
34
54
33
32
30
30
8E
C1
00
00
00
00
00
00
00
xx
36
34
54
31
32
38
30
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
32
30
30
32
Data Sheet
56
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
SPD Codes
Table 36
SPD Codes for HYS64T[32/64/128]xxxHDL–5–B (cont’d)
Product Type
Organization
Label Code
256 MB
×64
1 Rank (×16)
PC2–3200S–
333
512 MB
×64
2 Ranks (×16)
PC2–3200S–
333
1 GByte
×64
2 Ranks (×8)
PC2–3200S–
333
JEDEC SPD Revision
Byte# Description
Rev. 1.2
HEX
48
44
4C
35
42
20
20
20
20
20
2x
xx
xx
xx
Rev. 1.2
HEX
48
44
4C
35
42
20
20
20
20
20
2x
xx
xx
xx
Rev. 1.2
HEX
31
48
44
4C
35
42
20
20
20
20
2x
xx
xx
xx
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
xx
00
xx
00
xx
00
Data Sheet
57
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Package Outlines
5
Package Outlines
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Figure 5
Package Outline Raw Card A L-DIM-200-31
Data Sheet
58
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Package Outlines
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Figure 6
Package Outline Raw Card C L-DIM-200-30
Data Sheet
59
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Package Outlines
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Figure 7
Package Outline Raw Card E L-DIM-200-36
Data Sheet
60
Rev 1.00, 2005-06
05122005-2TKP-OM7N
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
6
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon’s nomenclature uses simple coding combined with some propriatory coding. Table 37 provides examples
for module and component product type number as well as the field number. The detailed field description together
with possible values and coding explanation is listed for modules in Table 38 and for components in Table 39.
Table 37
Example for
Nomenclature Fields and Examples
Field Number
1
HYS
HYB
2
64
18
3
T
T
4
64
512
5
0
16
6
2
7
0
0
8
K
A
9
M
C
10
–5
–5
11
–A
Micro-DIMM
DDR2 DRAM
1) Multiplying “Memory Density per I/O” with “Module Data
Width” and dividing by 8 for Non-ECC and 9 for ECC
modules gives the overall module memory density in
MBytes as listed in column “Coding”.
Table 38
Field Description
DDR2 DIMM Nomenclature
Values Coding
1
INFINEON
Modul Prefix
HYS
Constant
2
Module Data
Width [bit]
64
72
T
Non-ECC
ECC
DDR2
Table 39
Field Description
DDR2 DRAM Nomenclature
Values Coding
3
4
DRAM
Technology
1
INFINEON
Component Prefix
HYB
Constant
Memory Density
per I/O [Mbit];
32
64
128
256
256 MByte
512 MByte
1 GByte
2 GByte
Look up table
2
3
4
Interface Voltage [V] 18
DRAM Technology
Component Density 256
[Mbit]
SSTL1.8
DDR2
256 Mbit
512 Mbit
1 Gbit
2 Gbit
×4
T
Module Density1)
512
1G
2G
5
6
Raw Card
Generation
Number of Module 0, 2, 4 1, 2, 4
Ranks
Product Variations 0 .. 9
Package,
Lead-Free Status
Module Type
0 .. 9
5+6 Number of I/Os
40
80
16
Product Variations 0 .. 9
×8
×16
7
8
Look up table
Look up table
A .. Z
7
8
Look up table
First
Die Revision
A
9
D
M
SO-DIMM
B
Second
Micro-DIMM
Registered
Unbuffered
PC2–4200 4–4–4
PC2–3200 3–3–3
First
9
Package,
Lead-Free Status
C
FBGA,
lead-containing
R
U
–3.7
–5
–A
–B
F
–3.7
–5
FBGA, lead-free
DDR2-533C
DDR2-400B
10
11
Speed Grade
Die Revision
10
11
Speed Grade
N/A for Components
Second
Data Sheet
61
Rev 1.00, 2005-06
05122005-2TKP-OM7N
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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