HYS64T128021HDL-3.7-A [QIMONDA]
DDR DRAM Module, 128MX64, 0.5ns, CMOS, PDMA200;
| 型号： | HYS64T128021HDL-3.7-A |
| 厂家： | 
QIMONDA AG |
| 描述： | DDR DRAM Module, 128MX64, 0.5ns, CMOS, PDMA200 时钟 动态存储器 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总39页 (文件大小：955K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.0, Oct. 2004
HYS64T32000HDL–[3.7/5]–A
HYS64T64020HDL–[3.7/5]–A
HYS64T128021HDL–[3.7/5]–A
200-Pin SO-DIMM DDR2 SDRAM Modules
DDR2 SDRAM
RoHS Compliant
Memory Products
N e v e r s t o p t h i n k i n g .
The information in this document is subject to change without notice.
Edition 2004-10
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, Rev. 1.0, Oct. 2004
HYS64T32000HDL–[3.7/5]–A
HYS64T64020HDL–[3.7/5]–A
HYS64T128021HDL–[3.7/5]–A
200-Pin SO-DIMM DDR2 SDRAM Modules
DDR2 SDRAM
SO-DIMM SDRAM
RoHS Compliant
Memory Products
N e v e r s t o p t h i n k i n g .
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Revision History:
Rev. 1.0
2004-10
Previous Revision:
Rev. 0.87
2003-06
Page
All
Subjects (major changes since last revision)
Layout and paragraph-order update
20, 21
IDD currents updated and final
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Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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Template: mp_a4_v2.3_2004-01-14.fm
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
1.2
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
I
DD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
3.2
I
DD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
6
7
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Sheet
5
Rev. 1.0, 2004-10
09122003-FTXN-KM26
200-Pin SO-DIMM DDR2 SDRAM Modules
DDR2 SDRAM
HYS64T32000HDL–[3.7/5]–A
HYS64T64020HDL–[3.7/5]–A
HYS64T128021HDL–[3.7/5]–A
1
Overview
This chapter gives an overview of the 1.8 V Unbuffered 200-Pin SO-DIMM DDR2 SDRAM Modules product family
and describes its main characteristics.
1.1
Features
•
200-Pin PC2-4200 and PC2-3200 DDR2 SDRAM
memory modules for use as main memory when
installed in systems such as mobile personal
computers.
•
Programmable CAS Latencies (3, 4 and 5), Burst
Length (8 & 4) and Burst Type
•
•
•
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_18 compatible
Off-Chip Driver Impedance Adjustment (OCD) and
On-Die Termination (ODT)
•
•
•
32M × 64, 64M × 64 and 128M × 64 module
organization, and 32M × 16, 64M × 8 chip
organization
•
•
Serial Presence Detect with E2PROM
SO-DIMM Dimensions (nominal):
30 mm high, 67.6 mm wide
JEDEC standard Double-Data-Rate-Two
Synchronous DRAMs (DDR2 SDRAM) with a single
+ 1.8 V (± 0.1 V) power supply
•
•
Based on JEDEC standard reference layouts Raw
Card “A”, “C“ and “D“
Built with 512 Mb DDR2 SDRAMs in P-TFBGA-84,
P-TFBGA-60 chipsize packages
RoHS Compliant Products1)
Table 1
Performance
Product Type Speed Code
Speed Grade
max. Clock Frequency
–3.7
PC2–4200 4–4–4
fCK5 266
fCK4 266
fCK3 200
tRCD 15
–5
Units
—
MHz
MHz
MHz
ns
ns
ns
ns
PC2–3200 3–3–3
@CL5
@CL4
@CL3
200
200
200
15
15
40
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
tRP
tRAS 45
tRC 60
15
55
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and
electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council
of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated
biphenyls and polybrominated biphenyl ethers.
Data Sheet
6
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Overview
1.2
Description
The INFINEON HYS64T[32/64/128]0xxHDL–[3.7/5]–A The memory array is designed with 512Mb Double-
module family are Small Outline DIMM modules “SO- Data-Rate-Two (DDR2) Synchronous DRAMs.
DIMMs” with 30,0 mm height based on DDR2 Decoupling capacitors are mounted on the PCB board.
technology. DIMMs are available as non-ECC modules The DIMMs feature serial presence detect based on a
in
32M × 64
(256MB),
64M × 64
(512MB), serial E2PROM device using the 2-pin I2C protocol. The
128M × 64 (1GB) organisation and density, intended first 128 bytes are programmed with configuration data
for mounting into 200 pin connector sockets.
and the second 128 bytes are available to the
customer.
Table 2
Ordering Informationfor RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM
Technology
PC2–3200
HYS64T32000HDL–5–A
HYS64T64020HDL–5–A
HYS64T128021HDL–5–A
PC2–4200
256MB 1R×16 PC2–3200S–333–11–C0 1 rank, Non-ECC
512MB 2R×16 PC2–3200S–333–11–A0 2 ranks, Non-ECC
512 Mbit (×16)
512 Mbit (×16
512 Mbit (×8)
1GB 2R×8 PC2–3200S–333–11–D0
2 ranks, Non-ECC
HYS64T32000HDL–3.7–A 256MB 1R×16 PC2–4200S–444–11–C0 1 rank, Non-ECC
HYS64T64020HDL–3.7–A 512MB 2R×16 PC2–4200S–444–11–A0 2 ranks, Non-ECC
512 Mbit (×16)
512 Mbit (×16
512 Mbit (×8)
HYS64T128021HDL–3.7–A 1GB 2R×8 PC2–4200S–444–11–F0
2 ranks, Non-ECC
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS64T32000HDL–5–A, indicating
Rev. “A” dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see
Chapter 7 of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200S–444–11–
C1”, where 4200S means SO-DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address
Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest
JEDEC SPD Revision 1.1 and produced on the Raw Card “C”.
Table 3
Address Format
DIMM
Module
Memory
Ranks
ECC/
# of
# of row/bank/columns bits Raw
Card
Density
Organization
Non-ECC
SDRAMs
256 MByte 32M ×64
512 MByte 64M ×64
1
2
2
Non-ECC
Non-ECC
Non-ECC
4
8
16
13/2/10
14/2/10
14/2/10
C
A
F
1 GByte
128M ×64
Table 4
Components on Modules1)
Product Type2)
DRAM Components2)
DRAM Density
512 Mbit
512 Mbit
DRAM Organisation
32M ×16
32M ×16
HYS64T32000HDL
HYS64T64020HDL
HYS64T128021HDL
HYB18T512160AF
HYB18T512160AF
HYB18T512800AF
512 Mbit
64Mb ×8
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
2) Green Product
Data Sheet
7
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Pin Configuration
2
Pin Configuration
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The
abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin
numbering is depicted in Figure 1
Table 5
Pin#
Pin Configuration of SO-DIMM
Name Pin
Buffer Function
Type Type
Clock Signals
30
164
32
CK0
CK1
CK0
CK1
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Clock Signals 2:0, Complement Clock Signals 2:0
Note:The system clock inputs. All address and
command lines are sampled on the cross point
of the rising edge of CK and the falling edge of
CK. A Delay Locked Loop (DLL) circuit is driven
from the clock inputs and output timing for read
operations is synchronized to the input clock.
166
79
80
CKE0
CKE1
I
I
SSTL
SSTL
Clock Enable Rank 1:0
Note:Activates the DDR2 SDRAM CK signal when
HIGH and deactivates the CK signal when
LOW. By deactivating the clocks, CKE LOW
initiates the Power Down Mode or the Self
Refresh Mode.
Note:2 Ranks module
Note:1-rank module
NC
NC
—
Control Signals
110
115
S0
S1
I
I
SSTL
SSTL
Chip Select Rank 1:0
Note:Enables the associated DDR2 SDRAM
command decoder when LOW and disables the
command decoder when HIGH. When the
command decoder is disabled, new commands
are ignored but previous operations continue.
Rank 0 is selected by S0; Rank 1 is selected by
S1. Ranks are also called "Physical banks".
Note:2 Ranks module
Note:1-rank module
Row Address Strobe
NC
RAS
NC
I
—
SSTL
108
Note:When sampled at the cross point of the rising
edge of CK,and falling edge of CK, RAS, CAS
and WE define the operation to be executed by
the SDRAM.
113
109
CAS
WE
I
I
SSTL
SSTL
Column Address Strobe
Write Enable
Address Signals
107
106
BA0
BA1
I
I
SSTL
SSTL
Bank Address Bus 2:0
Note:Selects which DDR2 SDRAM internal bank of
four or eight is activated.
Data Sheet
8
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Pin Configuration
Table 5
Pin#
Pin Configuration of SO-DIMM (cont’d)
Name Pin Buffer Function
Type Type
85
BA2
I
SSTL
Bank Address Bus 2
Note:greater than 512Mb DDR2 SDRAMS
Note:less than 1Gb DDR2 SDRAMS
Address Bus 12:0
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
102
101
100
99
98
97
94
92
93
91
Note:During a Bank Activate command cycle, defines
the row address when sampled at the
crosspoint of the rising edge of CK and falling
edge of CK. During a Read or Write command
cycle, defines the column address when
sampled at the cross point of the rising edge of
CK and falling edge of CK. In addition to the
column address, AP is used to invoke
autoprecharge operation at the end of the burst
read or write cycle. If AP is HIGH,
autoprecharge is selected and BA0-BAn
defines the bank to be precharged. If AP is
LOW, autoprecharge is disabled. During a
Precharge command cycle, AP is used in
conjunction with BA0-BAn to control which
bank(s) to precharge. If AP is HIGH, all banks
will be precharged regardless of the state of
BA0-BAn inputs. If AP is LOW, then BA0-BAn
are used to define which bank to precharge.
105
90
89
A12
A13
NC
I
SSTL
SSTL
—
Address Signal 12
Note:Module based on 256 Mbit or larger dies
Address Signal 13
Note:1 Gbit based module
116
I
NC
Note:Module based on 512 Mbit or smaller dies
Data Signals
5
7
17
19
4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Note:Data Input/Output pins
6
14
16
23
25
35
37
20
22
36
Data Sheet
9
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Pin Configuration
Table 5
Pin#
Pin Configuration of SO-DIMM (cont’d)
Name Pin Buffer Function
Type Type
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
Data Sheet
10
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Pin Configuration
Table 5
Pin#
Pin Configuration of SO-DIMM (cont’d)
Name Pin Buffer Function
Type Type
176
179
181
189
191
180
182
192
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
194
Data Strobe Signals
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186
DQS0 I/O
DQS0 I/O
DQS1 I/O
DQS1 I/O
DQS2 I/O
DQS2 I/O
DQS3 I/O
DQS3 I/O
DQS4 I/O
DQS4 I/O
DQS5 I/O
DQS5 I/O
DQS6 I/O
DQS6 I/O
DQS7 I/O
DQS7 I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobe Bus 7:0
Note:The data strobes, associated with one data
byte, sourced with data transfers. In Write
mode, the data strobe is sourced by the
controller and is centered in the data window. In
Read mode the data strobe is sourced by the
DDR2 SDRAM and is sent at the leading edge
of the data window. DQS signals are
complements, and timing is relative to the
crosspoint of respective DQS and DQS. If the
module is to be operated in single ended strobe
mode, all DQS signals must be tied on the
system board to VSS and DDR2 SDRAM mode
registers programmed appropriately.
Data Mask Signals
10
26
52
67
130
147
170
185
EEPROM
197
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Mask Bus 7:0
Note:The data write masks, associated with one data
byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is
LOW but blocks the write operation if it is HIGH.
In Read mode, DM lines have no effect.
SCL
I
CMOS Serial Bus Clock
Note:This signal is used to clock data into and out of
the SPD EEPROM.
Data Sheet
11
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Pin Configuration
Table 5
Pin#
Pin Configuration of SO-DIMM (cont’d)
Name Pin Buffer Function
Type Type
195
SDA
I/O
OD
Serial Bus Data
Note:This is a bidirectional pin used to transfer data
into or out of the SPD EEPROM. A resistor must
be connected from SDA to to VDDSPD on the
motherboard to act as a pull-up.
198
200
SA0
SA1
I
I
CMOS Serial Address Select Bus 1:0
Note:Address pins used to select the Serial Presence
CMOS
Detect base address.
Power Supplies
1
VREF
AI
—
—
I/O Reference Voltage
Note:Reference voltage for the SSTL-18 inputs.
EEPROM Power Supply
199
VDDSPD PWR
Note:Power supplies for core, I/O, Serial Presence
Detect, and ground for the module.
81,82,87,88,95,96,103,104,
111,112,117,118
VDD
PWR
GND
—
—
Power Supply
Note:Power supplies for core, I/O, Serial Presence
Detect, and ground for the module.
2,3,8,9,12,15,18,21,24,27,28, VSS
33,34,39,40,41,42,47,48,53,
54,59,60,65,66,71,72,77,78,
121,122,127,128,132,133,138,
139,144,145,149,150,155,156,
161,162,165,171,172,177,
Ground Plane
Note:Power supplies for core, I/O, Serial Presence
Detect, and ground for the module.
178,183,184,187,190,193,196
Other Pins
114
119
ODT0
ODT1
I
I
SSTL
SSTL
On-Die Termination Control 1:0
On-Die Termination Control 1
Note:Asserts on-die termination for DQ, DM, DQS,
and DQS signals if enabled via the DDR2
SDRAM mode register.
Note:2 Rank modules
NC
NC
NC
NC
—
—
Note:1 Rank modules
Not connected
50,69,83,84,120,163,168
Note:Pins not connected on Infineon SO-DIMMs
Data Sheet
12
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Pin Configuration
Table 6
Abbreviation
Abbreviations for Pin Type
Description
I
Standard input-only pin. Digital levels.
O
I/O
AI
PWR
GND
NC
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
Table 7
Abbreviation
SSTL
LV-CMOS
CMOS
OD
Abbreviations for Buffer Type
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Data Sheet
13
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Pin Configuration
VREF - Pin 001
DQ0 - Pin 005
Pin 002 -
Pin 006 -
Pin 010 -
Pin 014 -
Pin 018 -
Pin 022 -
Pin 026 -
Pin 030 -
Pin 034 -
Pin 038 -
VSS
VSS
- Pin 003
Pin 004 -
DQ4
DQ5
DM0
DQ6
VSS
DQ1 - Pin 007
DQS0 - Pin 011
Pin 008 - VSS
Pin 012 - VSS
Pin 016 - DQ7
Pin 020 - DQ12
Pin 024 - VSS
Pin 028 - VSS
Pin 032 - CK0
Pin 036 - DQ14
Pin 040 - VSS
V
SS - Pin 009
DQS0 - Pin 013
DQ2 - Pin 017
V
SS - Pin 015
DQ3 - Pin 019
DQ8 - Pin 023
V
SS - Pin 021
DQ13
DM1
CK0
VSS
DQ9 - Pin 025
DQS1 - Pin 029
V
SS - Pin 027
DQS1 - Pin 031
DQ10 - Pin 035
V
SS - Pin 033
DQ11 - Pin 037
DQ15
V
SS - Pin 039
VSS - Pin 041
DQ17 - Pin 045
DQS2 - Pin 049
VSS - Pin 053
Pin 042 - VSSDDD
Pin 046 - DQ21
Pin 050 - NC
DQ16 - Pin 043
VSS - Pin 047
Pin 044 - DQ20
Pin 048 - VSS
Pin 052 - DM2
Pin 056 - DQ22
Pin 060 - VSS
Pin 064 - DQ29
Pin 068 - DQS3
Pin 072 - VSS
Pin 076 - DQ31
Pin 080 - NC/CKE1
Pin 084 - NC
DQS2 - Pin 051
DQ18 - Pin 055
VSS - Pin 059
Pin 054 - VSS
Pin 058 - DQ23
Pin 062 - DQ28
Pin 066 - VSS
Pin 070 - DQS3
Pin 074 - DQ30
Pin 078 - VSS
Pin 082 - VDD
Pin 086 - NC/A14
Pin 090 - A11
Pin 094 - A6
DQ19 - Pin 057
DQ24 - Pin 061
VSS - Pin 065
DQ25 - Pin 063
DM3 - Pin 067
NC - Pin 069
V
SS - Pin 071
DQ26 - Pin 073
DQ27 - Pin 075
CKE0 - Pin 079
NC - Pin 083
V
SS - Pin 077
VDD - Pin 081
NC/BA2 - Pin 085
A12 - Pin 089
A8 - Pin 093
VDD - Pin 087
Pin 088 - VDD
Pin 092 - A7
A9 - Pin 091
VDD - Pin 095
Pin 096 - VDD
Pin 100 - A2
A5 - Pin 097
Pin 098 - A4
A3 - Pin 099
A1 - Pin 101
Pin 102 - A0
VDD - Pin 103
Pin 104 - VDD
Pin 108 - RAS
Pin 112 - VDD
Pin 116 - NC/A13
Pin 120 - NC
A10/AP - Pin 105
WE - Pin 109
CAS - Pin 113
Pin 106 - BA1
Pin 110 - S0
BA0 - Pin 107
VDD - Pin 111
Pin 114 - ODT0
Pin 118 - VDD
Pin 122 - VSS
Pin 126 - DQ37
Pin 130 - DM4
Pin 134 - DQ38
Pin 138 - VSS
Pin 142 - DQ45
Pin 146 - DQS5
Pin 150 - VSS
Pin 154 - DQ47
Pin 158 - DQ52
Pin 162 - VSS
Pin 166 - CK1
Pin 170 - DM6
Pin 174 - DQ54
Pin 178 - VSS
Pin 182 - DQ61
Pin 186 - DQS7
Pin 190 - VSS
Pin 194 - DQ63
Pin 198 - SA0
NC/S1 - Pin 115
NC/ODT1 - Pin 119
DQ32 - Pin 123
VDD - Pin 117
V
SS - Pin 121
Pin 124 - DQ36
Pin 128 - VSS
Pin 132 - VSS
Pin 136 - DQ39
Pin 140 - DQ44
Pin 144 - VSS
Pin 148 - DQS5
Pin 152 - DQ46
Pin 156 - VSS
Pin 160 - DQ53
Pin 164 - CK1
Pin 168 - VSS
Pin 172 - VSS
Pin 176 - DQ55
Pin 180 - DQ60
Pin 184 - VSS
Pin 188 - DQS7
Pin 192 - DQ62
Pin 196 - VSS
Pin 200 - SA1
DQ33 - Pin 125
DQS4 - Pin 129
V
SS - Pin 127
DQS4 - Pin 131
DQ34 - Pin 135
V
SS - Pin 133
DQ35 - Pin 137
DQ40 - Pin 141
V
SS - Pin 139
DQ41 - Pin 143
DM5 - Pin 147
DQ42 - Pin 151
V
V
SS - Pin 145
SS - Pin 149
DQ43 - Pin 153
DQ48 - Pin 157
V
SS - Pin 155
DQ49 - Pin 159
NC - Pin 163
V
V
SS - Pin 161
SS - Pin 165
DQS6 - Pin 167
DQS6 - Pin 169
DQ50 - Pin 173
V
SS - Pin 171
DQ51 - Pin 175
DQ56 - Pin 179
V
SS - Pin 177
DQ57 - Pin 181
DM7 - Pin 185
DQ58 - Pin 189
V
V
SS - Pin 183
SS - Pin 187
DQ59 - Pin 191
SDA - Pin 195
V
SS - Pin 193
SCL - Pin 197
VDDSPD - Pin 199
MPPT0140
Figure 1
Pin Configuration SO-DIMM (200 Pin)
Data Sheet
14
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Pin Configuration
2.1
Block Diagrams
ꢂꢘꢄꢑꢙꢑꢂꢘꢅ
ꢂꢘꢄꢑꢙꢑꢂꢘꢅꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢀꢇꢇꢢꢉꢁꢇ
ꢀꢇꢇꢕꢀꢇꢇꢈ
ꢀꢇꢇꢟꢑꢉꢁꢇꢑꢝꢝꢁꢛꢖꢀꢑꢝꢄ
ꢀꢇꢇꢕꢀꢇꢇꢈꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢘꢄꢑꢙꢑꢘꢚ
ꢛꢘꢉ
ꢓꢘꢉ
ꢘꢄꢑꢙꢑꢘꢚꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢛꢘꢉꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢓꢘꢉꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢜꢝꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢀꢛꢝꢡ
ꢀꢉꢉ
ꢀꢛꢝꢡꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢀꢉꢉꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢜꢝ
ꢓꢞꢝꢄ
ꢓꢞꢝꢅ
ꢖꢇꢃꢄ
ꢖꢇꢃꢅ
ꢓꢞꢝꢄꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢋ
ꢓꢞꢝꢅꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢌꢑꢙꢑꢇꢎ
ꢖꢇꢃꢄꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢋ
ꢖꢇꢃꢅꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢌꢑꢙꢑꢇꢎ
ꢝꢄ
ꢑꢉꢓꢒ
ꢑꢉꢇꢘ
ꢑꢘꢄ
ꢑꢘꢅ
ꢑꢘꢊ
ꢉꢓꢒ
ꢉꢇꢘ
ꢉꢘꢄ
ꢉꢘꢅ
ꢓꢞꢄ
ꢓꢞꢄ
ꢓꢞꢅ
ꢓꢞꢅ
ꢌꢑꢣꢤꢥꢦꢠ
ꢌꢑꢣꢤꢥꢦꢠ
ꢑꢑꢑꢑꢑꢑꢑꢜꢁ
ꢧꢠꢠ
ꢉꢄ
ꢉꢅ
ꢇꢊ
ꢇꢄ
ꢇꢌ
ꢇꢆ
ꢇꢀꢄ
ꢇꢈꢉꢄ
ꢇꢈꢉꢄ
ꢇꢈꢄ
ꢇꢈꢅ
ꢇꢈꢊ
ꢇꢈꢋ
ꢇꢈꢌ
ꢇꢈꢍ
ꢇꢈꢆ
ꢇꢈꢎ
ꢇꢀꢅ
ꢇꢈꢉꢅ
ꢇꢈꢉꢅ
ꢇꢈꢏ
ꢑꢒꢇꢀꢑꢑꢑꢓꢉ
ꢑꢒꢇꢈꢉ
ꢑꢒꢇꢈꢉ
ꢑꢔꢕꢖꢑꢄ
ꢑꢔꢕꢖꢑꢅ
ꢑꢔꢕꢖꢑꢊ
ꢑꢔꢕꢖꢑꢋ
ꢑꢔꢕꢖꢑꢌ
ꢑꢔꢕꢖꢑꢍ
ꢑꢔꢕꢖꢑꢆ
ꢑꢔꢕꢖꢑꢎ
ꢑꢒꢇꢀꢑꢑꢑꢓꢉ
ꢑꢒꢇꢈꢉ
ꢑꢒꢇꢈꢉ
ꢑꢔꢕꢖꢑꢄ
ꢑꢔꢕꢖꢑꢅ
ꢑꢔꢕꢖꢑꢊ
ꢑꢔꢕꢖꢑꢋ
ꢑꢔꢕꢖꢑꢌ
ꢑꢔꢕꢖꢑꢍ
ꢑꢔꢕꢖꢑꢆ
ꢑꢔꢕꢖꢑꢎ
ꢇꢀꢌ
ꢇꢈꢉꢌ
ꢇꢈꢉꢌ
ꢇꢈꢋꢊ
ꢇꢈꢋꢋ
ꢇꢈꢋꢌ
ꢇꢈꢋꢍ
ꢇꢈꢋꢆ
ꢇꢈꢋꢎ
ꢇꢈꢋꢏ
ꢇꢈꢋꢐ
ꢇꢀꢍ
ꢇꢈꢉꢍ
ꢇꢈꢉꢍ
ꢇꢈꢌꢄ
ꢇꢈꢌꢅ
ꢇꢈꢌꢊ
ꢇꢈꢌꢋ
ꢇꢈꢌꢌ
ꢇꢈꢌꢍ
ꢇꢈꢌꢆ
ꢇꢈꢌꢎ
ꢑꢒꢇꢀꢑꢑꢑꢓꢉ
ꢑꢒꢇꢀꢑꢑꢑꢓꢉ
ꢑꢒꢇꢈꢉ
ꢑꢒꢇꢈꢉ
ꢑꢔꢕꢖꢑꢄ
ꢑꢔꢕꢖꢑꢅ
ꢑꢔꢕꢖꢑꢊ
ꢑꢔꢕꢖꢑꢋ
ꢑꢔꢕꢖꢑꢌ
ꢑꢔꢕꢖꢑꢍ
ꢑꢔꢕꢖꢑꢆ
ꢑꢔꢕꢖꢑꢎ
ꢑꢒꢇꢈꢉ
ꢑꢒꢇꢈꢉ
ꢑꢔꢕꢖꢑꢄ
ꢑꢔꢕꢖꢑꢅ
ꢑꢔꢕꢖꢑꢊ
ꢑꢔꢕꢖꢑꢋ
ꢑꢔꢕꢖꢑꢌ
ꢑꢔꢕꢖꢑꢍ
ꢑꢔꢕꢖꢑꢆ
ꢑꢔꢕꢖꢑꢎ
ꢑꢗꢇꢀ
ꢑꢗꢇꢈꢉ
ꢑꢗꢇꢈꢉ
ꢑꢔꢕꢖꢏ
ꢑꢗꢇꢀ
ꢑꢗꢇꢈꢉ
ꢑꢗꢇꢈꢉ
ꢑꢔꢕꢖꢏ
ꢑꢗꢇꢀ
ꢑꢗꢇꢈꢉ
ꢑꢗꢇꢈꢉ
ꢑꢔꢕꢖꢏ
ꢑꢗꢇꢀ
ꢑꢗꢇꢈꢉ
ꢑꢗꢇꢈꢉ
ꢑꢔꢕꢖꢏ
ꢇꢈꢐ
ꢑꢔꢕꢖꢐ
ꢑꢔꢕꢖꢐ
ꢑꢔꢕꢖꢐ
ꢑꢔꢕꢖꢐ
ꢇꢈꢅꢄ
ꢇꢈꢅꢅ
ꢇꢈꢅꢊ
ꢇꢈꢅꢋ
ꢇꢈꢅꢌ
ꢇꢈꢅꢍ
ꢑꢔꢕꢖꢅꢄ
ꢑꢔꢕꢖꢅꢅ
ꢑꢔꢕꢖꢅꢊ
ꢑꢔꢕꢖꢅꢋ
ꢑꢔꢕꢖꢅꢌ
ꢑꢔꢕꢖꢅꢍ
ꢑꢔꢕꢖꢅꢄ
ꢑꢔꢕꢖꢅꢅ
ꢑꢔꢕꢖꢅꢊ
ꢑꢔꢕꢖꢅꢋ
ꢑꢔꢕꢖꢅꢌ
ꢑꢔꢕꢖꢅꢍ
ꢑꢔꢕꢖꢅꢄ
ꢑꢔꢕꢖꢅꢅ
ꢑꢔꢕꢖꢅꢊ
ꢑꢔꢕꢖꢅꢋ
ꢑꢔꢕꢖꢅꢌ
ꢑꢔꢕꢖꢅꢍ
ꢑꢔꢕꢖꢅꢄ
ꢑꢔꢕꢖꢅꢅ
ꢑꢔꢕꢖꢅꢊ
ꢑꢔꢕꢖꢅꢋ
ꢑꢔꢕꢖꢅꢌ
ꢑꢔꢕꢖꢅꢍ
ꢇꢅ
ꢇꢍ
ꢇꢋ
ꢇꢎ
ꢇꢀꢊ
ꢇꢈꢉꢊ
ꢇꢈꢉꢊ
ꢇꢈꢅꢆ
ꢇꢈꢅꢎ
ꢇꢈꢅꢏ
ꢇꢈꢅꢐ
ꢇꢈꢊꢄ
ꢇꢈꢊꢅ
ꢇꢈꢊꢊ
ꢇꢈꢊꢋ
ꢇꢀꢋ
ꢇꢈꢉꢋ
ꢇꢈꢉꢋ
ꢇꢈꢊꢌ
ꢇꢈꢊꢍ
ꢇꢈꢊꢆ
ꢇꢈꢊꢎ
ꢇꢈꢊꢏ
ꢇꢈꢊꢐ
ꢇꢈꢋꢄ
ꢇꢈꢋꢅ
ꢑꢒꢇꢀꢑꢑꢑꢓꢉ
ꢑꢒꢇꢈꢉ
ꢑꢒꢇꢈꢉ
ꢑꢔꢕꢖꢑꢄ
ꢑꢔꢕꢖꢑꢅ
ꢑꢔꢕꢖꢑꢊ
ꢑꢔꢕꢖꢑꢋ
ꢑꢔꢕꢖꢑꢌ
ꢑꢔꢕꢖꢑꢍ
ꢑꢔꢕꢖꢑꢆ
ꢑꢔꢕꢖꢑꢎ
ꢑꢒꢇꢀꢑꢑꢑꢓꢉ
ꢑꢒꢇꢈꢉ
ꢑꢒꢇꢈꢉ
ꢑꢔꢕꢖꢑꢄ
ꢑꢔꢕꢖꢑꢅ
ꢑꢔꢕꢖꢑꢊ
ꢑꢔꢕꢖꢑꢋ
ꢑꢔꢕꢖꢑꢌ
ꢑꢔꢕꢖꢑꢍ
ꢑꢔꢕꢖꢑꢆ
ꢑꢔꢕꢖꢑꢎ
ꢇꢀꢆ
ꢇꢈꢉꢆ
ꢇꢈꢉꢆ
ꢇꢈꢌꢏ
ꢇꢈꢌꢐ
ꢇꢈꢍꢄ
ꢇꢈꢍꢅ
ꢇꢈꢍꢊ
ꢇꢈꢍꢋ
ꢇꢈꢍꢌ
ꢇꢈꢍꢍ
ꢇꢀꢎ
ꢇꢈꢉꢎ
ꢇꢈꢉꢎ
ꢇꢈꢍꢆ
ꢇꢈꢍꢎ
ꢇꢈꢍꢏ
ꢇꢈꢍꢐ
ꢇꢈꢆꢄ
ꢇꢈꢆꢅ
ꢇꢈꢆꢊ
ꢇꢈꢆꢋ
ꢑꢒꢇꢀꢑꢑꢑꢓꢉ
ꢑꢒꢇꢈꢉ
ꢑꢒꢇꢈꢉ
ꢑꢔꢕꢖꢑꢄ
ꢑꢔꢕꢖꢑꢅ
ꢑꢔꢕꢖꢑꢊ
ꢑꢔꢕꢖꢑꢋ
ꢑꢔꢕꢖꢑꢌ
ꢑꢔꢕꢖꢑꢍ
ꢑꢔꢕꢖꢑꢆ
ꢑꢔꢕꢖꢑꢎ
ꢑꢒꢇꢀꢑꢑꢑꢓꢉ
ꢑꢒꢇꢈꢉ
ꢑꢒꢇꢈꢉ
ꢑꢔꢕꢖꢑꢄ
ꢑꢔꢕꢖꢑꢅ
ꢑꢔꢕꢖꢑꢊ
ꢑꢔꢕꢖꢑꢋ
ꢑꢔꢕꢖꢑꢌ
ꢑꢔꢕꢖꢑꢍ
ꢑꢔꢕꢖꢑꢆ
ꢑꢔꢕꢖꢑꢎ
ꢑꢗꢇꢀ
ꢑꢗꢇꢈꢉ
ꢑꢗꢇꢈꢉ
ꢑꢔꢕꢖꢏ
ꢑꢗꢇꢀ
ꢑꢗꢇꢈꢉ
ꢑꢗꢇꢈꢉ
ꢑꢔꢕꢖꢏ
ꢑꢗꢇꢀ
ꢑꢗꢇꢈꢉ
ꢑꢗꢇꢈꢉ
ꢑꢔꢕꢖꢏ
ꢑꢗꢇꢀ
ꢑꢗꢇꢈꢉ
ꢑꢗꢇꢈꢉ
ꢑꢔꢕꢖꢏ
ꢑꢔꢕꢖꢐ
ꢑꢔꢕꢖꢐ
ꢑꢔꢕꢖꢐ
ꢑꢔꢕꢖꢐ
ꢑꢔꢕꢖꢅꢄ
ꢑꢔꢕꢖꢅꢅ
ꢑꢔꢕꢖꢅꢊ
ꢑꢔꢕꢖꢅꢋ
ꢑꢔꢕꢖꢅꢌ
ꢑꢔꢕꢖꢅꢍ
ꢑꢔꢕꢖꢅꢄ
ꢑꢔꢕꢖꢅꢅ
ꢑꢔꢕꢖꢅꢊ
ꢑꢔꢕꢖꢅꢋ
ꢑꢔꢕꢖꢅꢌ
ꢑꢔꢕꢖꢅꢍ
ꢑꢔꢕꢖꢅꢄ
ꢑꢔꢕꢖꢅꢅ
ꢑꢔꢕꢖꢅꢊ
ꢑꢔꢕꢖꢅꢋ
ꢑꢔꢕꢖꢅꢌ
ꢑꢔꢕꢖꢅꢍ
ꢑꢔꢕꢖꢅꢄ
ꢑꢔꢕꢖꢅꢅ
ꢑꢔꢕꢖꢅꢊ
ꢑꢔꢕꢖꢅꢋ
ꢑꢔꢕꢖꢅꢌ
ꢑꢔꢕꢖꢅꢍ
ꢀꢁꢂꢃꢄꢅꢆꢄ
Figure 2
Block Diagram Raw Card A SO-DIMM (×64, 2 Ranks, ×16)
Notes
2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
1. DQ, DQS, DM resistors are 22 Ω ±5 %
Data Sheet
15
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Pin Configuration
ꢂꢘꢄꢑꢙꢑꢂꢘꢅꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢘꢄꢑꢙꢑꢘꢚꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢛꢘꢉꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢓꢘꢉꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢜꢝꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢓꢞꢝꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢋ
ꢖꢇꢃꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢋ
ꢂꢘꢄꢑꢙꢑꢂꢘꢅ
ꢘꢄꢑꢙꢑꢘꢚ
ꢛꢘꢉ
ꢀꢇꢇꢢꢉꢁꢇ
ꢀꢇꢇꢕꢀꢇꢇꢈ
ꢀꢇꢇꢟꢑꢉꢁꢇꢑꢝꢝꢁꢛꢖꢀꢑꢝꢄ
ꢀꢇꢇꢕꢀꢇꢇꢈꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢀꢛꢝꢡ
ꢀꢉꢉ
ꢓꢘꢉ
ꢜꢝ
ꢓꢞꢝꢄ
ꢖꢇꢃꢄ
ꢀꢛꢝꢡꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢀꢉꢉꢟꢑꢉꢇꢛꢘꢀꢠꢑꢇꢄꢑꢙꢑꢇꢎ
ꢉꢄ
ꢇꢊ
ꢇꢄ
ꢓꢞꢄ
ꢓꢞꢄ
ꢓꢞꢅ
ꢓꢞꢅ
ꢇꢀꢄ
ꢇꢈꢉꢄ
ꢇꢈꢉꢄ
ꢇꢈꢄ
ꢇꢈꢅ
ꢇꢈꢊ
ꢇꢈꢋ
ꢇꢈꢌ
ꢇꢈꢍ
ꢇꢈꢆ
ꢇꢈꢎ
ꢇꢀꢅ
ꢇꢈꢉꢅ
ꢇꢈꢉꢅ
ꢇꢈꢏ
ꢑꢒꢇꢀꢑꢑꢑꢓꢉ
ꢑꢒꢇꢈꢉ
ꢑꢒꢇꢈꢉ
ꢑꢔꢕꢖꢑꢄ
ꢑꢔꢕꢖꢑꢅ
ꢑꢔꢕꢖꢑꢊ
ꢑꢔꢕꢖꢑꢋ
ꢑꢔꢕꢖꢑꢌ
ꢑꢔꢕꢖꢑꢍ
ꢑꢔꢕꢖꢑꢆ
ꢑꢔꢕꢖꢑꢎ
ꢇꢀꢌ
ꢇꢈꢉꢌ
ꢇꢈꢉꢌ
ꢇꢈꢋꢊ
ꢇꢈꢋꢋ
ꢇꢈꢋꢌ
ꢇꢈꢋꢍ
ꢇꢈꢋꢆ
ꢇꢈꢋꢎ
ꢇꢈꢋꢏ
ꢇꢈꢋꢐ
ꢇꢀꢍ
ꢇꢈꢉꢍ
ꢇꢈꢉꢍ
ꢇꢈꢌꢄ
ꢇꢈꢌꢅ
ꢇꢈꢌꢊ
ꢇꢈꢌꢋ
ꢇꢈꢌꢌ
ꢇꢈꢌꢍ
ꢇꢈꢌꢆ
ꢇꢈꢌꢎ
ꢑꢒꢇꢀꢑꢑꢑꢓꢉ
ꢑꢒꢇꢈꢉ
ꢑꢒꢇꢈꢉ
ꢑꢔꢕꢖꢑꢄ
ꢑꢔꢕꢖꢑꢅ
ꢑꢔꢕꢖꢑꢊ
ꢑꢔꢕꢖꢑꢋ
ꢑꢔꢕꢖꢑꢌ
ꢑꢔꢕꢖꢑꢍ
ꢑꢔꢕꢖꢑꢆ
ꢑꢔꢕꢖꢑꢎ
ꢌꢑꢣꢤꢥꢦꢠ
ꢌꢑꢣꢤꢥꢦꢠ
ꢝꢄ
ꢉꢓꢒ
ꢉꢇꢘ
ꢉꢘꢄ
ꢉꢘꢅ
ꢑꢉꢓꢒ
ꢑꢉꢇꢘ
ꢑꢘꢄ
ꢑꢘꢅ
ꢑꢘꢊ
ꢑꢑꢑꢑꢑꢑꢑꢜꢁ
ꢑꢗꢇꢀ
ꢑꢗꢇꢈꢉ
ꢑꢗꢇꢈꢉ
ꢑꢔꢕꢖꢏ
ꢑꢗꢇꢀ
ꢑꢗꢇꢈꢉ
ꢑꢗꢇꢈꢉ
ꢑꢔꢕꢖꢏ
ꢧꢠꢠ
ꢇꢈꢐ
ꢑꢔꢕꢖꢐ
ꢑꢔꢕꢖꢐ
ꢇꢈꢅꢄ
ꢇꢈꢅꢅ
ꢇꢈꢅꢊ
ꢇꢈꢅꢋ
ꢇꢈꢅꢌ
ꢇꢈꢅꢍ
ꢑꢔꢕꢖꢅꢄ
ꢑꢔꢕꢖꢅꢅ
ꢑꢔꢕꢖꢅꢊ
ꢑꢔꢕꢖꢅꢋ
ꢑꢔꢕꢖꢅꢌ
ꢑꢔꢕꢖꢅꢍ
ꢑꢔꢕꢖꢅꢄ
ꢑꢔꢕꢖꢅꢅ
ꢑꢔꢕꢖꢅꢊ
ꢑꢔꢕꢖꢅꢋ
ꢑꢔꢕꢖꢅꢌ
ꢑꢔꢕꢖꢅꢍ
ꢇꢅ
ꢇꢋ
ꢇꢀꢊ
ꢇꢈꢉꢊ
ꢇꢈꢉꢊ
ꢇꢈꢅꢆ
ꢇꢈꢅꢎ
ꢇꢈꢅꢏ
ꢇꢈꢅꢐ
ꢇꢈꢊꢄ
ꢇꢈꢊꢅ
ꢇꢈꢊꢊ
ꢇꢈꢊꢋ
ꢇꢀꢋ
ꢇꢈꢉꢋ
ꢇꢈꢉꢋ
ꢇꢈꢊꢌ
ꢇꢈꢊꢍ
ꢇꢈꢊꢆ
ꢇꢈꢊꢎ
ꢇꢈꢊꢏ
ꢇꢈꢊꢐ
ꢇꢈꢋꢄ
ꢇꢈꢋꢅ
ꢑꢒꢇꢀꢑꢑꢑꢓꢉ
ꢑꢒꢇꢈꢉ
ꢑꢒꢇꢈꢉ
ꢑꢔꢕꢖꢑꢄ
ꢑꢔꢕꢖꢑꢅ
ꢑꢔꢕꢖꢑꢊ
ꢑꢔꢕꢖꢑꢋ
ꢑꢔꢕꢖꢑꢌ
ꢑꢔꢕꢖꢑꢍ
ꢑꢔꢕꢖꢑꢆ
ꢑꢔꢕꢖꢑꢎ
ꢇꢀꢆ
ꢇꢈꢉꢆ
ꢇꢈꢉꢆ
ꢇꢈꢌꢏ
ꢇꢈꢌꢐ
ꢇꢈꢍꢄ
ꢇꢈꢍꢅ
ꢇꢈꢍꢊ
ꢇꢈꢍꢋ
ꢇꢈꢍꢌ
ꢇꢈꢍꢍ
ꢇꢀꢎ
ꢇꢈꢉꢎ
ꢇꢈꢉꢎ
ꢇꢈꢍꢆ
ꢇꢈꢍꢎ
ꢇꢈꢍꢏ
ꢇꢈꢍꢐ
ꢇꢈꢆꢄ
ꢇꢈꢆꢅ
ꢇꢈꢆꢊ
ꢇꢈꢆꢋ
ꢑꢒꢇꢀꢑꢑꢑꢓꢉ
ꢑꢒꢇꢈꢉ
ꢑꢒꢇꢈꢉ
ꢑꢔꢕꢖꢑꢄ
ꢑꢔꢕꢖꢑꢅ
ꢑꢔꢕꢖꢑꢊ
ꢑꢔꢕꢖꢑꢋ
ꢑꢔꢕꢖꢑꢌ
ꢑꢔꢕꢖꢑꢍ
ꢑꢔꢕꢖꢑꢆ
ꢑꢔꢕꢖꢑꢎ
ꢑꢗꢇꢀ
ꢑꢗꢇꢈꢉ
ꢑꢗꢇꢈꢉ
ꢑꢔꢕꢖꢏ
ꢑꢗꢇꢀ
ꢑꢗꢇꢈꢉ
ꢑꢗꢇꢈꢉ
ꢑꢔꢕꢖꢏ
ꢑꢔꢕꢖꢐ
ꢑꢔꢕꢖꢐ
ꢑꢔꢕꢖꢅꢄ
ꢑꢔꢕꢖꢅꢅ
ꢑꢔꢕꢖꢅꢊ
ꢑꢔꢕꢖꢅꢋ
ꢑꢔꢕꢖꢅꢌ
ꢑꢔꢕꢖꢅꢍ
ꢑꢔꢕꢖꢅꢄ
ꢑꢔꢕꢖꢅꢅ
ꢑꢔꢕꢖꢅꢊ
ꢑꢔꢕꢖꢅꢋ
ꢑꢔꢕꢖꢅꢌ
ꢑꢔꢕꢖꢅꢍ
ꢀꢁꢂꢃꢄꢄꢐꢄ
Figure 3
Block Diagram Raw Card C SO-DIMM (×64, 1Rank, ×16)
Notes
2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
1. DQ, DQS, DM resistors are 22 Ω ±5 %
)
Data Sheet
16
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Pin Configuration
BA0 - BA2: SDRAMs D0 - D15
A0 - An: SDRAMs D0 - D15
RAS: SDRAMs D0 - D15
CAS: SDRAMs D0 - D15
WE: SDRAMs D0 - D15
BA0 - BA2
A0 - An
RAS
VDD,SPD
VDD/VDDQ
VREF
VDD: SPD EEPROM E0
VDD/VDDQ: SDRAMs D0 - D15
VREF: SDRAMs D0 - D15
VSS: SDRAMs D0 - D15
CAS
WE
CKE 0: SDRAMs D0 - D1, D4 - D5, D10 - D11, D14 - D15
CKE 1: SDRAMs D2 - D3, D6 - D9, D12 - D13
ODT 0: SDRAMs D0 - D1, D4 - D5, D10 - D11, D14 - D15
ODT 1: SDRAMs D2 - D3, D6 - D9, D12 - D13
CKE 0
CKE 1
ODT 0
ODT 1
VSS
S0
S1
D0
D8
D9
D2
D3
D4
D12
D13
D6
E0
DM4
DQS4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM0
DQS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SCL
SDA
A0
A1
A2
SCL
SDA
SA0
SA1
SA2
VSS
WP
CK0
CK0
8 loads
8 loads
5.6 pF
5.6 pF
D1
D5
CK1
CK1
DM1
DQS1
DQS1
DQ8
DM5
DQS5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D10
D14
DM2
DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM6
DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D11
D15
D7
DM3
DQS3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM7
DQS7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
MPBT0370
Figure 4
Block Diagram Raw Card F SO-DIMM (×64, 2 Ranks, ×8)
Notes
4. S0, S1, ODTO, ODT1, CKEO, CKE1 resistors are
3 Ω ±5 %
3. DQ, DQS, DM resistors are 22 Ω ±5 %
5. BAn, An, RAS, CAS, WE resistors are 10 Ω ±5 %
Data Sheet
17
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
IDD Specifications and Conditions
3
IDD Specifications and Conditions
Table 8
I
DD Measurement Conditions 1)2)3)4)5)6)
Parameter
Symbol
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH
between valid commands. Address and control inputs are SWITCHING, Databus inputs are
SWITCHING.
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING.
Precharge Power-Down Current
IDD2P
IDD2Q
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Standby Current
IDD3N
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Active Power-Down Current
IDD3P(0)
IDD3P(1)
IDD4R
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
IDD5B
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
IDD5D
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
18
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
IDD Specifications and Conditions
Table 8
I
DD Measurement Conditions (cont’d)1)2)3)4)5)6)
Parameter
Symbol
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD
:
LOW is defined as VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
STABLE is defined as: inputs are stable at a HIGH or LOW level
FLOATING is defined as: inputs are VREF = VDDQ /2
SWITCHING is defined as: inputs are changing between HIGH and LOW every other clock (once per 2 cycles)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer
(once per cycle) for DQ signals not including mask or strobes.
4) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to
HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6) For details and notes see the relevant INFINEON component data sheet
Data Sheet
19
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
IDD Specifications and Conditions
Table 9
Product Type
I
DD Specification
Unit
Notes1)
Organization
256 MB
×64
1 Rank
–3.7
Max.
320
360
160
20
512 MB
×64
2 Ranks
–3.7
Max.
340
380
320
30
1 GB
×64
2 Ranks
–3.7
Max.
550
630
640
60
Symbol
IDD0
IDD1
IDD2N
IDD2P
2)
2)
3)
3)
3)
3)
3)
3)
2)
2)
2)
3)
3)
2)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2Q
IDD3N
IDD3P(MRS= 0)
IDD3P(MRS= 1)
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
120
160
60
240
320
130
40
420
460
540
50
480
640
260
80
750
790
1070
100
32
20
400
440
520
20
8
880
16
900
1160
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
2) The other rank is in IDD2P Pre charge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
Data Sheet
20
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
IDD Specifications and Conditions
Table 10
Product Type
I
DD Specification
Unit
Notes1)
Organization
256 MB
×64
1 Rank
–5
512 MB
×64
2 Ranks
–5
1 GB
×64
2 Ranks
–5
Symbol
IDD0
IDD1
IDD2N
IDD2P
IDD2Q
IDD3N
IDD3P(MRS=
IDD3P(MRS=
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
Max.
280
300
130
20
100
140
50
Max.
300
320
260
30
200
280
100
40
360
380
500
50
Max.
470
510
510
60
400
560
210
80
590
630
990
100
32
2)
2)
3)
3)
3)
3)
3)
3)
2)
2)
2)
3)
3)
2)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
0)
20
1)
340
360
480
20
8
840
16
860
IDD7
1070
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
2) The other rank is in IDD2P Pre charge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
Data Sheet
21
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
IDD Specifications and Conditions
3.1
IDD Test Conditions
For testing the IDD parameters, the following timing parameters are used:
Table 11
IDD Measurement Test Conditions
Parameter
Symbol
–3.7
–5
Unit
PC2-4200-4-4-4 PC2-3200-3-3-3
CAS Latency
Clock Cycle Time
CL(IDD)
tCK(IDD)
tRCD(IDD)
tRC(IDD)
4
3
5
15
55
7.5
10
40
70000
15
105
7.8
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
3.75
15
60
7.5
10
Active to Read or Write delay
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay ×81) tRRD(IDD)
×162) tRRD(IDD)
Active to Precharge Command
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command period tRFC(IDD)
Average periodic Refresh interval
tRAS.MIN(IDD) 45
tRAS.MAX(IDD) 70000
tRP(IDD)
15
105
7.8
tREFI
1) For modules based on ×8 components
2) For modules based on ×16 components
3.2
On Die Termination (ODT) Current
The ODT function adds additional current consumption current consumption for any terminated input pin,
to the DDR2 SDRAM when enabled by the EMRS(1). depends on the input pin is in tristate or driving 0 or 1,
Depending on address bits A[6,2] in the EMRS(1) a as long a ODT is enabled during a given period of time.
“weak” or “strong” termination can be selected. The
Table 12
Parameter
ODT current per terminated pin:
Symbol Min.
Typ.
6
Max.
7.5
Unit
EMRS(1) State
Enabled ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; Data Bus inputs are
FLOATING
IODTO
5
2.5
mA/DQ A6 = 0, A2 = 1
3
3.75
mA/DQ A6 = 1, A2 = 0
Active ODT current per DQ
IODTT
10
5
12
6
15
7.5
mA/DQ A6 = 0, A2 = 1
mA/DQ A6 = 1, A2 = 0
added IDDQ current for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs
are STABLE or SWITCHING.
Note:For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
22
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Electrical Characteristics
4
Electrical Characteristics
4.1
Operating Conditions
Table 13
Absolute Maximum Ratings
Parameter
Symbol
Values
min.
VIN, VOUT – 0.5
Unit Note/Test Condition
max.
2.3
2.3
2.3
95
1)
Voltage on any pins relative to VSS
Voltage on VDD relative to VSS
Voltage on VDD Q relative to VSS
Storage Humidity (without condensation)
V
V
V
1)
VDD
VDDQ
HSTG
– 1.0
– 0.5
5
1)
1)
%
1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability
Table 14
Operating Conditions
Parameter
Symbol Values
min.
Unit Notes
max.
+55
+95
+100
+105
90
DIMM Module Operating Temperature Range (ambient)
DRAM Component Case Temperature Range
Storage Temperature
Barometric Pressure (operating & storage)
Operating Humidity (relative)
TOPR
TCASE
TSTG
PBar
HOPR
0
0
– 50
+69
10
°C
°C
1)2)3)4)
°C
kPa
5)
%
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs
2) Within the DRAM Component Case Temperature range all DRAM specification will be supported.
3) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below
85°C case temperature before initiating self-refresh operation.
5) Up to 3000 m.
Table 15
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Values
Min.
1.7
1.7
0.49 x VDDQ
1.7
Unit
Notes
Nom.
1.8
1.8
0.5 x VDDQ
–
–
–
Max.
1.9
1.9
0.51 x VDDQ
3.6
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
DC Input Logic High
DC Input Logic Low
VDD
V
V
V
V
V
V
µA
-
1)
VDDQ
VREF
VDDSPD
VIH (DC)
VIL (DC)
IL
2)
V
REF + 0.125
V
V
5
DDQ + 0.3
REF – 0.125
– 0.30
– 5
3)
In / Output Leakage Current
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise in VDDQ
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
.
Data Sheet
23
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Electrical Characteristics
Table 16
Speed Grade Definition Speed Bins
Speed Grade
DDR2–533C
–3.7
4–4–4
DDR2–400B
–5
3–3–3
Unit
Notes
IFX Sort Name
CAS-RCD-RP latencies
Parameter
tCK
—
ns
ns
ns
ns
ns
ns
ns
Symbol
tCK
tCK
Min.
5
Max.
8
Min.
5
Max.
8
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
3.75
3.75
45
8
8
5
8
tCK
5
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
40
55
15
15
70000
—
—
60
15
—
15
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI
.
Table 17
Parameter
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C
Symbol –3.7
–5
Unit Notes1)
DDR2–533 4–4–4
DDR2–400 3–3–3
Min.
–500
2
0.45
3
Max.
+500
—
0.55
—
Min.
–600
2
0.45
3
Max.
+600
—
0.55
—
DQ output access time from CK / CK tAC
CAS A to CAS B command period tCCD
ps
tCK
tCK
tCK
CK, CK high-level width
tCH
CKE minimum high and low pulse
tCKE
width
CK, CK low-level width
tCL
tDAL
0.45
WR + tRP
0.55
—
0.45
WR + tRP
0.55
—
tCK
tCK
Auto-Precharge write recovery +
precharge time
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
tDELAY
tIS + tCK
+
––
tIS + tCK
+
—
ns
tIH
tIH
DQ and DM input hold time
tDH(base) 225
DH1(base) –25
––
275
25
––
ps
ps
tCK
ps
(differential data strobe)
DQ and DM input hold time (single
ended data strobe)
t
—
—
DQ and DM input pulse width (each tDIPW
0.35
—
0.35
–500
—
input)
DQS output access time from CK / tDQSCK
–450
+450
+500
CK
Data Sheet
24
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Electrical Characteristics
Table 17
Parameter
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C (cont’d)
Symbol –3.7
–5
Unit Notes1)
DDR2–533 4–4–4
DDR2–400 3–3–3
Min.
Max.
Min.
Max.
DQS input low (high) pulse width
(write cycle)
tDQSL,H
tDQSQ
0.35
—
0.35
—
tCK
DQS-DQ skew (for DQS &
—
300
—
350
ps
associated DQ signals)
Write command to 1st DQS latching tDQSS
WL – 0.25 WL + 0.25 WL – 0.25 WL + 0.25 tCK
transition
DQ and DM input setup time
tDS(base) 100
—
—
—
—
150
25
—
—
—
—
ps
ps
tCK
tCK
(differential data strobe)
DQ and DM input setup time (single tDS1(base) –25
ended data strobe)
DQS falling edge hold time from CK tDSH
0.2
0.2
0.2
0.2
(write cycle)
DQS falling edge to CK setup time tDSS
(write cycle)
Clock half period
tHP
MIN. (tCL, tCH)
tAC.MAX
MIN. (tCL, tCH)
Data-out high-impedance time from tHZ
—
—
tAC.MAX
ps
CK / CK
Address and control input hold time tIH(base) 375
—
—
475
0.6
—
—
ps
tCK
Address and control input pulse
tIPW
0.6
width
(each input)
Address and control input setup time tIS(base) 250
—
350
—
ps
ps
DQ low-impedance time from CK / tLZ(DQ)
2 × tAC.MIN tAC.MAX
2 × tAC.MIN tAC.MAX
CK
DQS low-impedance from CK / CK tLZ(DQS)
tAC.MIN
2
tAC.MAX
—
tAC.MIN
2
tAC.MAX
—
ps
tCK
Mode register set command cycle
tMRD
time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
tOIT
tQH
tQHS
tREFI
0
12
—
400
7.8
3.9
—
0
12
—
450
7.8
3.9
—
ns
t
HP – tQHS
t
HPQ – tQHS
—
—
—
105
—
—
—
105
ps
µs
µs
ns
2)
3)
Average periodic refresh Interval
Auto-Refresh to Active/Auto-
Refresh command period
tRFC
Precharge-All (4 banks) command tRP
t
RP + 1tCK
—
t
RP + 1tCK
—
ns
period
Read preamble
Read postamble
tRPRE
tRPST
tRRD
0.9
0.40
7.5
10
1.1
0.60
—
—
—
0.9
0.40
7.5
10
1.1
0.60
—
—
—
tCK
tCK
ns
ns
ns
Active bank A to Active bank B
command period
Internal Read to Precharge
command delay
tRTP
7.5
7.5
Data Sheet
25
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Electrical Characteristics
Table 17
Parameter
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C (cont’d)
Symbol –3.7
–5
Unit Notes1)
DDR2–533 4–4–4
DDR2–400 3–3–3
Min.
0.35xtCK
0.40
Max.
—
0.60
—
Min.
0.35xtCK
0.40
Max.
—
0.60
—
Write preamble
Write postamble
tWPRE
tWPST
tCK
tCK
ns
Write recovery time for write without tWR
15
15
Auto-Precharge
Write recovery time for write with
WR
t
WR/tCK
t
WR/tCK
tCK
ns
Auto-Precharge
Internal Write to Read command
delay
tWTR
tXARD
7.5
2
—
—
10
2
—
—
Exit power down to any valid
tCK
command
(other than NOP or Deselect)
Exit active power-down mode to
Read command (slow exit, lower
power)
Exit precharge power-down to any tXP
valid command (other than NOP or
Deselect)
tXARDS
6 – AL
2
—
—
6 – AL
2
—
—
tCK
tCK
Exit Self-Refresh to non-Read
tXSNR
t
RFC +10
—
—
t
RFC +10
—
—
ns
command
Exit Self-Refresh to Read command tXSRD
200
200
tCK
1) For details and notes see the relevant INFINEON component data sheet
2) 0 ≤ TCASE ≤ 85 °C
3) 85 °C < TCASE ≤ 95 °C
Table 18
ODT AC Electrical Characteristics and Operating Conditions
Symbol Parameter / Condition
Values
Min.
2
Unit
Notes
Max.
2
tAOND
tAON
ODT turn-on delay
ODT turn-on
tCK
ns
1)
tAC.MIN
tAC.MAX + 1 ns
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency 3
ODT Power Down Exit Latency
tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns ns
2.5
2.5
tCK
2)
tAC.MIN
tAC.MAX + 0.6 ns
ns
tAC.MIN + 2 ns 2.5 tCK +tAC.MAX + 1 ns ns
—
—
tCK
tCK
8
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
max is when the ODT resistance is fully on. Both are measure from tAOND
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high
impedance. Both are measured from tAOFD
.
.
Data Sheet
26
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
SPD Codes
5
SPD Codes
Table 19
SPD Codes for HYS64T[32/64/128]0xxHDL–3.7–A
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
Rev. 1.1
HEX
80
0
Programmed SPD Bytes in EEPROM
1
2
Total number of Bytes in EEPROM
Memory Type (DDR2)
08
08
08
08
08
08
3
4
5
6
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
0D
0A
60
0D
0A
61
0E
0A
61
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
t
t
CK @ CLMAX (Byte 18) [ns]
AC SDRAM @ CLMAX (Byte 18) [ns]
3D
50
00
82
10
00
00
0C
04
38
00
04
00
01
3D
50
3D
50
00
82
10
00
00
0C
04
38
00
04
00
01
3D
50
3D
50
00
82
08
00
00
0C
04
38
00
04
00
01
3D
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
Data Sheet
27
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
SPD Codes
Table 19
SPD Codes for HYS64T[32/64/128]0xxHDL–3.7–A (cont’d)
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
50
60
3C
28
3C
2D
40
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
Rev. 1.1
HEX
50
60
3C
28
3C
2D
40
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
Rev. 1.1
HEX
50
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
t
t
t
t
t
t
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
60
3C
1E
3C
2D
80
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
00
51
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Re-lock Time
T
Psi(T-A) DRAM
∆T0 (DT0)
00
53
72
52
00
53
72
52
CASE.MAX Delta / ∆T4R4W Delta
78
3E
2E
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q,
2B
2B
RDIMM)
51
∆T2P (DT2P)
1D
1D
1E
Data Sheet
28
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
SPD Codes
Table 19
SPD Codes for HYS64T[32/64/128]0xxHDL–3.7–A (cont’d)
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
1D
23
16
36
1C
30
00
00
00
00
11
BB
C1
00
Rev. 1.1
HEX
1D
23
16
36
1C
30
00
00
00
00
11
BC
C1
00
Rev. 1.1
HEX
1E
24
17
34
1E
20
00
00
00
00
11
D2
C1
00
52
53
54
55
56
57
58
59
60
61
62
63
64
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
65 -71 JEDEC ID Code of Infineon (2 - 8)
72
73
74
75
76
77
78
79
80
81
82
83
84
Module Manufacturer Location
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
xx
36
34
54
33
32
30
30
30
48
44
4C
33
xx
36
34
54
36
34
30
32
30
48
44
4C
33
xx
36
34
54
31
32
38
30
32
31
48
44
4C
Data Sheet
29
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
SPD Codes
Table 19
SPD Codes for HYS64T[32/64/128]0xxHDL–3.7–A (cont’d)
Product Type
Organization
256 MB
×64
512 MB
×64
1 GByte
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
2E
37
41
20
20
20
2x
Rev. 1.1
HEX
2E
37
41
20
20
20
2x
xx
Rev. 1.1
HEX
33
2E
37
41
20
20
2x
85
86
87
88
89
90
91
92
93
94
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
xx
xx
xx
xx
95 - 98 Module Serial Number (1 - 4)
99 -127 Not used
xx
00
xx
00
xx
00
Data Sheet
30
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
SPD Codes
Table 20
SPD Codes for HYS64T[32/64/128]0xxHDL–5–A
Product Type
Organization
256 MB
512 MB
1 GByte
×64
×64
×64
1 Rank (×16) 2 Ranks (×16) 2 Ranks (×8)
Label Code
PC2–3200S– PC2–3200S–
PC2–3200S–
333
Rev. 1.1
HEX
80
333
Rev. 1.1
HEX
80
333
JEDEC SPD Revision
Rev. 1.1
HEX
80
08
08
Byte#
0
1
Description
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
08
08
2
08
08
3
4
5
6
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
0D
0A
60
0D
0A
61
0E
0A
61
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
t
t
CK @ CLMAX (Byte 18) [ns]
AC SDRAM @ CLMAX (Byte 18) [ns]
50
60
00
82
10
00
00
0C
04
38
00
04
00
01
50
60
50
50
60
00
82
10
00
00
0C
04
38
00
04
00
01
50
60
50
50
60
00
82
08
00
00
0C
04
38
00
04
00
01
50
60
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
60
60
60
Data Sheet
31
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
SPD Codes
Table 20
SPD Codes for HYS64T[32/64/128]0xxHDL–5–A (cont’d)
Product Type
Organization
256 MB
512 MB
1 GByte
×64
×64
×64
1 Rank (×16) 2 Ranks (×16) 2 Ranks (×8)
Label Code
PC2–3200S– PC2–3200S–
PC2–3200S–
333
Rev. 1.1
HEX
3C
28
333
Rev. 1.1
HEX
3C
28
333
JEDEC SPD Revision
Rev. 1.1
HEX
3C
1E
3C
28
80
35
47
15
27
3C
28
1E
00
00
37
69
80
23
Byte#
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Description
t
t
t
t
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
3C
28
3C
28
Module Density per Rank
40
40
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
35
35
47
47
15
15
27
27
3C
28
3C
28
WTR.MIN [ns]
RTP.MIN [ns]
1E
00
1E
00
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
00
00
37
37
69
69
80
80
23
23
2D
00
2D
00
2D
00
51
78
32
PLL Re-lock Time
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q ( (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
CASE.MAX Delta / ∆T4R4W Delta
51
51
72
72
42
42
23
23
24
1D
19
1D
19
1E
1B
1E
∆T3P.fast (DT3P fast)
1C
1C
Data Sheet
32
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
SPD Codes
Table 20
SPD Codes for HYS64T[32/64/128]0xxHDL–5–A (cont’d)
Product Type
Organization
256 MB
512 MB
1 GByte
×64
×64
×64
1 Rank (×16) 2 Ranks (×16) 2 Ranks (×8)
Label Code
PC2–3200S– PC2–3200S–
PC2–3200S–
333
Rev. 1.1
HEX
16
333
Rev. 1.1
HEX
16
333
JEDEC SPD Revision
Rev. 1.1
HEX
17
Byte#
54
55
Description
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W)
∆T5B (DT5B)
2E
1A
2D
00
2E
1A
2D
00
28
56
1B
1E
00
57
∆T7 (DT7)
58
Psi(ca) PLL
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
61
62
∆TREG (DTREG) / Toggle Rate
SPD Revision
00
11
00
11
00
11
63
64
65 - 71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Checksum of Bytes 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2 - 8)
Module Manufacturer Location
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
03
C1
00
xx
36
34
54
33
32
30
30
30
48
44
4C
35
41
20
04
C1
00
xx
36
34
54
36
34
30
32
30
48
44
4C
35
41
20
1C
C1
00
xx
36
34
54
31
32
38
30
32
31
48
44
4C
35
41
86
Data Sheet
33
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
SPD Codes
Table 20
SPD Codes for HYS64T[32/64/128]0xxHDL–5–A (cont’d)
Product Type
Organization
256 MB
512 MB
1 GByte
×64
×64
×64
1 Rank (×16) 2 Ranks (×16) 2 Ranks (×8)
Label Code
PC2–3200S– PC2–3200S–
PC2–3200S–
333
Rev. 1.1
HEX
20
333
Rev. 1.1
HEX
20
333
JEDEC SPD Revision
Rev. 1.1
HEX
20
Byte#
87
Description
Product Type, Char 15
88
Product Type, Char 16
20
20
20
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
2x
2x
2x
92
93
94
95 - 98
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1 - 4)
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
99 - 127 Not used
00
00
00
Data Sheet
34
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Package Outlines
6
Package Outlines
67.6
3.8 MAX.
±0.1
63.6
1
100
(2.15)
±0.1
(2.45)
±0.1
1
17.55
0.15
±0.1
2.7
(1.5)
±0.1
11.4
±0.1
47.4
(1.8)
(2.45)
±0.1
(2.15)
200
2.4
±0.1
1
101
2 MIN.
Detail of contacts
±0.03
0.45
±0.1
0.6
Burnished, no burr allowed
GLD09649
Figure 5
Package Outline Raw Card A L-DIM-200-31
Data Sheet
35
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Package Outlines
67.6
3.8 MAX.
±0.1
63.6
1
100
(2.15)
±0.1
(2.45)
±0.1
1
17.55
0.15
±0.1
2.7
(1.5)
±0.1
11.4
±0.1
47.4
(1.8)
(2.45)
±0.1
(2.15)
200
2.4
±0.1
1
101
2 MIN.
Detail of contacts
±0.03
0.45
±0.1
0.6
Burnished, no burr allowed
GLD09648
Figure 6
Package Outline Raw Card C L-DIM-200-30
Data Sheet
36
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Package Outlines
67.6
3.8 MAX.
±0.1
63.6
1
100
(2.15)
±0.1
(2.45)
±0.1
1
17.55
0.15
±0.1
2.7
(1.5)
±0.1
11.4
±0.1
47.4
(1.8)
(2.45)
±0.1
(2.15)
200
2.4
±0.1
1
101
2 MIN.
Detail of contacts
±0.03
0.45
±0.1
0.6
Burnished, no burr allowed
GLD09675
Figure 7
Package Outline Raw Card F - L-DIM-200-34
Data Sheet
37
Rev. 1.0, 2004-10
09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL–[3.7/5]–A
Small Outline DDR2 SDRAM Modules
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
7
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon’s nomenclature uses simple coding combined with some proprietary coding. Table 21 provides examples
for module and component product type number as well as the field number. The detailed field description together
with possible values and coding explanation is listed for modules in Table 22 and for components in Table 23.
Table 21
Example for
Nomenclature Fields and Examples
Field Number
1
HYS
HYB
2
64
18
3
T
T
4
64
512
5
0
16
6
2
7
0
0
8
K
A
9
M
C
10
–5
–5
11
–A
Micro-DIMM
DDR2 DRAM
1) Multiplying “Memory Density per I/O” with “Module Data
Width” and dividing by 8 for Non-ECC and 9 for ECC
modules gives the overall module memory density in
MBytes as listed in column “Coding”.
Table 22
Field Description
DDR2 DIMM Nomenclature
Values Coding
1
INFINEON
HYS
Constant
Modul Prefix
2
Module Data
64
72
T
Non-ECC
ECC
DDR2
Table 23
Field Description
DDR2 DRAM Nomenclature
Values Coding
Width [bit]
3
4
DRAM
1
INFINEON
HYB
Constant
Technology
Component Prefix
Memory Density
32
64
128
256
0 .. 9
256 MByte
512 MByte
1 GByte
2 GByte
look up table
2
3
4
Interface Voltage [V] 18
DRAM Technology
Component Density 256
SSTL1.8
DDR2
256 Mbit
512 Mbit
1 Gbit
2 Gbit
×4
per I/O [Mbit];
T
Module Density1)
[Mbit]
512
1G
2G
40
5
6
Raw Card
Generation
Number of Module 0, 2, 4 1, 2, 4
5+6 Number of I/Os
Ranks
80
×8
7
8
Product Variations 0 .. 9
look up table
look up table
16
×16
Package,
A .. Z
7
8
Product Variations 0 .. 9
Die Revision
look up table
First
Second
Lead-Free Status
A
B
C
9
Module Type
D
M
R
U
–3.7
–5
–A
–B
SO-DIMM
Micro-DIMM
Registered
Unbuffered
PC2–4200 4–4–4
PC2–3200 3–3–3
First
9
Package,
FBGA,
Lead-Free Status
lead-containing
F
–3.7
–5
FBGA, lead-free
DDR2-533C
DDR2-400B
10
11
Speed Grade
Die Revision
10
11
Speed Grade
N/A for Components
Second
Data Sheet
38
Rev. 1.0, 2004-10
09122003-FTXN-KM26
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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