HYS64T128021HDL-37-A [INFINEON]
200-Pin Small Outline Dual-In-Line Memory Module; 200引脚小外形双列直插式内存模块
| 型号： | HYS64T128021HDL-37-A |
| 厂家： | 
Infineon |
| 描述： | 200-Pin Small Outline Dual-In-Line Memory Module |
| 文件： | 总48页 (文件大小：1116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 0.91, June 2004
HYS64T32000[G/H]DL–[3.7/5]–A
HYS64T64020[G/H]DL–[3.7/5]–A
HYS64T128021[G/H]DL–[3.7/5]–A
200-Pin Small Outline Dual-In-Line Memory Module
SO-DIMM
DDR2 SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
Edition 2004-06
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, Rev. 0.91, June 2004
HYS64T32000[G/H]DL–[3.7/5]–A
HYS64T64020[G/H]DL–[3.7/5]–A
HYS64T128021[G/H]DL–[3.7/5]–A
200-Pin Small Outline Dual-In-Line Memory Module
SO-DIMM
DDR2 SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
all
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
Revision History:
Rev. 0.91
2004-06
Previous Revision:
Rev. 0.83
2003-09
Page
all
Subjects (major changes since last revision)
editorial changes
all
removed HYS64T128022HDL products and all -3 products
added HYS64T128021[G/]DL products
all
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Template: mp_a4_v2.2_2003-10-07.fm
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1
1.2
1.3
2
3
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
4.1
4.2
I
DD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I
ODT (On Die Termination) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical Characteristics & AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5
6
7
8
Data Sheet
5
Rev. 0.91, 2004-06
09122003-FTXN-KM26
200-Pin Small Outline Dual-In-Line Memory Module
DDR2 SDRAM
HYS64T32000[G/H]DL–[3.7/5]–A
HYS64T64020[G/H]DL–[3.7/5]–A
HYS64T128021[G/H]DL–[3.7/5]–A
1
Overview
This chapter gives an overview of the 1.8 V 200-Pin Small Outline Dual-In-Line Memory Module, 256 MByte and
512 MByte and describes its main characteristics.
1.1
Features
•
•
•
•
200-pin Non-ECC Unbuffered 8-Byte Dual-In-Line
DDR2 SDRAM Module for Notebooks and other
application where small form factors are required.
One rank 32M × 64, two ranks 64M × 64 and
128M × 64 module organisation and 32M × 16 and
64M × 8 chip organisation
JEDEC standard Double-Data-Rate-Two
Synchronous DRAMs (DDR2 SDRAM) with a single
+ 1.8 V (± 0.1 V) power supply
256 ,512 MByte and 1GByte modules built with
512Mb DDR2 SDRAMs in 60-ball FBGA
(P–TFBGA–60) and 84-ball FBGA (P–TFBGA–84)
chipsize packages
•
Programmable CAS Latencies (3, 4 and 5), Burst
Length (4 & 8) and Burst Type
•
•
•
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment(OCD) and
On-Die Termination(ODT)
•
•
Serial Presence Detect with E2PROM
Low Profile Modules form factor: 67.60 mm x 30.00
mm (MO-224)
•
Based on JEDEC standard reference layouts Raw
Card “A”, “C” and “D”
Table 1
Performance
Product Type Speed Code
Speed Grade
–3.7
PC2–4200 4–4–4
fCK5 266
–5
Units
—
PC2–3200 3–3–3
max. Clock Frequency
@CL5
@CL4
@CL3
200
200
200
15
MHz
MHz
MHz
ns
fCK4 266
fCK3 200
tRCD 15
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
tRP
tRAS 45
tRC 60
15
15
ns
40
ns
55
ns
1.2
Description
The INFINEON
The memory array is designed with 512Mb Double-
Data-Rate-Two (DDR2) Synchronous DRAMs.
Decoupling capacitors are mounted on the PCB board.
The DIMMs feature serial presence detect based on a
serial E2PROM device using the 2-pin I2C protocol. The
first 128 bytes are programmed with configuration data
and are write protected; the second 128 bytes are
available to the customer.
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
module family are low profile SO-DIMM modules with
30,0 mm height based on DDR2 technology. DIMMs
are available as Non-ECC modules in 32M × 64
(256 MByte),64M × 64 (512 MByte) and 128M × 64
(1 GByte) organisation and density, intended for
mounting into 200-pin connector sockets.
Data Sheet
6
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 2
Ordering Information
Product Type
Compliance Code
Description
SDRAM
Technology
HYS64T32000GDL–3.7–A
HYS64T64020GDL–3.7–A
HYS64T128021GDL–3.7–A
HYS64T32000GDL–5–A
HYS64T64020GDL–5–A
HYS64T128021GDL–5–A
PC2–4200S–444–10–C0 one rank 256 MByte SO–DIMM
512 Mbit (×16)
PC2–4200S–444–10–A0 two ranks 512 MByte SO–DIMM 512 Mbit (×16)
PC2–4200S–444–10–D0 two ranks 1 GByte SO–DIMM
PC2–3200S–333–10–C0 one rank 256 MByte SO–DIMM
512 Mbit (× 8)
512 Mbit (×16)
PC2–3200S–333–10–A0 two ranks 512 MByte SO–DIMM 512 Mbit (×16)
PC2–3200S–333–10–D0 two ranks 1 GByte SO–DIMM
512 Mbit (× 8)
HYS64T32000HDL–3.7–A
HYS64T64020HDL–3.7–A
HYS64T128021HDL–3.7–A
HYS64T32000HDL–5–A
HYS64T64020HDL–5–A
HYS64T128021HDL–5–A
PC2–4200S–444–10–C0 one rank 256 MByte SO–DIMM
512 Mbit (×16)
PC2–4200S–444–10–A0 two ranks 512 MByte SO–DIMM 512 Mbit (×16)
PC2–4200S–444–10–D0 two ranks 1 GByte SO–DIMM
PC2–3200S–333–10–C0 one rank 256 MByte SO–DIMM
512 Mbit (× 8)
512 Mbit (×16)
PC2–3200S–333–10–A0 two ranks 512 MByte SO–DIMM 512 Mbit (×16)
PC2–3200S–333–10–D0 two ranks 1 GByte SO–DIMM 512 Mbit (× 8)
Note:The Compliance Code is printed on the module label and describes the speed grade,e.g. "512MB 2R×16
PC2–3200S–33310–A" where "512MB" tells the density in megabytes, "2Rx16" means 2 ranks on module
built of ×16 components, "PC2–3200S" means DDR2 SO-DIMM with 4.26 GB/s module bandwidth and "444-
11" means CAS latency of 4, RCD1) latency of 4, and RP2) latency of 4 using Jedec SPD revision 1.0. All
part numbers end with a place code, designating the silicon die revision. Example: HYS64T32000GDL–3.7–
A, indicating Rev. A dice are used for DDR2 SDRAM components. For all INFINEON DDR2 module and
component nomenclature see Chapter 8 of this datasheet.
Table 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
# of
SDRAMs
# of row/bank/column bits
Raw
Card
256 MB
512 MB
1 GB
32M ×64
64M ×64
128M ×64
1
2
2
4
13/2/10
13/2/10
14/2/10
C
A
D
8
16
1) RCD: Row Column Delay
2) RP: Row Precharge
Data Sheet
7
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 4
Components on Modules1)
Product Type
DRAM Components
DRAM Density
DRAM Organisation
HYS64T32000GDL
HYS64T64020GDL
HYS64T32000HDL2)
HYS64T64020HDL2)
HYS64T128021GDL
HYS64T128021HDL2)
HYB18T512160AC
512 Mbit
32M ×16
HYB18T512160AF2)
512 Mbit
32M ×16
HYB18T512800AC
HYB18T512800AF2)
512 Mbit
512 Mbit
64M ×8
64M ×8
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
2) Green Product
1.3
Pin Configuration
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The
abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin
numbering is depicted in Figure 1
Table 5
Pin#
Pin Configuration of SO-DIMM
Name Pin
Buffer Function
Type Type
Clock Signals
30
CK0
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Clock Signals 2:0
164
32
CK1
CK0
Complement Clock Signals 2:0
166
79
CK1
CKE0
CKE1
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
80
NC
NC
—
Control Signals
110
115
S0
S1
I
I
SSTL
SSTL
Chip Select Rank 0
Chip Select Rank 1
Note: 2-rank module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
NC
NC
—
108
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
113
109
Address Signals
107
106
102
101
100
99
BA0
BA1
A0
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Address Bus 4:0
A1
A2
A3
98
A4
Data Sheet
8
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin#
Pin Configuration of SO-DIMM (cont’d)
Name Pin Buffer Function
Type Type
97
94
92
93
91
105
A5
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Bus 11:5
A6
A7
A8
A9
A10
AP
A11
A12
A13
90
89
Address Signal 12
116
Address Signal 13
Note: 512M ×4/×8
NC
NC
—
Note: Module based on 512 Mbit ×16
Data Signals
5
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 26:0
7
DQ1
17
19
4
DQ2
DQ3
DQ4
6
DQ5
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
Data Sheet
9
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin#
Pin Configuration of SO-DIMM (cont’d)
Name Pin Buffer Function
Type Type
75
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:27
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
Data Strobe Signals
Data Sheet
10
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin#
Pin Configuration of SO-DIMM (cont’d)
Name Pin Buffer Function
Type Type
13
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
DQS6 I/O
DQS7 I/O
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
DQS6 I/O
DQS7 I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobe Bus 7:0
Note: See block diagram for corresponding DQ
signals
31
51
70
131
148
169
188
11
Complement Data Strobe Bus 7:0
Note: See block diagram for corresponding DQ
signals
29
49
68
129
146
167
186
Data Mask Signals
10
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Mask Bus 7:0
26
52
67
130
147
170
185
EEPROM
197
SCL
SDA
SA0
SA1
I
CMOS Serial Bus Clock
OD Serial Bus Data
195
I/O
198
I
I
CMOS Slave Address Select Bus 2:0
200
CMOS
Power Supplies
1
VREF
AI
—
—
—
I/O Reference Voltage
EEPROM Power Supply
Power Supply
199
VDDSPD PWR
81,82,87,88,95,96,103,104,
111,112,117,118
VDD
PWR
2,3,8,9,12,15,18,21,24,27,28, VSS
33,34,39,40,41,42,47,48,53,
54,59,60,65,66,71,72,77,78,
121,122,127,128,132,133,138,
139,144,145,149,150,155,156,
161,162,165,168,171,172,177,
178,183,184,187,190,193,196
GND
—
Ground Plane
Data Sheet
11
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin#
Pin Configuration of SO-DIMM (cont’d)
Name Pin Buffer Function
Type Type
Other Pins
114
ODT0
ODT1
NC
On-Die Termination Control 0
119
On-Die Termination Control 1
Note: 1 Rank modules
50,69,83,84,85,120,163
NC
NC
—
Not connected
Note: Pins not connected on Infineon SO-DIMMs
Table 6
Abbreviations for Pin Type
Description
Abbreviation
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
Table 7
Abbreviation
SSTL
Abbreviations for Buffer Type
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Data Sheet
12
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
VREF - Pin 001
DQ0 - Pin 005
VSS - Pin 009
Pin 002 -
Pin 006 -
Pin 010 -
Pin 014 -
Pin 018 -
Pin 022 -
Pin 026 -
Pin 030 -
Pin 034 -
Pin 038 -
VSS
VSS - Pin 003
DQ1 - Pin 007
DQS0 - Pin 011
VSS - Pin 015
Pin 004 -
DQ4
DQ5
DM0
DQ6
VSS
Pin 008 - VSS
Pin 012 - VSS
Pin 016 - DQ7
Pin 020 - DQ12
Pin 024 - VSS
Pin 028 - VSS
Pin 032 - CK0
Pin 036 - DQ14
Pin 040 - VSS
DQS0 - Pin 013
DQ2 - Pin 017
VSS - Pin 021
DQ3 - Pin 019
DQ8 - Pin 023
VSS - Pin 027
DQ13
DM1
CK0
VSS
DQ9 - Pin 025
DQS1 - Pin 029
VSS - Pin 033
DQS1 - Pin 031
DQ10 - Pin 035
VSS - Pin 039
DQ11 - Pin 037
DQ15
VSS - Pin 041
DQ17 - Pin 045
DQS2 - Pin 049
VSS - Pin 053
DQ19 - Pin 057
DQ24 - Pin 061
VSS - Pin 065
NC - Pin 069
DQ26 - Pin 073
VSS - Pin 077
VDD - Pin 081
NC - Pin 085
A12 - Pin 089
A8 - Pin 093
Pin 042 - VSS
Pin 046 - DQ21
Pin 050 - NC
Pin 054 - VSS
Pin 058 - DQ23
Pin 062 - DQ28
Pin 066 - VSS
Pin 070 - DQS3
Pin 074 - DQ30
Pin 078 - VSS
Pin 082 - VDD
Pin 086 - A14
Pin 090 - A11
Pin 094 - A6
DQ16 - Pin 043
VSS - Pin 047
Pin 044 - DQ20
Pin 048 - VSS
Pin 052 - DM2
Pin 056 - DQ22
Pin 060 - VSS
Pin 064 - DQ29
Pin 068 - DQS3
Pin 072 - VSS
Pin 076 - DQ31
Pin 080 - NC/CKE1
Pin 084 - NC
Pin 088 - VDD
Pin 092 - A7
DQS2 - Pin 051
DQ18 - Pin 055
VSS - Pin 059
DQ25 - Pin 063
DM3 - Pin 067
VSS - Pin 071
DQ27 - Pin 075
CKE0 - Pin 079
NC - Pin 083
VDD - Pin 087
A9 - Pin 091
VDD - Pin 095
A3 - Pin 099
Pin 096 - VDD
Pin 100 - A2
A5 - Pin 097
Pin 098 - A4
A1 - Pin 101
Pin 102 - A0
VDD - Pin 103
BA0 - Pin 107
VDD - Pin 111
NC/CS1 - Pin 115
ODT1 - Pin 119
DQ32 - Pin 123
VSS - Pin 127
Pin 104 - VDD
Pin 108 - RAS
Pin 112 - VDD
Pin 116 - A13
Pin 120 - NC
Pin 124 - DQ36
Pin 128 - VSS
Pin 132 - VSS
Pin 136 - DQ39
Pin 140 - DQ44
Pin 144 - VSS
Pin 148 - DQS5
Pin 152 - DQ46
Pin 156 - VSS
Pin 160 - DQ53
Pin 164 - CK1
Pin 168 - VSS
Pin 172 - VSS
Pin 176 - DQ55
Pin 180 - DQ60
Pin 184 - VSS
Pin 188 - DQS7
Pin 192 - DQ62
Pin 196 - VSS
Pin 200 - SA1
A10/AP - Pin 105
WE - Pin 109
CAS - Pin 113
VDD - Pin 117
VSS - Pin 121
DQ33 - Pin 125
DQS4 - Pin 129
VSS - Pin 133
DQ35 - Pin 137
DQ40 - Pin 141
VSS - Pin 145
VSS - Pin 149
DQ43 - Pin 153
DQ48 - Pin 157
VSS - Pin 161
VSS - Pin 165
DQS6 - Pin 169
DQ50 - Pin 173
VSS - Pin 177
DQ57 - Pin 181
DM7 - Pin 185
DQ58 - Pin 189
VSS - Pin 193
SCL - Pin 197
Pin 106 - BA1
Pin 110 - CS0
Pin 114 - ODT0
Pin 118 - VDD
Pin 122 - VSS
Pin 126 - DQ37
Pin 130 - DM4
Pin 134 - DQ38
Pin 138 - VSS
Pin 142 - DQ45
Pin 146 - DQS5
Pin 150 - VSS
Pin 154 - DQ47
Pin 158 - DQ52
Pin 162 - VSS
Pin 166 - CK1
Pin 170 - DM6
Pin 174 - DQ54
Pin 178 - VSS
Pin 182 - DQ61
Pin 186 - DQS7
Pin 190 - VSS
Pin 194 - DQ63
Pin 198 - SA0
DQS4 - Pin 131
DQ34 - Pin 135
VSS - Pin 139
DQ41 - Pin 143
DM5 - Pin 147
DQ42 - Pin 151
VSS - Pin 155
DQ49 - Pin 159
NC - Pin 163
DQS6 - Pin 167
VSS - Pin 171
DQ51 - Pin 175
DQ56 - Pin 179
VSS - Pin 183
VSS - Pin 187
DQ59 - Pin 191
SDA - Pin 195
VDD SPD - Pin 199
MPPT0140
Figure 1
Pin Configuration SO-DIMM (200 Pin)
Data Sheet
13
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 8
Symbol
Input/Output Functional Description
Type
Polarity Function
CK[1:0],
CK[1:0]
I
Cross
point
The system clock inputs. All address and command lines are sampled on the
cross point of the rising edge of CK and the falling edge of CK. A Delay Locked
Loop (DLL) circuit is driven from the clock inputs and output timing for read
operations is synchronized to the input clock.
CKE[1:0]
S[1:0]
I
I
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal
when low. By deactivating the clocks, CKE low initiates the Power Down Mode
or the Self Refresh Mode.
Active
Low
Enables the associated DDR2 SDRAM command decoder when low and
disables the command decoder when high. When the command decoder is
disabled, new commands are ignored but previous operations continue. Rank 0
is selected by S0; Rank 1 is selected by S1.
RAS, CAS, I
WE
Active
Low
When sampled at the cross point of the rising edge of CK,and falling edge of CK,
RAS, CAS and WE define the operation to be executed by the SDRAM.
BA[1:0]
I
I
—
Selects internal SDRAM memory bank
ODT[1:0]
Active
High
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the
DDR2 SDRAM mode register.
A[9:0],
A10/AP,
A[13:11]
I
—
During a Bank Activate command cycle, defines the row address when sampled
at the crosspoint of the rising edge of CK and falling edge of CK. During a Read
or Write command cycle, defines the column address when sampled at the cross
point of the rising edge of CK and falling edge of CK. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn
defines the bank to be precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA[1:0] to
control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA[1:0] inputs. If AP is low, then BA[1:0] are used to
define which bank to precharge.
DQ[63:0]
DM[7:0]
I/O
I
—
Data Input/Output pins
Active
High
The data write masks, associated with one data byte. In Write mode, DM
operates as a byte mask by allowing input data to be written if it is low but blocks
the write operation if it is high. In Read mode, DM lines have no effect.
DQS[7:0], I/O
DQS[7:0]
Cross
point
The data strobes, associated with one data byte, sourced with data transfers. In
Write mode, the data strobe is sourced by the controller and is centered in the
data window. In Read mode the data strobe is sourced by the DDR2 SDRAM
and is sent at the leading edge of the data window. DQS signals are
complements, and timing is relative to the crosspoint of respective DQS and
DQS. If the module is to be operated in single ended strobe mode, all DQS
signals must be tied on the system board to VSS through a 20 ohm to 10 Kohm
resistor and DDR2 SDRAM mode registers programmed appropriately.
VDD,
Supply
—
—
Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
V
DDSPD, VSS
SDA
I/O
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM.
A resistor must be connected from SDA to VDDSPD on the motherboard to act as
a pull-up.
SCL
I
I
—
—
This signal is used to clock data into and out of the SPD EEPROM.
Address pins used to select the Serial Presence Detect base address.
SA[1:0]
Data Sheet
14
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
2
Block Diagrams
3.0
Ω
+/- 5%
CS0
CS
CS
LDQS
LDQS
LDM
DQS0
LDQS
LDQS
LDM
DQS4
DQS4
DM4
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
D0
D2
DQS5
DQS1
UDQS
UDM
UDQS
UDM
DQS5
DQS1
DM5
DM1
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 8
I/O 8
DQ9
I/O 9
I/O 9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
I/O 10
I/O 11
I/
O 12
I/O 13
I/0 14
I/O 15
CS
CS
LDQS
LDQS
LDM
LDQS
LDQS
LDM
DQS6
DQS6
DM6
DQS2
DQS2
DM2
DQ48
DQ49
DQ50
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
DQ51
DQ52
DQ53
DQ54
DQ55
D3
D1
DQS7
DQS3
DQS7
DQS3
DM7
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 8
I/O 9
I/O 8
I/O 9
O 10
I/O 10
I/O 11
I/
I/O 11
I/
I/
O 12
O 12
I/O 13
I/0 14
I/O 15
I/O 13
I/0 14
I/O 15
V
EEPROM
D0 - D3
DDSPD
Clock Wiring
SDRAMs
2 SDRAMs
Serial PD
Clock Input
V
SDA
DD
VREF
(VDD&VDDQ)
D0 - D3
CK0, CK0
CK1, CK1
SCL
WP A0
SA0 SA1
A1 A2
2
SDRAMs
V
SS
D0 - D3
3.0Ω+/- 5%
BA0, BA1
BA0, BA1 : SDRAMs D0 - D3
A0 - A12 : SDRAMs D0 - D3
DQ-to-I/O wiring may be changed within a byte
DQ/DQS/DQS/DM/CKE/CS relationships must be maintained as shown
DQ/DQS/DQS/DM resistors are 22 +/- 5%
Address and control resistors are 3.0 +/- 5%
A0 - A12
RAS
RAS
CAS
WE
CKE
ODT
: SDRAMs D0 - D3
: SDRAMs D0 - D3
: SDRAMs D0 - D3
: SDRAMs D0 - D3
: SDRAMs D0 - D3
Ω
CAS
WE
CKE0
ODT0
Ω
Figure 2
Note
Block Diagram Raw Card C (32M x 64, 1 rank, x16)
1. DQ, DQS, DQS, DM resistors are 22 Ω ±5 %
2. S0, S1, BAn, An, RAS, CAS, WE, ODT0, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
Data Sheet
15
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
CS1
CS0
3.0Ω+/- 5%
CS
CS
CS
CS
DQS0
DQS0
DM0
LDQS
LDQS
LDM
LDQS
LDQS
LDM
DQS4
DQS4
DM4
LDQS
LDQS
LDM
LDQS
LDQS
LDM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
D0
D4
D2
D6
DQS1
DQS5
UDQS
UDM
UDQS
UDM
UDQS
UDM
DQS1
DQS5
UDQS
UDM
DM1
DM5
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 8
I/O 8
I/O 8
I/O 8
DQ9
I/O 9
I/O 9
I/O 9
I/O 9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
I/O 10
I/O 11
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
I/O 10
I/O 11
I/
O 12
I/
O 12
I/O 13
I/0 14
I/O 15
I/O 13
I/0 14
I/O 15
CS
CS
CS
CS
LDQS
LDQS
LDM
DQS6
DQS6
DM6
LDQS
LDQS
LDM
DQS2
DQS2
DM2
LDQS
LDQS
LDQS
LDQS
LDM
LDM
DQ48
DQ49
DQ50
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
DQ51
DQ52
DQ53
DQ54
DQ55
D1
D3
D5
D7
DQS3
DQS7
UDQS
UDM
UDQS
UDM
I/O 8
I/O 9
DQS3
UDQS
UDM
DQS7
UDQS
UDM
DM3
DM7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 8
I/O 8
I/O 8
I/O 9
I/O 9
I/O 9
I/
O 10
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
I/O 10
I/O 11
I/O 10
I/O 11
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
I/
I/
O 12
O 12
I/O 13
I/0 14
I/O 15
I/O 13
I/0 14
I/O 15
V
EEPROM
D0 - D7
DDSPD
Clock Wiring
Serial PD
SDRAMs
Clock Input
SDA
V
DD
(VDD & VDDQ)
D0 - D7
SCL
WP A0
SA0 SA1
A1 A2
CK0, CK0
CK1, CK1
4 SDRAMs
VREF
4
SDRAMs
V
D0 - D7
SS
BA0, BA1
BA0, BA1 : SDRAMs D0 - D3
A0 - A12 : SDRAMs D0 - D3
DQ-to-I/O wiring may be changed within a byte
DQ/DQS/DQS/DM/CKE/CS relationships must be maintained as shown
DQ/DQS/DQS/DM resistors are 22 +/- 5%
Address and control resistors are 3.0 +/- 5%
A0 - A12
RAS
Ω
RAS
CAS
WE
: SDRAMs D0 - D3
: SDRAMs D0 - D3
: SDRAMs D0 - D3
CAS
WE
Ω
CKE0
CKE1
CKE
CKE
: SDRAMs D0 - D3
: SDRAMs D4 - D7
ODT0
ODT1
ODT
ODT
: SDRAMs D0 - D3
: SDRAMs D4 - D7
Figure 3
Block Diagram Raw Card A (64M x 64, 2 ranks, x16)
Note
1. DQ, DQS, DQS, DM resistors are 22 Ω ±5 %
2. S0, S1, BAn, An, RAS, CAS, WE, ODT0, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
Data Sheet
16
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
10
Ω
+/- 5%
CKE1
ODT1
CS1
CKE0
ODT0
CS0
CS0 ODT0 CKE0 CS1 ODT1 CKE1
D0, D8 (dual die)
CS0 ODT0 CKE0 CS1 ODT1 CKE1
D4, D12 (dual die)
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DQS
DQS
DM
DQS
DQS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS0 ODT0 CKE0 CS1 ODT1 CKE1
CS0 ODT0 CKE0 CS1 ODT1 CKE1
D5, D13 (dual die)
DQS1
DQS1
DM1
DQS
DQS
DM
DQS5
DQS5
DM5
DQS
DQS
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1, D0 (dual die)
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS0 ODT0 CKE0 CS1 ODT1 CKE1
CS0 ODT0 CKE0 CS1 ODT1 CKE1
D6, D14 (dual die)
DQS2
DQS2
DM2
DQS
DQS
DM
DQS6
DQS6
DM6
DQS
DQS
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2, D10 (dual die)
CS0 ODT0 CKE0 CS1 ODT1 CKE1
D3, D11 (dual die)
CS0 ODT0 CKE0 CS1 ODT1 CKE1
D7, D15 (dual die)
DQS3
DQS3
DM3
DQS
DQS
DM
DQS7
DQS7
DM7
DQS
DQS
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
V
EEPROM
Serial PD
DDSPD
SDA
VDD
D0 - D15, VDD, VDDQ
SCL
WP A0
SA0 SA1
A1 A2
VREF
D0 - D15
D0 - D15
V
SS
Clock Wiring
SDRAMs
loads
10
Ω
+/- 5%
Clock Input
BA0, BA1
BA0, BA1 : SDRAMs D0 - D15
A0 - A13 : SDRAMs D0 - D15
RAS
CAS
WE
A0 - A13
RAS
CK0, CK0
CK1, CK1
8
8
: SDRAMs D0 - D15
: SDRAMs D0 - D15
: SDRAMs D0 - D15
loads
CAS
WE
Unless otherwise noted, resistor values are 22
Ω +/- 5%.
DQ wiring may differ from that described in this drawing, however
DQ, DM, DQS, DQS relationship are maintained as shown
Figure 4
Note
Block Diagram Raw Card D (128M x 64, 2 ranks, x8)
1. DQ, DQS, DQS, DM resistors are 22 Ω ±5 %
2. S0, S1, BAn, An, RAS, CAS, WE, ODT0, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
Data Sheet
17
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics
3
Electrical Characteristics
Table 9
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Min.
Unit
Note/Test
Condition
Max.
2.3
1)
1)
1)
1)
1)
Voltage on any pins relative to VSS
Voltage on VDD relative to VSS
VIN, VOUT
VDD
– 0.5
– 1.0
– 0.5
+69
V
V
2.3
Voltage on VDD Q relative to VSS
VDDQ
2.3
Barometric Pressure (operating & storage)
Storage Humidity (without condensation)
+105
95
kPa
%
HSTG
5
1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Table 10
Operating Temperature Range
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
+65
DIMM Module Operating Temperature Range (ambient)
DRAM Component Case Temperature Range
Storage temperature
TOPR
TCASE
TSTG
0
°C
1)2)3)4)
0
+95
°C
– 55
+69
10
+100
+105
90
°C
5)
Barometric Pressure (operating & storage)
Operating Humidity (relative)
kPa
HOPR
%
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For
measurement conditions, please refer to the JEDEC document JESD51-2
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
3) Above 85 °C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below
85 °C case temperature before initiating self-refresh operation.
5) Up to 3000 m.
Table 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
Unit
Notes
Min.
Nom.
Max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
VDD
1.7
1.8
1.9
V
1)
2)
VDDQ
VREF
VDDSPD
VIH (DC)
VIL (DC)
IL
1.7
1.8
1.9
V
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
3.6
V
1.7
—
—
—
—
V
DC Input Logic High
V
REF + 0.125
VDDQ +0.3
VREF –0.125
5
V
DC Input Logic Low
– 0.30
– 5
V
3)
In / Output Leakage Current
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ
.
3) For any pin on the DIMM connector under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V.
Data Sheet
18
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
4
IDD Specifications and Conditions
Table 12
I
DD Measurement Conditions1)2)
Parameter
Symbol
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.
,
tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
IDD2N
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current
IDD2Q
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Power-Down Current
All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
IDD3P(0)
IDD3P(1)
IDD3N
Active Power-Down Current
All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.
;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.
;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
IDD5B
tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
IDD5D
t
CK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
19
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
Table 12
I
DD Measurement Conditions1)2) (cont’d)
Parameter
Symbol
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85 °C
max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) For details and notes see the relevant INFINEON component data sheet
Table 13
IDD Specification HYS64T[32000/64020][G/H]DL
Product Type
Unit Notes
Organization 256 MB 256 MB 512 MB 512 MB 256 MB 256 MB 512 MB 512 MB
×64 ×64 ×64 ×64 ×64 ×64 ×64 ×64
1 Rank 1 Rank 2 Ranks 2 Ranks 1 Rank 1 Rank 2 Ranks 2 Ranks
Symbol
IDD0
Max.
280
300
20
Max.
280
300
20
Max.
300
320
30
Max.
300
320
30
Max.
320
360
20
Max.
320
360
20
Max.
340
380
30
Max.
340
380
30
1)2)
mA
1)2)
IDD1
mA
1)3)
IDD2P
mA
1)3)
IDD2N
130
100
50
130
100
50
260
200
100
40
260
200
100
40
160
120
60
160
120
60
320
240
130
40
320
240
130
40
mA
1)3)
IDD2Q
mA
1)3)
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
mA
1)3)
20
20
20
20
mA
1)3)
140
340
360
480
20
140
340
360
480
20
280
360
380
500
50
280
360
380
500
50
160
400
440
520
20
160
400
440
520
20
320
420
460
540
50
320
420
460
540
50
mA
1)2)
IDD4R
mA
1)2)
IDD4W
mA
1)2)
IDD5B
mA
1)3)
IDD5D
mA
1)4)
IDD6
20
20
30
30
20
20
30
30
mA
1)2)
IDD7
840
840
860
860
880
880
900
900
mA
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
4) standard
Data Sheet
20
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
Table 14
IDD Specification HYS64T128021[G/H]DL
Product Type
Unit Notes
Organization 1 GB
1 GB
×64
2 Ranks
Max.
472
512
64
1 GB
×64
2 Ranks
Max.
552
632
64
1 GB
×64
2 Ranks
Max.
552
632
64
×64
2 Ranks
Max.
Symbol
IDD0
1)2)
472
512
64
mA
1)2)
IDD1
mA
1)3)
IDD2P
mA
1)3)
IDD2N
512
400
208
80
512
400
208
80
640
480
256
80
640
480
256
80
mA
1)3)
IDD2Q
mA
1)3)
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
mA
1)3)
mA
1)3)
560
592
632
976
96
560
592
632
976
96
640
752
792
1060
96
640
752
792
1060
96
mA
1)2)
IDD4R
mA
1)2)
IDD4W
mA
1)2)
IDD5B
mA
1)3)
IDD5D
mA
1)4)
IDD6
64
64
64
64
mA
1)2)
IDD7
1072
1072
1312
1312
mA
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
4) standard
Data Sheet
21
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
4.1
IDD Test Conditions
For testing the IDD parameters, the timing parameters as in Table 15 are used.
Table 15
I
DD Measurement Test Condition
Symbol
Parameter
-3.7
-5
Unit
PC2-4200-4-4-4 PC2-3200-3-3-3
CAS Latency
CLmin
tCKmin
tRCDmin
tRCmin
4
3
tCK
ns
ns
ns
Clock Cycle Time
3.75
15
60
5
Active to Read or Write delay
15
55
Active to Active / Auto-Refresh command
period
Active bank A to Active bank B command
delay
tRRDmin
10
10
ns
Active to Precharge Command
tRASmin
tRASmax
tRPmin
45
40
ns
ns
ns
ns
70000
15
70000
15
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh
command period
tRFCmin
105
105
Average periodic Refresh interval
tREFI
7.8
7.8
µs
4.2
ODT (On Die Termination) Current
The ODT function adds additional current consumption current consumption for any terminated input pin,
to the DDR2 SDRAM when enabled by the EMRS(1). depends on the input pin is in tri-state or driving “0” or
Depending on address bits A[6,2] in the EMRS(1) a “1”, as long a ODT is enabled during a given period of
“weak” or “strong” termination can be selected. The time.
Table 16
ODT current per terminated pin
Parameter
Symbol Min. Typ. Max. Unit
EMRS(1) State
mA/DQ A6 = 0, A2 = 1
3.75 mA/DQ A6 = 1, A2 = 0
Enabled ODT current per DQ
ODT is HIGH; Data Bus inputs are FLOATING
IODTO
5
6
7.5
2.5
10
5
3
Active ODT current per DQ
ODT is HIGH; worst case of Data Bus inputs are
STABLE or SWITCHING.
IODTT
12
6
15
mA/DQ A6 = 0, A2 = 1
mA/DQ A6 = 1, A2 = 0
7.5
Note:For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
22
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
5
Electrical Characteristics & AC Timings
Table 17
AC Timing - Absolute Specificatioins –5/–3.7
Parameter
Symbol –3.7
PC2-4200S
Min.
–5
Unit Notes
PC2-3200S
Min.
Max.
+500
+450
0.55
0.55
Max.
+600
+500
0.55
0.55
1)
DQ output access time from CK/CK tAC
DQS output access time from CK/CK tDQSCK
-500
−450
0.45
−600
−500
0.45
ps
1)
ps
1)
CK, CK high-level width
CK, CK low-level width
Clock Half Period
tCH
tCL
tHP
tCK
tCK
1)
0.45
0.45
tCK
1)
min. (tCL, tCH)
5000
3750
600
min. (tCL, tCH)
5000
5000
600
tCK
1)2)
Clock cycle time
8000
8000
—
8000
8000
—
ps
1)3)
ps
1)
Address and control input setup time tIS
Address and control input hold time tIH
ps
1)
600
—
600
—
ps
1)
DQ and DM input hold time
DQ and DM input setup time
tDH
tDS
350
—
400
—
ps
1)
350
—
400
—
ps
1)
Control and Addr. input pulse width tIPW
0.6
—
0.6
—
tCK
(each input)
1)
DQ and DM input pulse width (each tDIPW
input)
0.35
—
—
0.35
—
—
tCK
1)
Data-out high-impedance time from tHZ
tACmax
tACmax
ps
CK/CK
1)
DQ low-impedance from CK / CK
DQS low-impedance from CK / CK
tLZ(DQ)
2×tACmin
tACmax
tACmax
300
2×tACmin
tACmin
—
tACmax
tACmax
350
ps
1)
tLZ(DQS) tACmin
ps
1)
DQS-DQ skew (for DQS &
associated DQ signals)
tDQSQ
—
ps
1)
Data hold skew factor
tQHS
tQH
—
400
—
—
450
—
ps
1)
Data Output hold time from DQS
tHP−tQHS
WL - 0.25
tHP−tQHS
tCK
1)
Write command to 1st DQS latching tDQSS
WL + 0.25 WL − 0.25 WL + 0.25 tCK
transition
1)
1)
1)
1)
DQS input low (high) pulse width
(write cycle)
tDQSL,H 0.35
—
—
—
—
0.35
0.2
0.2
2
—
—
—
—
tCK
tCK
tCK
tCK
DQS falling edge to CLK setup time tDSS
(write cycle)
0.2
0.2
2
DQS falling edge hold time from CLK tDSH
(write cycle)
Mode register set command cycle
time
tMRD
1)
1)
1)
1)
1)
Write preamble
tWPRE
tWPST
tRPRE
tRPST
tRAS
0.25
0.40
0.9
—
0.25
0.40
0.9
—
tCK
tCK
tCK
tCK
ns
Write postamble
0.60
1.1
0.60
1.1
Read preamble
Read postamble
0.40
45
0.60
70000
0.40
40
0.60
70000
Active to Precharge command
Data Sheet
23
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
Table 17
AC Timing - Absolute Specificatioins –5/–3.7
Symbol –3.7
PC2-4200S
Parameter
–5
Unit Notes
PC2-3200S
Min.
Min.
Max.
Max.
1)
Active to Active/Auto-refresh
command period
tRC
60
—
55
—
ns
1)
Auto-refresh to Active/Auto-refresh tRFC
command period
105
15
—
—
105
15
—
—
ns
1)
Active to Read or Write delay (with
and without Auto-Precharge) delay
tRCD
ns
1)
Precharge command period
tRP
15
10
—
—
15
10
—
—
ns
1)
Active bank A to Active bank B
command
tRRD
ns
1)
CAS A to CAS B Command Period tCCD
2
—
—
—
2
—
—
—
tCK
1)
Write recovery time
tWR
15
15
ns
1)
Auto precharge write recovery +
precharge time
tDAL
WR + tRP
WR + tRP
tCK
1)
Internal write to read command delay tWTR
7.5
7.5
—
—
10
—
—
ns
1)
Internal read to precharge command tRTP
7.5
ns
delay
1)
Exit power down to any valid
command
tXARD
2
—
2
—
tCK
(other than NOP or Deselect)
1)
Exit active power-down mode to read tXARDS
command (slew exit, lower power)
6 − AL
—
—
6 − AL
—
—
tCK
1)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
2
2
tCK
1)
Exit Self-Refresh to read command tXSRD
200
—
—
200
—
—
tCK
1)
Exit Self-Refresh to non-read
command
tXSNR
tRFC + 10
t
RFC + 10
ns
1)
CKE minimum high and low pulse
width
tCKE
3
—
3
—
tCK
1)
OCD drive mode output delay
tOIT
0
12
—
0
12
—
ns
1)
Minimum time clocks remain ON
tDELAY
tIS + tCK + tIH
tIS + tCK+ tIH
ns
after CKE asynchronously drops low
1)4)
Average Periodic Refresh Interval
tREFI
—
—
7.8
3.9
—
—
7.8
3.9
µs
1)5)
1) For details and notes see the relevant INFINEON component datasheet
2) CL = 3
3) CL = 4 & 5
4) 0 °C ≤ TCASE ≤ 85 °C
5) 85 °C < TCASE ≤ 95 °C
Data Sheet
24
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
Table 18
ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition
Min.
2
Max.
Unit
tCK
ns
tAOND
tAON
ODT turn-on delay
2
ODT turn-on
tAC(min)
tAC(max) + 1 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC(min) + 2 ns
2 tCK + tAC(max) + 1 ns
ns
2.5
2.5
tCK
ns
ODT turn-off
tAC(min)
tAC(max) + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off delay (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC(min) + 2 ns
2.5 tCK + tAC(max) + 1 ns
ns
3
8
—
—
tCK
tCK
Data Sheet
25
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
6
SPD Codes
Table 19
SPD Codes for HYS 64T[32000/64020] PC2–4200S
Product Type
Organization
512 MB
512 MB
256 MB
×64
256 MB
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
0
1
2
3
4
5
Programmed SPD
Bytes in EEPROM
80
80
80
80
Total number of Bytes 08
in EEPROM
08
08
0D
0A
61
08
08
0D
0A
60
08
08
0D
0A
60
Memory Type
(DDR2)
08
0D
0A
61
Number of Row
Addresses
Number of Column
Addresses
DIMM Rank and
Stacking Information
6
7
8
Data Width
Not used
40
00
05
40
00
05
40
00
05
40
00
05
Interface Voltage
Level
9
t
CK @ CLmax (Byte 18) 3D
[ns]
tAC SDRAM @ CLmax 50
3D
50
00
3D
50
00
3D
50
00
10
11
(Byte 18) [ns]
Error Correction
Support (non-ECC,
ECC)
00
12
13
14
Refresh Rate and
Type
82
10
00
82
10
00
82
10
00
82
10
00
Primary SDRAM
Width
Error Checking
SDRAM Width
Data Sheet
26
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 19
SPD Codes for HYS 64T[32000/64020] PC2–4200S
Product Type
Organization
512 MB
512 MB
256 MB
×64
256 MB
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
15
16
Not used
Burst Length
Supported
0C
0C
0C
0C
17
18
Number of Banks on 04
SDRAM Device
04
38
04
38
04
38
Supported CAS
Latencies
38
19
20
Not used
00
04
00
04
00
04
00
04
DIMM Type
Information
21
22
23
DIMM Attributes
00
00
01
3D
00
01
3D
00
01
3D
Component Attributes 01
CK @ CLmax -1 (Byte 3D
18) [ns]
AC SDRAM @ CLmax - 50
1 [ns]
CK @ CLmax -2 (Byte 50
18) [ns]
AC SDRAM @ CLmax - 60
2 [ns]
t
24
25
26
t
50
50
60
50
50
60
50
50
60
t
t
27
28
29
30
31
t
t
t
t
RP.min [ns]
RRD.min [ns]
RCD.min [ns]
RAS.min [ns]
3C
28
3C
2D
40
3C
28
3C
2D
40
3C
28
3C
2D
40
3C
28
3C
2D
40
Module Density per
Rank
32
33
34
35
t
t
t
t
AS.min and tCS.min [ns] 25
25
37
10
22
25
37
10
22
25
37
10
22
AH.min and tCH.min [ns] 37
DS.min [ns]
DH.min [ns]
10
22
Data Sheet
27
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 19
SPD Codes for HYS 64T[32000/64020] PC2–4200S
Product Type
Organization
512 MB
512 MB
256 MB
×64
256 MB
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
3C
Rev. 1.1
HEX
3C
Rev. 1.1
HEX
3C
Rev. 1.1
HEX
3C
36
37
38
39
t
t
t
WR.min [ns]
WTR.min [ns]
RTP.min [ns]
1E
1E
1E
1E
1E
1E
1E
1E
Analysis
00
00
00
00
Characteristics
40
41
42
43
44
45
46
47
t
t
t
t
t
t
RC and tRFC Extension 00
00
3C
69
80
1E
28
00
53
00
3C
69
80
1E
28
00
53
00
3C
69
80
1E
28
00
53
RC.min [ns]
3C
69
80
1E
28
00
53
RFC.min [ns]
CK.max [ns]
DQSQ.max [ns]
QHS.max [ns]
PLL Relock Time
T
CASE.max Delta /
∆T4R4W Delta
Psi(T-A) DRAM
∆T0 (DT0)
48
49
50
72
52
72
52
2B
72
52
2B
72
52
2B
∆T2N (DT2N, UDIMM) 2B
or ∆T2Q ( (DT2Q,
RDIMM)
51
52
53
54
55
∆T2P (DT2P)
1D
1D
23
1D
1D
23
16
36
1D
1D
23
16
36
1D
1D
23
16
36
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow) 16
∆T4R (DT4R) / ∆T4R4W 36
S Sign (DT4R4W)
56
57
58
59
∆T5B (DT5B)
∆T7 (DT7)
1C
30
00
00
1C
30
00
00
1C
30
00
00
1C
30
00
00
Psi(ca) PLL
Psi(ca) REG
Data Sheet
28
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 19
SPD Codes for HYS 64T[32000/64020] PC2–4200S
Product Type
Organization
512 MB
512 MB
256 MB
×64
256 MB
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
60
61
∆TPLL (DTPLL)
∆TREG (DTREG) /
00
00
00
00
Toggle Rate
62
63
SPD Revision
11
11
11
11
Checksum of Bytes 0- BC
62
BC
BB
BB
64
65
66
67
68
69
70
71
72
JEDEC ID Code of
Infineon (1)
C1
00
00
00
00
00
00
00
C1
00
00
00
00
00
00
00
xx
C1
00
00
00
00
00
00
00
xx
C1
00
00
00
00
00
00
00
xx
JEDEC ID Code of
Infineon (2)
JEDEC ID Code of
Infineon (3)
JEDEC ID Code of
Infineon (4)
JEDEC ID Code of
Infineon (5)
JEDEC ID Code of
Infineon (6)
JEDEC ID Code of
Infineon (7)
JEDEC ID Code of
Infineon (8)
Module Manufacturer xx
Location
73
74
75
76
77
78
Product Type, Char 1 36
Product Type, Char 2 34
Product Type, Char 3 54
Product Type, Char 4 36
Product Type, Char 5 34
Product Type, Char 6 30
36
34
54
36
34
30
36
34
54
33
32
30
36
34
54
33
32
30
Data Sheet
29
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 19
SPD Codes for HYS 64T[32000/64020] PC2–4200S
Product Type
Organization
512 MB
512 MB
256 MB
×64
256 MB
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
32
Rev. 1.1
HEX
30
Rev. 1.1
HEX
30
79
80
81
82
Product Type, Char 7 32
Product Type, Char 8 30
Product Type, Char 9 47
30
30
30
48
47
48
Product Type, Char
10
44
4C
33
2E
37
41
20
20
20
1x
xx
44
44
44
83
84
85
86
87
88
89
90
91
92
93
94
95
Product Type, Char
11
4C
33
2E
37
41
20
20
20
1x
xx
xx
xx
xx
4C
33
2E
37
41
20
20
20
1x
xx
xx
xx
xx
4C
33
2E
37
41
20
20
20
1x
xx
xx
xx
xx
Product Type, Char
12
Product Type, Char
13
Product Type, Char
14
Product Type, Char
15
Product Type, Char
16
Product Type, Char
17
Product Type, Char
18
Module Revision
Code
Test Program
Revision Code
ModuleManufacturing xx
Date Year
ModuleManufacturing xx
Date Week
ModuleManufacturing xx
Date Week
Data Sheet
30
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 19
SPD Codes for HYS 64T[32000/64020] PC2–4200S
Product Type
Organization
512 MB
512 MB
256 MB
×64
256 MB
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
96
97
98
99
ModuleSerialNumber xx
(1)
xx
xx
xx
ModuleSerialNumber xx
(2)
xx
xx
xx
00
FF
xx
xx
xx
00
FF
xx
xx
xx
00
FF
ModuleSerialNumber xx
(3)
ModuleSerialNumber xx
(4)
100 -
127
Not used
00
128-
255
BLANK
FF
Data Sheet
31
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 20
SPD Codes for HYS 64T[32000/64020] PC2-3200S
Product Type
Organization
512 MB
512 MB
256 MB
×64
256 MB
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–3200S–333 PC2–3200S–333 PC2–3200S–333 PC2–3200S–333
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
0
1
2
3
4
5
Programmed SPD
Bytes in EEPROM
80
80
80
80
Total number of Bytes 08
in EEPROM
08
08
0D
0A
61
08
08
0D
0A
60
08
08
0D
0A
60
Memory Type
(DDR2)
08
0D
0A
61
Number of Row
Addresses
Number of Column
Addresses
DIMM Rank and
Stacking Information
6
7
8
Data Width
Not used
40
00
05
40
00
05
40
00
05
40
00
05
Interface Voltage
Level
9
t
CK @ CLmax (Byte 18) 50
[ns]
tAC SDRAM @ CLmax 60
50
60
00
50
60
00
50
60
00
10
11
(Byte 18) [ns]
Error Correction
Support (non-ECC,
ECC)
00
12
13
14
15
Refresh Rate and
Type
82
10
00
00
82
10
00
00
82
10
00
00
82
10
00
00
Primary SDRAM
Width
Error Checking
SDRAM Width
Not used
Data Sheet
32
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 20
SPD Codes for HYS 64T[32000/64020] PC2-3200S
Product Type
Organization
512 MB
512 MB
256 MB
×64
256 MB
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–3200S–333 PC2–3200S–333 PC2–3200S–333 PC2–3200S–333
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
16
17
18
Burst Length
Supported
0C
0C
0C
0C
Number of Banks on 04
SDRAM Device
04
38
04
38
04
38
Supported CAS
Latencies
38
19
20
Not used
00
04
00
04
00
04
00
04
DIMM Type
Information
21
22
23
DIMM Attributes
00
00
01
50
00
01
50
00
01
50
Component Attributes 01
CK @ CLmax -1 (Byte 50
18) [ns]
AC SDRAM @ CLmax - 60
1 [ns]
CK @ CLmax -2 (Byte 50
18) [ns]
AC SDRAM @ CLmax - 60
2 [ns]
t
24
25
26
t
60
50
60
60
50
60
60
50
60
t
t
27
28
29
30
31
t
t
t
t
RP.min [ns]
RRD.min [ns]
RCD.min [ns]
RAS.min [ns]
3C
28
3C
2D
40
3C
28
3C
2D
40
3C
28
3C
2D
40
3C
28
3C
2D
40
Module Density per
Rank
32
33
34
35
36
t
t
t
t
t
AS.min and tCS.min [ns] 35
35
47
15
27
3C
35
47
15
27
3C
35
47
15
27
3C
AH.min and tCH.min [ns] 47
DS.min [ns]
DH.min [ns]
WR.min [ns]
15
27
3C
Data Sheet
33
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 20
SPD Codes for HYS 64T[32000/64020] PC2-3200S
Product Type
Organization
512 MB
512 MB
256 MB
×64
256 MB
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–3200S–333 PC2–3200S–333 PC2–3200S–333 PC2–3200S–333
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
28
Rev. 1.1
HEX
28
Rev. 1.1
HEX
28
Rev. 1.1
HEX
28
37
38
39
t
WTR.min [ns]
RTP.min [ns]
t
1E
1E
1E
1E
Analysis
00
00
00
00
Characteristics
40
41
42
43
44
45
46
47
t
t
t
t
t
t
RC and tRFC Extension 00
00
3C
69
80
23
2D
00
51
00
3C
69
80
23
2D
00
51
00
3C
69
80
23
2D
00
51
RC.min [ns]
3C
69
80
23
2D
00
51
RFC.min [ns]
CK.max [ns]
DQSQ.max [ns]
QHS.max [ns]
PLL Relock Time
T
CASE.max Delta /
∆T4R4W Delta
Psi(T-A) DRAM
∆T0 (DT0)
48
49
50
72
42
72
42
23
72
42
23
72
42
23
∆T2N (DT2N, UDIMM) 23
or ∆T2Q ( (DT2Q,
RDIMM)
51
52
53
54
55
∆T2P (DT2P)
1D
19
1C
1D
19
1C
16
2E
1D
19
1C
16
2E
1D
19
1C
16
2E
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow) 16
∆T4R (DT4R) / ∆T4R4W 2E
S Sign (DT4R4W)
56
57
58
59
60
∆T5B (DT5B)
∆T7 (DT7)
1A
2D
00
00
00
1A
2D
00
00
00
1A
2D
00
00
00
1A
2D
00
00
00
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
Data Sheet
34
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 20
SPD Codes for HYS 64T[32000/64020] PC2-3200S
Product Type
Organization
512 MB
512 MB
256 MB
×64
256 MB
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–3200S–333 PC2–3200S–333 PC2–3200S–333 PC2–3200S–333
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
61
∆TREG (DTREG) /
00
00
00
00
Toggle Rate
62
63
SPD Revision
11
11
0E
11
11
Checksum of Bytes 0- 0E
62
0D
0D
64
65
66
67
68
69
70
71
72
JEDEC ID Code of
Infineon (1)
C1
00
00
00
00
00
00
00
C1
00
00
00
00
00
00
00
xx
C1
00
00
00
00
00
00
00
xx
C1
00
00
00
00
00
00
00
xx
JEDEC ID Code of
Infineon (2)
JEDEC ID Code of
Infineon (3)
JEDEC ID Code of
Infineon (4)
JEDEC ID Code of
Infineon (5)
JEDEC ID Code of
Infineon (6)
JEDEC ID Code of
Infineon (7)
JEDEC ID Code of
Infineon (8)
Module Manufacturer xx
Location
73
74
75
76
77
78
79
80
Product Type, Char 1 36
Product Type, Char 2 34
Product Type, Char 3 54
Product Type, Char 4 36
Product Type, Char 5 34
Product Type, Char 6 30
Product Type, Char 7 32
Product Type, Char 8 30
36
34
54
36
34
30
32
30
36
34
54
33
32
30
30
30
36
34
54
33
32
30
30
30
Data Sheet
35
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 20
SPD Codes for HYS 64T[32000/64020] PC2-3200S
Product Type
Organization
512 MB
512 MB
256 MB
×64
256 MB
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–3200S–333 PC2–3200S–333 PC2–3200S–333 PC2–3200S–333
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
48
Rev. 1.1
HEX
47
Rev. 1.1
HEX
48
81
82
Product Type, Char 9 47
Product Type, Char
10
44
4C
35
41
20
20
20
20
20
1x
xx
44
44
44
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Product Type, Char
11
4C
35
41
20
20
20
20
20
1x
xx
xx
xx
xx
xx
4C
35
41
20
20
20
20
20
1x
xx
xx
xx
xx
xx
4C
35
41
20
20
20
20
20
1x
xx
xx
xx
xx
xx
Product Type, Char
12
Product Type, Char
13
Product Type, Char
14
Product Type, Char
15
Product Type, Char
16
Product Type, Char
17
Product Type, Char
18
Module Revision
Code
Test Program
Revision Code
ModuleManufacturing xx
Date Year
ModuleManufacturing xx
Date Week
ModuleManufacturing xx
Date Week
ModuleSerialNumber xx
(1)
Data Sheet
36
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 20
SPD Codes for HYS 64T[32000/64020] PC2-3200S
Product Type
Organization
512 MB
512 MB
256 MB
×64
256 MB
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–3200S–333 PC2–3200S–333 PC2–3200S–333 PC2–3200S–333
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
97
98
99
ModuleSerialNumber xx
(2)
xx
xx
xx
ModuleSerialNumber xx
(3)
xx
xx
00
FF
xx
xx
00
FF
xx
xx
00
FF
ModuleSerialNumber xx
(4)
100 -
127
Not used
00
128-
255
BLANK
FF
Data Sheet
37
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 21
SPD Codes for HYS64T128021[G/H]DL
Product Type
Organization
1 GByte
×64
1 GByte
×64
1 GByte
×64
1 GByte
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444
PC2–3200S–444 PC2–3200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
0
Programmed SPD
Bytes in EEPROM
80
80
80
80
1
Total number of Bytes 08
in EEPROM
08
08
08
2
3
Memory Type (DDR2) 08
08
0E
08
0E
08
0E
Number of Row
Addresses
0E
0A
61
4
5
Number of Column
Addresses
0A
61
0A
61
0A
61
DIMM Rank and
Stacking Information
6
7
8
Data Width
Not used
40
00
05
40
00
05
40
00
05
40
00
05
Interface Voltage
Level
9
t
CK @ CLmax (Byte 18) 3D
[ns]
AC SDRAM @ CLmax 50
3D
50
00
50
60
00
50
60
00
10
11
t
(Byte 18) [ns]
Error Correction
Support (non-ECC,
ECC)
00
12
13
14
15
Refresh Rate and
Type
82
08
00
00
82
08
00
00
82
08
00
00
82
08
00
00
Primary SDRAM
Width
Error Checking
SDRAM Width
Not used
Data Sheet
38
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 21
SPD Codes for HYS64T128021[G/H]DL
Product Type
Organization
1 GByte
×64
1 GByte
×64
1 GByte
×64
1 GByte
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444
PC2–3200S–444 PC2–3200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
16
17
18
Burst Length
Supported
0C
0C
0C
0C
Number of Banks on 04
SDRAM Device
04
38
04
38
04
38
Supported CAS
Latencies
38
19
20
Not used
00
04
00
04
00
04
00
04
DIMM Type
Information
21
22
23
DIMM Attributes
00
00
01
3D
00
01
50
00
01
50
Component Attributes 01
CK @ CLmax -1 (Byte 3D
18) [ns]
AC SDRAM @ CLmax - 50
1 [ns]
CK @ CLmax -2 (Byte 50
18) [ns]
AC SDRAM @ CLmax - 60
2 [ns]
t
24
25
26
t
50
50
60
60
50
60
60
50
60
t
t
27
28
29
30
31
t
t
t
t
RP.min [ns]
RRD.min [ns]
RCD.min [ns]
RAS.min [ns]
3C
1E
3C
2D
80
3C
1E
3C
2D
80
3C
1E
3C
2D
80
3C
1E
3C
2D
80
Module Density per
Rank
32
33
34
35
t
t
t
t
AS.min and tCS.min [ns] 25
AH.min and tCH.min [ns] 37
25
37
10
22
35
47
15
27
35
47
15
27
DS.min [ns]
DH.min [ns]
10
22
Data Sheet
39
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 21
SPD Codes for HYS64T128021[G/H]DL
Product Type
Organization
1 GByte
×64
1 GByte
×64
1 GByte
×64
1 GByte
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444
PC2–3200S–444 PC2–3200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
3C
Rev. 1.1
HEX
3C
Rev. 1.1
HEX
3C
Rev. 1.1
HEX
3C
36
37
38
39
t
t
t
WR.min [ns]
WTR.min [ns]
RTP.min [ns]
1E
1E
28
28
1E
1E
1E
1E
Analysis
00
00
00
00
Characteristics
40
41
42
43
44
45
46
47
t
t
t
t
t
t
RC and tRFC Extension 00
00
3C
69
80
1E
28
00
51
00
3C
69
80
23
2D
00
51
00
3C
69
80
23
2D
00
51
RC.min [ns]
3C
69
80
1E
28
00
51
RFC.min [ns]
CK.max [ns]
DQSQ.max [ns]
QHS.max [ns]
PLL Relock Time
T
CASE.max Delta /
∆T4R4W Delta
Psi(T-A) DRAM
∆T0 (DT0)
48
49
50
78
78
3E
2E
78
32
24
78
32
24
3E
∆T2N (DT2N, UDIMM) 2E
or ∆T2Q ( (DT2Q,
RDIMM)
51
52
53
54
55
∆T2P (DT2P)
1E
1E
24
1E
1E
24
17
34
1E
1B
1E
17
28
1E
1B
1E
17
28
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow) 17
∆T4R (DT4R) / ∆T4R4W 34
S Sign (DT4R4W)
56
57
58
59
∆T5B (DT5B)
∆T7 (DT7)
1E
20
00
00
1E
20
00
00
1B
1E
00
00
1B
1E
00
00
Psi(ca) PLL
Psi(ca) REG
Data Sheet
40
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 21
SPD Codes for HYS64T128021[G/H]DL
Product Type
Organization
1 GByte
×64
1 GByte
×64
1 GByte
×64
1 GByte
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444
PC2–3200S–444 PC2–3200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
Rev. 1.1
HEX
00
60
61
∆TPLL (DTPLL)
∆TREG (DTREG) /
00
00
00
00
Toggle Rate
62
63
SPD Revision
11
11
11
26
11
26
Checksum of Bytes 0- D2
62
D2
64
65
66
67
68
69
70
71
72
JEDEC ID Code of
Infineon (1)
C1
00
00
00
00
00
00
00
C1
00
00
00
00
00
00
00
xx
C1
00
00
00
00
00
00
00
xx
C1
00
00
00
00
00
00
00
xx
JEDEC ID Code of
Infineon (2)
JEDEC ID Code of
Infineon (3)
JEDEC ID Code of
Infineon (4)
JEDEC ID Code of
Infineon (5)
JEDEC ID Code of
Infineon (6)
JEDEC ID Code of
Infineon (7)
JEDEC ID Code of
Infineon (8)
Module Manufacturer xx
Location
73
74
75
76
77
78
Product Type, Char 1 36
Product Type, Char 2 34
Product Type, Char 3 54
Product Type, Char 4 31
Product Type, Char 5 32
Product Type, Char 6 38
36
34
54
31
32
38
36
34
54
31
32
38
36
34
54
31
32
38
Data Sheet
41
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 21
SPD Codes for HYS64T128021[G/H]DL
Product Type
Organization
1 GByte
×64
1 GByte
×64
1 GByte
×64
1 GByte
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444
PC2–3200S–444 PC2–3200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
30
Rev. 1.1
HEX
30
Rev. 1.1
HEX
30
79
80
81
82
83
84
85
86
87
88
89
90
91
Product Type, Char 7 30
Product Type, Char 8 32
32
32
32
Product Type, Char 9 31
Product Type, Char 10 48
Product Type, Char 11 44
Product Type, Char 12 4C
Product Type, Char 13 33
Product Type, Char 14 2E
Product Type, Char 15 37
Product Type, Char 16 41
Product Type, Char 17 20
Product Type, Char 18 20
31
31
31
47
48
47
44
44
44
4C
33
4C
35
4C
35
2E
41
41
37
20
20
41
20
20
20
20
20
20
20
20
Module Revision
Code
0x
0x
0x
0x
92
93
94
95
96
97
98
Test Program
Revision Code
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
ModuleManufacturing xx
Date Year
ModuleManufacturing xx
Date Week
ModuleManufacturing xx
Date Week
Module Serial Number xx
(1)
Module Serial Number xx
(2)
Module Serial Number xx
(3)
Data Sheet
42
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 21
SPD Codes for HYS64T128021[G/H]DL
Product Type
Organization
1 GByte
×64
1 GByte
×64
1 GByte
×64
1 GByte
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444
PC2–3200S–444 PC2–3200S–444
JEDEC SPD Revision
Byte# Description
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
99
Module Serial Number xx
xx
xx
xx
(4)
100 -
127
Not used
00
FF
00
00
00
128-
255
BLANK
FF
FF
FF
Data Sheet
43
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Package Outlines
7
Package Outlines
67.6
3.8 MAX.
±0.1
63.6
1
100
(2.15)
±0.1
(2.45)
±0.1
1
17.55
0.15
±0.1
2.7
(1.5)
±0.1
11.4
±0.1
47.4
(1.8)
(2.45)
±0.1
(2.15)
200
2.4
±0.1
1
101
2 MIN.
Detail of contacts
±0.03
0.45
±0.1
0.6
Burnished, no burr allowed
GLD09648
Figure 5
Package Outline L-DIM-200-30
Data Sheet
44
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Package Outlines
67.6
3.8 MAX.
±0.1
63.6
1
100
(2.15)
±0.1
(2.45)
±0.1
1
17.55
0.15
±0.1
2.7
(1.5)
±0.1
11.4
±0.1
47.4
(1.8)
(2.45)
±0.1
(2.15)
200
2.4
±0.1
1
101
2 MIN.
Detail of contacts
±0.03
0.45
±0.1
0.6
Burnished, no burr allowed
GLD09649
Figure 6
Package Outline L-DIM-200-31
Data Sheet
45
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Package Outlines
67.6 ±
0.15
3.8 max.
63.6
0.
1
39
11.4
1
41
199
±
1
2.15
2.45
2.15
47.4
4.2
2.7
1.0
40 42
2.45
2
200
1.8
4
Detail of Contacts
Detail of Chamfer
0.2
0.15
-
0.45
0.6
Figure 7
Package Outline L-DIM-200-33
Data Sheet
46
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
8
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon’s nomenclature uses simple coding combined with some propriatory coding. Table 22 provides examples
for module and component product type number as well as the field number. The detailed field description together
with possible values and coding explanation is listed for modules in Table 23 and for components in Table 24.
Table 22
Nomenclature Fields and Examples
Field Number
Example for
1
2
3
T
T
4
5
6
7
0
0
8
9
10
–5
–5
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
64
512
0
2
K
A
M
C
–A
16
1) Multiplying “Memory Density per I/O” with “Module Data
Width” and dividing by 8 for Non-ECC and 9 for ECC
modules gives the overall module memory density in
MBytes as listed in column “Coding”.
Table 23
DDR2 DIMM Nomenclature
Values Coding
Field Description
1
INFINEON
HYS
Constant
Modul Prefix
2
Module Data
Width [bit]
64
72
T
Non-ECC
ECC
Table 24
DDR2 DRAM Nomenclature
Values Coding
Field Description
3
4
DRAM
Technology
DDR2
1
INFINEON
HYB
Constant
Component Prefix
Memory Density
per I/O [Mbit];
32
256 MByte
512 MByte
1 GByte
2
3
4
Interface Voltage [V] 18
DRAM Technology
SSTL1.8
DDR2
256 Mbit
512 Mbit
1 Gbit
2 Gbit
×4
64
T
Module Density1)
128
256
0 .. 9
Component Density 256
2 GByte
[Mbit]
512
5
6
Raw Card
Generation
look up table
1G
2G
Number of Module 0, 2, 4 1, 2, 4
Ranks
5+6 Number of I/Os
40
80
16
×8
7
8
Product Variations 0 .. 9
look up table
×16
Package,
A .. Z
look up table
7
8
Product Variations 0 .. 9
look up table
First
Lead-Free Status
Die Revision
A
B
C
9
Module Type
S
SO-DIMM
Second
M
Micro-DIMM
Registered
Unbuffered
PC2–4200 4–4–4
PC2–3200 3–3–3
First
9
Package,
FBGA,
lead-containing
R
Lead-Free Status
U
F
FBGA, lead-free
DDR2-533
10
11
Speed Grade
Die Revision
–3.7
–5
–A
–B
10
11
Speed Grade
–3.7
–5
DDR2-400
N/A for Components
Second
Data Sheet
47
Rev. 0.91, 2004-06
09122003-FTXN-KM26
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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