CY2309CZXC-1HT [INFINEON]
3.3V Zero Delay Buffer;
| 型号： | CY2309CZXC-1HT |
| 厂家： | 
Infineon |
| 描述： | 3.3V Zero Delay Buffer 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总22页 (文件大小：581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2305C
CY2309C
3.3 V Zero Delay Clock Buffer
3.3
V Zero Delay Clock Buffer
100 MHz–133 MHz frequencies and have higher drive than the
-1 devices. All parts have on-chip phase locked loops (PLLs)
which lock to an input clock on the REF pin. The PLL feedback
is on-chip and is obtained from the CLKOUT pad.
Features
■ 10 MHz to 100–133 MHz operating range
■ Zero input and output propagation delay
■ Multiple low skew outputs
The CY2309C has two banks of four outputs each that are
controlled by the select inputs as shown in the Select Input
Decoding on page 6. If all output clocks are not required, Bank
B is three-stated. The input clock is directly applied to the outputs
by the select inputs for chip and system testing purposes.
■ One input drives five outputs (CY2305C)
■ One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C)
■ 50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
The CY2305C and CY2309C PLLs enter a power down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off. This
results in less than 12.0 A of current draw for commercial
temperature devices and 25.0 Afor industrial and automotive-A
temperature parts. The CY2309C PLL shuts down in one
additional case as shown in the Select Input Decoding on page 6.
■ Test mode to bypass phase locked loop (PLL) (CY2309C) only,
see Select Input Decoding on page 6
■ Available in space saving 16-pin 150 Mil small outline
integrated circuit (SOIC) or 4.4 mm thin shrunk small outline
package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil
SOIC package (CY2305C)
In the special case when S2:S1 is 1:0, the PLL is bypassed and
REF is output from DC to the maximum allowable frequency. The
part behaves as a non-zero delay buffer in this mode and the
outputs are not three-stated.
■ 3.3 V operation
■ Commercial, industrial and automotive-A flows available
Functional Description
The CY2305C or CY2309C is available in two or three different
configurations as shown in the Ordering Information on page 15.
The CY2305C-1 or CY2309C-1 is the base part. The CY2305-1H
or CY2309-1H is the high drive version of the -1. Its rise and fall
times are much faster than the -1.
The CY2305C and CY2309C are die replacement parts for
CY2305 and CY2309.
The CY2309C is a low-cost 3.3 V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC or
TSSOP package. The CY2305C is an 8-pin version of the
CY2309C. It accepts one reference input and drives out five low
skew clocks. The -1H versions of each device operate up to
For a complete list of related documentation, click here.
Logic Block Diagram – CY2305C
PLL
CLKOUT
CLK1
REF
CLK2
CLK3
CLK4
Cypress Semiconductor Corporation
Document Number: 38-07672 Rev. *Q
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 27, 2017
CY2305C
CY2309C
Logic Block Diagram – CY2309C
CLKOUT
CLKA1
PLL
MUX
REF
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
S2
S1
Select Input
Decoding
Document Number: 38-07672 Rev. *Q
Page 2 of 22
CY2305C
CY2309C
Contents
Pinouts ..............................................................................4
Pin Definitions ..................................................................5
Pin Definitions ..................................................................5
Functional Overview ........................................................6
Select Input Decoding .................................................6
Zero Delay and Skew Control .....................................6
Absolute Maximum Conditions .......................................7
Operating Conditions .......................................................7
Operating Conditions .......................................................7
Electrical Characteristics .................................................8
Electrical Characteristics .................................................8
Test Circuits ......................................................................9
Thermal Resistance ..........................................................9
Switching Characteristics ..............................................10
Switching Characteristics ..............................................11
Switching Characteristics ..............................................12
Switching characteristics ..............................................13
Switching Waveforms ....................................................14
Ordering Information ......................................................15
Ordering Code Definitions .........................................16
Package Diagrams ..........................................................17
Acronyms ........................................................................19
Document Conventions .................................................19
Units of Measure .......................................................19
Document History Page .................................................20
Sales, Solutions, and Legal Information ......................22
Worldwide Sales and Design Support .......................22
Products ....................................................................22
PSoC®Solutions .......................................................22
Cypress Developer Community .................................22
Technical Support .....................................................22
Document Number: 38-07672 Rev. *Q
Page 3 of 22
CY2305C
CY2309C
Pinouts
Figure 1. 8-pin SOIC pinout (Top View)
CY2305C
CLKOUT
REF
8
1
CLK4
VDD
CLK2
CLK1
GND
7
6
5
2
3
4
CY2305C
CLK3
Figure 2. 16-pin SOIC / TSSOP pinout (Top View)
CY2309C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
CLKOUT
CLKA1
CLKA4
CLKA3
VDD
CY2309C
CLKA2
VDD
GND
GND
CLKB4
CLKB3
S1
CLKB1
CLKB2
S2
Document Number: 38-07672 Rev. *Q
Page 4 of 22
CY2305C
CY2309C
Pin Definitions
8-pin SOIC
Pin
1
Signal
Description
REF [1]
CLK2 [2]
CLK1 [2]
GND
Input reference frequency
Buffered clock output
Buffered clock output
Ground
2
3
4
5
CLK3 [2]
Buffered clock output
3.3 V supply
6
VDD
7
CLK4 [2]
Buffered clock output
8
CLKOUT [2] Buffered clock output, internal feedback on this pin
Pin Definitions
16-pin SOIC / TSSOP
Pin
1
Signal
REF [1]
CLKA1 [2]
CLKA2 [2]
VDD
Description
Input reference frequency
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3 V supply
2
3
4
5
GND
Ground
6
CLKB1 [2]
CLKB2 [2]
S2 [3]
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
7
8
9
S1 [3]
Select input, bit 1
10
11
12
13
14
15
16
CLKB3 [2]
CLKB4 [2]
GND
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
VDD
3.3 V supply
CLKA3 [2]
CLKA4 [2]
Buffered clock output, Bank A
Buffered clock output, Bank A
CLKOUT [2] Buffered output, internal feedback on this pin
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
Document Number: 38-07672 Rev. *Q
Page 5 of 22
CY2305C
CY2309C
Functional Overview
Select Input Decoding
For CY2309C
S2
0
S1
0
CLOCK A1–A4
Three state
Driven
CLOCK B1–B4
Three state
Three state
Driven
CLKOUT [4]
Driven
Output Source
PLL
PLL Shutdown
N
N
Y
N
0
1
Driven
PLL
1
0
Driven
Driven
Reference
PLL
1
1
Driven
Driven
Driven
Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB pins
For zero output to output skew, all outputs must be loaded
equally.
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input or output delay.
Even if CLKOUT is not used, it must have a capacitive load,
equal to that on other outputs, for obtaining zero input-output
delay. If input to output delay adjustments are required, use
Figure 3 to calculate loading differences between the CLKOUT
pin and other outputs.
For applications requiring zero input or output delay, all outputs
including CLKOUT are equally loaded. Even if CLKOUT is not
used, it must have a capacitive load equal to that on other
outputs for obtaining zero input or output delay.
Note
4. This output is driven and has an internal feedback for the PLL. The load on this output is adjusted to change the skew between the reference and output.
Document Number: 38-07672 Rev. *Q
Page 6 of 22
CY2305C
CY2309C
Storage temperature ................................ –65 °C to +150 °C
Junction temperature ................................................. 150 °C
Absolute Maximum Conditions
Supply voltage to ground potential ..............–0.5 V to +4.6 V
DC input voltage (Except REF) ..........–0.5 V to VDD + 0.5 V
DC input voltage REF .........................–0.5 V to VDD + 0.5 V
Static discharge voltage
(per MIL-STD-883, Method 3015) .........................> 2,000 V
Operating Conditions
Operating Conditions Table for CY2305CSXC-XX and CY2309CSXC-XX Commercial Temperature devices.
Parameter
VDD
Description
Min
3.0
0
Max
3.6
70
30
10
7
Unit
V
Supply voltage
TA
Operating temperature (ambient temperature)
Load capacitance, below 100 MHz
Load capacitance, from 100 MHz to 133 MHz
Input capacitance
°C
pF
pF
pF
ms
CL
CL
CIN
tPU
–
–
–
Power-up time for all VDDs to reach minimum specified voltage (power ramps are
monotonic)
0.05
50
Operating Conditions
Operating Conditions Table for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX Industrial / Automotive-A Temperature
devices.
Parameter
VDD
Description
Min
3.0
–40
–
Max
3.6
85
30
10
7
Unit
V
Supply voltage
TA
Operating temperature (ambient temperature)
Load capacitance, below 100 MHz
Load capacitance, from 100 MHz to 133 MHz
Input capacitance
°C
pF
pF
pF
ms
CL
CL
CIN
tPU
–
–
Power-up time for all VDDs to reach minimum specified voltage (power ramps are
monotonic)
0.05
50
Document Number: 38-07672 Rev. *Q
Page 7 of 22
CY2305C
CY2309C
Electrical Characteristics
Electrical Characteristics Table for CY2305CSXC-XX and CY2309CSXC-XX Commercial Temperature devices.
Parameter
VIL
Description
Input LOW voltage [5]
Input HIGH voltage [5]
Input LOW current
Test Conditions
Min
–
Max
0.8
–
Unit
V
VIH
IIL
2.0
–
V
VIN = 0 V
50
A
A
V
IIH
Input HIGH current
Output LOW voltage [6]
VIN = VDD
–
100
0.4
VOL
IOL = 8 mA (–1)
–
IOL = 12 mA (–1H)
IOH = –8 mA (–1)
IOH = –12 mA (–1H)
REF = 0 MHz
VOH
Output HIGH voltage [6]
2.4
–
V
IDD (PD mode) Power-down supply current
IDD Supply current
–
–
12
32
A
Unloaded outputs at 66.67 MHz, SEL inputs at
VDD
mA
Electrical Characteristics
Electrical Characteristics Table for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX Industrial / Automotive-A Temperature
devices.
Parameter
VIL
Description
Input LOW voltage [5]
Input HIGH voltage [5]
Input LOW current
Test Conditions
Min
–
Max
0.8
–
Unit
V
VIH
IIL
2.0
–
V
VIN = 0 V
50
A
A
V
IIH
Input HIGH current
Output LOW voltage [6]
VIN = VDD
–
100
0.4
VOL
IOL = 8 mA (–1)
–
IOL = 12 mA (–1H)
IOH = –8 mA (–1)
IOH = –12 mA (–1H)
REF = 0 MHz
VOH
Output HIGH voltage [6]
2.4
–
V
IDD (PD mode) Power-down supply current
–
–
25
35
A
IDD
Supply current
Unloaded outputs at 66.67 MHz, SEL inputs at
VDD
mA
Notes
5. REF input has a threshold voltage of V /2.
DD
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *Q
Page 8 of 22
CY2305C
CY2309C
Test Circuits
Figure 4. Test Circuits
Test Circuit # 2
Test Circuit # 1
V
DD
V
1 k
1 k
DD
0.1 F
CLK out
0.1 F
OUTPUTS
GND
OUTPUTS
10 pF
C
LOAD
V
DD
V
DD
0.1 F
GND
0.1 F
GND
GND
For parameter t8 (output slew rate) on -1H devices
Thermal Resistance
Parameter [7]
Description
Test Conditions
8-pin SOIC
16-pin SOIC 16-pin TSSOP Unit
θJA
Thermal resistance
(junction to ambient)
Test conditions follow
standard test methods
and procedures for
measuring thermal
impedance, in
145
121
111
°C/W
θJC
Thermal resistance
(junction to case)
62
53
26
°C/W
accordance with
EIA/JESD51.
Note
7. These parameters are guaranteed by design and are not tested.
Document Number: 38-07672 Rev. *Q
Page 9 of 22
CY2305C
CY2309C
Switching Characteristics
Switching Characteristics Table for CY2305CSXC-1 and CY2309CSXC-1 Commercial Temperature devices. All parameters are
specified with loaded outputs.
Parameter
Description
Output frequency
Test Conditions
30 pF load
Min
10
10
40
45
–
Typ
–
Max
100
Unit
MHz
MHz
%
t1
10 pF load
–
133.33
60
tDC
Output duty cycle [8] = t2 t1
Measured at 1.4 V, Fout > 50 MHz
Measured at 1.4 V, Fout 50 MHz
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
Measured at VDD/2
50
50
–
55
%
t3
Rise time [8]
Fall time [8]
Output-to-output skew [8]
2.25
2.25
200
ns
t4
–
–
ns
t5
–
–
ps
t6A
Delay, REF rising edge to
CLKOUT rising edge [8]
–
0
±350
ps
t6B
Delay, REF rising edge to
CLKOUT rising edge [8]
Measured at VDD/2. Measured in
PLL Bypass mode, CY2309C
device only.
1
5
8.7
ns
t7
Device-to-device skew [8]
Cycle-to-cycle jitter, peak [8]
PLL lock time [8]
Measured at VDD/2 on the CLKOUT
pins of devices
–
–
–
0
50
–
700
175
1.0
ps
ps
tJ
Measured at 66.67 MHz, loaded
outputs
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Note
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *Q
Page 10 of 22
CY2305C
CY2309C
Switching Characteristics
Switching Characteristics Table for CY2305CSXC-1H and CY2309CSXC-1H Commercial Temperature devices. All parameters are
specified with loaded outputs.
Parameter
Description
Output frequency
Description
Min
10
10
40
45
–
Typ
–
Max
100
133.33
60
Unit
MHz
MHz
%
t1
30 pF load
10 pF load
–
tDC
Output duty cycle [9] = t2 t1
Measured at 1.4 V, Fout > 50 MHz
Measured at 1.4 V, Fout 50 MHz
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
50
50
–
55
%
t3
Rise time [9]
Fall time [9]
Output-to-output skew [9]
1.5
ns
t4
–
–
1.5
ns
t5
–
–
200
±350
ps
t6A
Delay, REF rising edge to
CLKOUT rising edge [9]
Measured at VDD/2
–
0
ps
t6B
Delay, REF rising edge to
CLKOUT rising edge [9]
Measured at VDD/2. Measured in
PLL Bypass mode, CY2309C
device only.
1
5
8.7
ns
t7
Device-to-device skew [9]
Output slew rate [9]
Measured at VDD/2 on the CLKOUT
pins of devices
–
1
–
–
0
–
–
–
700
–
ps
V/ns
ps
t8
Measured between 0.8 V and 2.0 V
using Test circuit #2
tJ
Cycle-to-cycle jitter, peak [9]
PLL lock time [9]
Measured at 66.67 MHz, loaded
outputs
175
1.0
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Note
9. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *Q
Page 11 of 22
CY2305C
CY2309C
Switching Characteristics
Switching Characteristics Table for CY2305CSXI-1, CY2305CSXA-1, and CY2309CSXI-1 Industrial Temperature devices. All
parameters are specified with loaded outputs.
Parameter
Description
Output frequency
Test Conditions
30 pF load
Min
10
10
40
45
–
Typ
–
Max
100
Unit
MHz
MHz
%
t1
10 pF load
–
133.33
60
tDC
Output duty cycle [10] = t2 t1
Measured at 1.4 V, Fout > 50 MHz
Measured at 1.4 V, Fout < 50 MHz
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
Measured at VDD/2
50
50
–
55
%
t3
Rise time [10]
Fall time [10]
Output-to-output skew [10]
2.25
2.25
200
ns
t4
–
–
ns
t5
–
–
ps
t6A
Delay, REF rising edge to
CLKOUT rising edge [10]
–
0
±350
ps
t6B
Delay, REF rising edge to
CLKOUT rising edge [10]
Measured at VDD/2. Measured in
PLL Bypass mode, CY2309C
device only.
1
5
8.7
ns
t7
Device-to-device skew [10]
Cycle-to-cycle jitter, peak [10]
PLL lock time [10]
Measured at VDD/2 on the CLKOUT
pins of devices
–
–
–
0
50
–
700
175
1.0
ps
ps
tJ
Measured at 66.67 MHz, loaded
outputs
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Note
10. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *Q
Page 12 of 22
CY2305C
CY2309C
Switching characteristics
Switching Characteristics Table for CY2305CSXI-1H, CY2305CSXA-1H and CY2309CSXI-1H Industrial / Automotive-A Temperature
devices. All parameters are specified with loaded outputs.
Parameter
Description
Output frequency
Description
Min
10
10
40
45
–
Typ
–
Max
100
133.33
60
Unit
MHz
MHz
%
t1
30 pF load
10 pF load
–
tDC
Output duty cycle [11] = t2 t1
Measured at 1.4 V, Fout > 50 MHz
Measured at 1.4 V, Fout < 50 MHz
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
50
50
–
55
%
t3
Rise time [11]
Fall time [11]
Output-to-output skew [11]
1.5
ns
t4
–
–
1.5
ns
t5
–
–
200
±350
ps
t6A
Delay, REF rising edge to
CLKOUT rising edge [11]
Measured at VDD/2
–
0
ps
t6B
Delay, REF rising edge to
CLKOUT rising edge [11]
Measured at VDD/2. Measured in
PLL Bypass mode, CY2309C
device only.
1
5
8.7
ns
t7
Device-to-device skew [11]
Output slew rate [11]
Measured at VDD/2 on the CLKOUT
pins of devices
–
1
–
–
0
–
–
–
700
–
ps
V/ns
ps
t8
Measured between 0.8 V and 2.0 V
using Test circuit #2
tJ
Cycle-to-cycle jitter, peak [11]
PLL lock time [11]
Measured at 66.67 MHz, loaded
outputs
175
1.0
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Note
11. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *Q
Page 13 of 22
CY2305C
CY2309C
Switching Waveforms
Figure 5. Duty Cycle Timing
t
1
t
2
1.4 V
1.4 V
1.4 V
Figure 6. All Outputs Rise/Fall Time
3.3 V
0 V
2.0 V
0.8 V
2.0 V
0.8 V
OUTPUT
t
3
t
4
Figure 7. Output-Output Skew
1.4 V
OUTPUT
OUTPUT
1.4 V
t
5
Figure 8. Input-Output Propagation Delay
VDD/2
INPUT
VDD/2
OUTPUT
t
6
Figure 9. Device-Device Skew
VDD/2
CLKOUT, Device 1
CLKOUT, Device 2
VDD/2
t7
Document Number: 38-07672 Rev. *Q
Page 14 of 22
CY2305C
CY2309C
Ordering Information
Ordering Code
Pb-free - CY2305C
CY2305CSXC-1
CY2305CSXC-1T
CY2305CSXC-1H
CY2305CSXC-1HT
CY2305CSXI-1
Package Type
Operating Range
8-pin SOIC (150 Mil)
Commercial
8-pin SOIC (150 Mil) – Tape and Reel
8-pin SOIC (150 Mil)
Commercial
Commercial
Commercial
Industrial
8-pin SOIC (150 Mil) – Tape and Reel
8-pin SOIC (150 Mil)
CY2305CSXI-1T
CY2305CSXI-1H
CY2305CSXI-1HT
CY2305CSXA-1H
CY2305CSXA-1HT
Pb-free - CY2309C
CY2309CSXC-1
CY2309CSXC-1T
CY2309CSXC-1H
CY2309CSXC-1HT
CY2309CSXI-1
8-pin SOIC (150 Mil) – Tape and Reel
8-pin SOIC (150 Mil)
Industrial
Industrial
8-pin SOIC (150 Mil) – Tape and Reel
8-pin SOIC (150 Mil)
Industrial
Automotive-A
Automotive-A
8-pin SOIC (150 Mil) – Tape and Reel
16-pin SOIC (150 Mil)
Commercial
Commercial
Commercial
Commercial
Industrial
16-pin SOIC (150 Mil) – Tape and Reel
16-pin SOIC (150 Mil)
16-pin SOIC (150 Mil) – Tape and Reel
16-pin SOIC (150 Mil)
CY2309CSXI-1T
CY2309CSXI-1H
CY2309CSXI-1HT
CY2309CZXC-1
CY2309CZXC-1T
CY2309CZXC-1H
CY2309CZXC-1HT
CY2309CZXI-1
16-pin SOIC (150 Mil) – Tape and Reel
16-pin SOIC (150 Mil)
Industrial
Industrial
16-pin SOIC (150 Mil) – Tape and Reel
16-pin TSSOP (4.4 mm)
Industrial
Commercial
Commercial
Commercial
Commercial
Industrial
16-pin TSSOP (4.4 mm) – Tape and Reel
16-pin TSSOP (4.4 mm)
16-pin TSSOP (4.4 mm) – Tape and Reel
16-pin TSSOP (4.4 mm)
CY2309CZXI-1T
CY2309CZXI-1H
CY2309CZXI-1HT
16-pin TSSOP (4.4 mm) – Tape and Reel
16-pin TSSOP (4.4 mm)
Industrial
Industrial
16-pin TSSOP (4.4 mm) – Tape and Reel
Industrial
Document Number: 38-07672 Rev. *Q
Page 15 of 22
CY2305C
CY2309C
Ordering Code Definitions
CY 230XC
X
X
–
X
X
1X
X = blank or T
blank = Tube; T = Tape and Reel
Output Drive: 1X = 1 or 1H
1 = Standard Drive; 1H = High Drive
Temperature Grade: X = C or I or A
C = Commercial; I = Industrial; A = Automotive
Pb-free
Package Type: X = S or Z
S = 8-pin SOIC or 16-pin SOIC; Z = 16-pin TSSOP
Base Device Part Number: 230XC = 2305C or 2309C
2305C = 5-output zero delay buffer, rev C
2309C = 9-output zero delay buffer, rev C
Company ID: CY = Cypress
Document Number: 38-07672 Rev. *Q
Page 16 of 22
CY2305C
CY2309C
Package Diagrams
Figure 10. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *H
Document Number: 38-07672 Rev. *Q
Page 17 of 22
CY2305C
CY2309C
Package Diagrams (continued)
Figure 11. 16-pin SOIC (150 Mil) S16.15/SZ16.15 Package Outline, 51-85068
51-85068 *E
Figure 12. 16-pin TSSOP (4.40 mm Body) Z16.173/ZZ16.173 Package Outline, 51-85091
51-85091 *E
Document Number: 38-07672 Rev. *Q
Page 18 of 22
CY2305C
CY2309C
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CMOS
PLL
Complementary Metal Oxide Semiconductor
Phase Locked Loop
Symbol
°C
Unit of Measure
degree Celsius
kilohertz
SOIC
TSSOP
Small Outline Integrated Circuit
Thin Shrunk Small Outline Package
kHz
MHz
µA
mA
ms
ns
megahertz
microampere
milliampere
millisecond
nanosecond
picofarad
pF
ps
picosecond
volt
V
Document Number: 38-07672 Rev. *Q
Page 19 of 22
CY2305C
CY2309C
Document History Page
Document Title: CY2305C/CY2309C, 3.3 V Zero Delay Clock Buffer
Document Number: 38-07672
Orig. of
Change
Rev.
ECN No.
Issue Date
Description of Change
**
224421
268571
276453
See ECN
See ECN
See ECN
RGL
New data sheet
Added bullet for 5 V tolerant inputs in the features
*A
*B
RGL
RGL
Minor Change: Moved one sentence from the features to the Functional
Description
*C
*D
*E
303063
318315
344815
See ECN
See ECN
See ECN
RGL
RGL
RGL
Updated data sheet as per characterization data
Data sheet rewrite
Minor Error: Corrected the header of all the AC/DC tables with the right part
numbers.
*F
1279889
See ECN
KVM
Changed title from “CY2305C/CY2309C‚ Low Cost 3.3 V Zero Delay Buffer”
to “CY2305C/CY2309C, 3.3 V Zero Delay Clock Buffer”.
Specified the VIL minimum value to -0.3 V
Specified the VIH maximum value to VDD + 0.3 V
Changed DC Input Voltage (REF) maximum value in Absolute Maximum
section
Removed references to 5 V tolerant inputs (pages 1 and 2)
Removed Pentium compatibility reference
Added CY2305C block diagram
Added ‚peak to the jitter specifications
Changed typical jitter from 75 ps to 50 ps for standard drive devices
For standard drive devices, tightened rise/fall times from 2.5 ns to 2.25 ns
Tightened cycle-to-cycle jitter from 200 ps to 175 ps
Tightened output-to-output skew from 250 ps to 200 ps
*G
*H
1561504
2558537
See ECN
08/27/08
KVM / NSI / Changed status from Preliminary to Final.
AESA
Added CY2305C Automotive-A grade devices
Extended duty cycle specs to cover entire frequency range
KVM / AESA Updated Ordering Information:
Added CY2305CSXA-1 and CY2305CSXA-1T parts under Pb-free
CY2305C.
*I
2901743
3080990
03/30/2010
11/10/2010
VIVG
Added Ordering Code Definitions under Ordering Information.
Updated Package Diagrams.
*J
BASH
Updated Pinouts:
Updated Figure 1 (Modified pin diagram).
Added Acronyms and Units of Measure.
Updated to new template.
*K
*L
3160535
02/03/2011
BASH
PURU
Updated Electrical Characteristics:
Removed minimum value of VIL parameter and maximum value of VIH
parameter.
Updated Electrical Characteristics:
Removed minimum value of VIL parameter and maximum value of VIH
parameter.
Updated Ordering Information:
Removed Prune parts CY2305CSXA-1 and CY2305CSXA-1T.
3822852
11/27/2012
Updated Functional Overview:
Updated Select Input Decoding (Added Figure 3 only, no edits).
Updated Zero Delay and Skew Control (Minor edits).
Updated Package Diagrams:
spec 51-85091 – Changed revision from *C to *D.
spec 51-85068 – Changed revision from *C to *E.
spec 51-85066 – Changed revision from *D to *E.
Document Number: 38-07672 Rev. *Q
Page 20 of 22
CY2305C
CY2309C
Document History Page (continued)
Document Title: CY2305C/CY2309C, 3.3 V Zero Delay Clock Buffer
Document Number: 38-07672
Orig. of
Rev.
ECN No.
Issue Date
Description of Change
Updated Package Diagrams:
Change
*M
4201564
11/25/2013
CINM
spec 51-85066 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*N
*O
4578443
5242528
11/25/2014
TAVA
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams.
04/15/2016 SDHK / PSR Updated Electrical Characteristics:
Updated details in “Test Conditions” column corresponding to VOL and VOH
parameters.
Updated Electrical Characteristics:
Updated details in “Test Conditions” column corresponding to VOL and VOH
parameters.
Added Thermal Resistance.
Updated Package Diagrams:
spec 51-85066 – Changed revision from *F to *H.
Updated to new template.
*P
5553658
5708829
12/14/2016
04/27/2017
TAVA
Updated to new template.
Completing Sunset Review.
*Q
AESATMP7 Updated Cypress Logo and Copyright.
Document Number: 38-07672 Rev. *Q
Page 21 of 22
CY2305C
CY2309C
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP| PSoC 6
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IoT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Lighting & Power Control
Memory
Technical Support
cypress.com/powerpsoc
cypress.com/memory
cypress.com/psoc
cypress.com/support
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-07672 Rev. *Q
Revised April 27, 2017
Page 22 of 22
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