CY2309ESXC-1H [CYPRESS]
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16;
| 型号： | CY2309ESXC-1H |
| 厂家： | 
CYPRESS |
| 描述： | PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16 光电二极管 |
| 文件： | 总17页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2305
CY2309
Low-Cost 3.3V Zero Delay Buffer
Features
Functional Description
■ 10MHzto100-/133MHzoperatingrange,compatiblewithCPU
and PCI bus frequencies
The CY2309 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC or
TSSOP package. The CY2305 is an 8-pin version of the
CY2309. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at up
to 100-/133 MHz frequencies, and have higher drive than the -1
devices. All parts have on-chip PLLs which lock to an input clock
on the REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad.
■ Zero input-output propagation delay
■ 60 ps typical cycle-to-cycle jitter (high drive)
■ Multiple low-skew outputs
❐ 85 ps typical output-to-output skew
❐ One input drives five outputs (CY2305)
❐ One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)
The CY2309 has two banks of four outputs each, which can be
controlled by the Select inputs as shown in the “Select Input
Decoding” table on page 3. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the input
clock to be directly applied to the outputs for chip and system
testing purposes.
■ Compatible with Pentium-based systems
■ Test Mode to bypass phase-locked loop (PLL) (CY2309 only
[see “Select Input Decoding” on page 3])
■ Available in space-saving 16-pin 150-mil SOIC or 4.4-mm
TSSOPpackages(CY2309), and8-pin, 150-milSOICpackage
(CY2305)
The CY2305 and CY2309 PLLs enter a power down mode when
there are no rising edges on the REF input. In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 12.0 μA of current draw for commercial temperature
devices and 25.0 μA for industrial temperature parts. The
CY2309 PLL shuts down in one additional case as shown in the
table below.
■ 3.3V operation
■ Industrial temperature available
Multiple CY2305 and CY2309 devices can accept the same input
clock and distribute it. In this case, the skew between the outputs
of two devices is guaranteed to be less than 700 ps.
The CY2305/CY2309 is available in two/three different configu-
rations, as shown in the ordering information (page 12). The
CY2305-1/CY2309-1 is the base part. The CY2305-1H/
CY2309-1H is the high-drive version of the -1, and its rise and
fall times are much faster than the -1s.
Logic Block Diagram
CLKOUT
MUX
PLL
REF
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
S2
Select Input
Decoding
S1
Cypress Semiconductor Corporation
Document #: 38-07140 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 23, 2008
[+] Feedback
CY2305
CY2309
Pinouts
Figure 1. Pin Diagram - CY2305
1
8
CLKOUT
CLK4
V
DD
REF
CLK2
CLK1
GND
2
3
4
7
6
5
CLK3
Table 1. Pin Description for CY2305
Pin
Signal
Description
REF[1]
1
Input reference frequency, 5V-tolerant input
Buffered clock output
CLK2[2]
2
3
CLK1[2]
GND
Buffered clock output
4
5
Ground
CLK3[2]
VDD
CLK4[2]
Buffered clock output
6
7
3.3V supply
Buffered clock output
CLKOUT[2]
8
Buffered clock output, internal feedback on this pin
Figure 2. Pin Diagram - CY2309
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
CLKOUT
CLKA1
CLKA4
CLKA3
VDD
CLKA2
VDD
GND
GND
CLKB4
CLKB3
S1
CLKB1
CLKB2
S2
Table 2. Pin Description for CY2309
Pin
1
Signal
Description
REF[1]
CLKA1[2]
CLKA2[2]
VDD
Input reference frequency, 5V-tolerant input
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V supply
2
3
4
5
GND
Ground
CLKB1[2]
CLKB2[2]
S2[3]
6
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
7
8
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
Document #: 38-07140 Rev. *H
Page 2 of 17
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CY2305
CY2309
Table 2. Pin Description for CY2309
Pin
9
Signal
Description
S1[3]
Select input, bit 1
CLKB3[2]
CLKB4[2]
GND
10
11
12
13
14
15
16
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
VDD
3.3V supply
CLKA3[2]
CLKA4[2]
CLKOUT[2]
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
Select Input Decoding for CY2309
S2
0
S1
0
CLOCK A1–A4
Three-state
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
CLKOUT[4]
Driven
Output Source
PLL
PLL Shutdown
N
N
Y
N
0
1
Driven
PLL
1
0
Driven
Driven
Reference
PLL
1
1
Driven
Driven
Driven
Notes
3. Weak pull ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07140 Rev. *H
Page 3 of 17
[+] Feedback
CY2305
CY2309
REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB
Pins
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal
feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not
used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. If input to output delay
adjustments are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs.
For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note entitled “CY2305
and CY2309 as PCI and SDRAM Buffers.”
Document #: 38-07140 Rev. *H
Page 4 of 17
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CY2305
CY2309
Absolute Maximum Conditions
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage (Except REF) ............–0.5V to VDD + 0.5V
DC Input Voltage REF .........................................–0.5V to 7V
Storage Temperature ................................. –65°C to +150°C
Junction Temperature................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ...........................> 2,000V
Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter
VDD
Description
Min
3.0
0
Max
3.6
70
30
10
7
Unit
V
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
°C
pF
pF
pF
ms
CL
CL
CIN
tPU
–
–
–
Power up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.05
50
Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature
Devices
Parameter
VIL
Description
Input LOW Voltage[5]
Input HIGH Voltage[5]
Input LOW Current
Input HIGH Current
Output LOW Voltage[6]
Test Conditions
Min
–
Max
0.8
Unit
V
VIH
IIL
2.0
–
–
V
VIN = 0V
50.0
100.0
0.4
μA
μA
V
IIH
VIN = VDD
–
VOL
IOL = 8 mA (–1)
–
I
OH = 12 mA (–1H)
IOH = –8 mA (–1)
OL = –12 mA (–1H)
Output HIGH Voltage[6]
VOH
2.4
–
V
I
IDD (PD mode) Power Down Supply Current REF = 0 MHz
–
–
12.0
32.0
μA
IDD
Supply Current
Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
mA
Switching Characteristics for CY2305SC-1and CY2309SC-1 Commercial Temperature
Devices [7]
Parameter
Name
Test Conditions
Min
Typ.
Max
Unit
t1
Output Frequency
30-pF load
10 pF load
10
10
–
100
133.33
MHz
MHz
Duty Cycle[6] = t2 ÷ t1
Rise Time[6]
Measured at 1.4V, Fout = 66.67
MHz
40.0
50.0
–
60.0
2.50
2.50
%
ns
ns
t3
t4
t5
Measured between 0.8V and
2.0V
–
Fall Time[6]
Measured between 0.8V and
2.0V
–
–
Output to Output Skew[6]
All outputs equally loaded
Measured at VDD/2
–
–
85
0
250
ps
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
±350
Notes
5. REF input has a threshold voltage of V /2.
DD
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
7. All parameters specified with loaded outputs.
Document #: 38-07140 Rev. *H
Page 5 of 17
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CY2305
CY2309
SwitchingCharacteristicsforCY2305SC-1andCY2309SC-1CommercialTemperatureDevices
(continued)[7]
Parameter
t6B
Name
Test Conditions
Min
Typ.
Max
Unit
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2. Measured in
PLL Bypass Mode, CY2309
device only.
1
5
8.7
ns
Device to Device Skew[6]
Cycle to Cycle Jitter[6]
PLL Lock Time[6]
t7
Measured at VDD/2 on the
CLKOUT pins of devices
–
–
–
–
70
–
700
200
1.0
ps
ps
tJ
Measured at 66.67 MHz, loaded
outputs
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature
Devices[7]
Parameter
Name
Description
Min
Typ.
Max
Unit
t1
Output Frequency
30 pF load
10 pF load
10
10
–
100
133.33
MHz
MHz
Duty Cycle[6] = t2 ÷ t1
Duty Cycle[6] = t2 ÷ t1
Rise Time[6]
Fall Time[6]
Output to Output Skew[6]
Measured at 1.4V, Fout = 66.67 MHz
Measured at 1.4V, Fout < 50.0 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
40.0
45.0
–
50.0
50.0
–
60.0
55.0
1.50
1.50
250
%
%
t3
t4
t5
ns
ns
ps
ps
–
–
–
85
–
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2
–
±350
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2. Measured in
PLL Bypass Mode, CY2309 device
only.
1
5
8.7
ns
Device to Device Skew[6]
Output Slew Rate[6]
Cycle to Cycle Jitter[6]
PLL Lock Time[6]
t7
Measured at VDD/2 on the CLKOUT
pins of devices
–
1
–
–
–
–
700
ps
V/ns
ps
t8
Measured between 0.8V and 2.0V
using Test Circuit #2
tJ
Measured at 66.67 MHz, loaded
outputs
60
–
200
1.0
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Operating Conditions for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter
VDD
Description
Min
3.0
–40
–
Max
3.6
85
30
10
7
Unit
V
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
°C
pF
pF
pF
CL
CL
CIN
–
–
Document #: 38-07140 Rev. *H
Page 6 of 17
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CY2305
CY2309
Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter
Description
Input LOW Voltage[5]
Test Conditions
Min
–
Max
0.8
Unit
V
VIL
VIH
IIL
Input HIGH Voltage[5]
Input LOW Current
Input HIGH Current
Output LOW Voltage[6]
2.0
–
–
V
VIN = 0V
50.0
100.0
0.4
μA
μA
V
IIH
VIN = VDD
–
VOL
IOL = 8 mA (–1)
IOH =12 mA (–1H)
–
Output HIGH Voltage[6]
VOH
IOH = –8 mA (–1)
IOL = –12 mA (–1H)
2.4
–
V
I
DD (PD mode)
Power down Supply Current
Supply Current
REF = 0 MHz
–
–
25.0
35.0
μA
IDD
Unloaded outputs at 66.67
MHz, SEL inputs at VDD
mA
Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices[7]
Parameter
Name
Test Conditions
Min
Typ.
Max
Unit
MHz
t1
Output Frequency
30 pF load
10 pF load
10
10
–
100
133.33 MHz
Duty Cycle[6] = t2 ÷ t1
Rise Time[6]
Fall Time[6]
Measured at 1.4V, Fout = 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
40.0
50.0
–
60.0
2.50
2.50
250
%
ns
ns
ps
ps
t3
t4
–
–
–
–
–
Output to Output Skew[6]
t5
85
–
t6A
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[6]
±350
t6B
t7
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL
1
–
5
–
8.7
ns
ps
CLKOUT Rising Edge[6]
Device to Device Skew[6]
Bypass Mode, CY2309 device only.
Measured at VDD/2 on the CLKOUT pins
of devices
700
Cycle to Cycle Jitter[6]
PLL Lock Time[6]
tJ
Measured at 66.67 MHz, loaded outputs
–
–
70
–
200
1.0
ps
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature
Devices[7]
Parameter
Name
Description
Min
Typ.
Max
Unit
t1
Output Frequency
30 pF load
10 pF load
10
10
–
100
133.33 MHz
MHz
Duty Cycle[6] = t2 ÷ t1
Duty Cycle[6] = t2 ÷ t1
Rise Time[6]
Fall Time[6]
Output to Output Skew[6]
Measured at 1.4V, Fout = 66.67 MHz
Measured at 1.4V, Fout < 50.0 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
40.0
45.0
–
50.0
50.0
–
60.0
55.0
1.50
1.50
250
%
%
t3
ns
ns
ps
ps
t4
–
–
t5
–
85
–
t6A
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[6]
–
±350
t6B
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL
1
5
8.7
ns
CLKOUT Rising Edge[6]
Bypass Mode, CY2309 device only.
Document #: 38-07140 Rev. *H
Page 7 of 17
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CY2305
CY2309
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature
Devices[7]
Parameter
Name
Description
Min
Typ.
Max
Unit
Device to Device Skew[6]
t7
Measured at VDD/2 on the CLKOUT pins
of devices
–
–
700
ps
Output Slew Rate[6]
t8
Measured between 0.8V and 2.0V using
Test Circuit #2
1
–
–
V/ns
Cycle to Cycle Jitter[6]
PLL Lock Time[6]
tJ
Measured at 66.67 MHz, loaded outputs
–
–
60
–
200
1.0
ps
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Switching Waveforms
Figure 3. Duty Cycle Timing
t
1
t
2
1.4V
1.4V
1.4V
Figure 4. All Outputs Rise/Fall Time
3.3V
0V
2.0V
0.8V
2.0V
0.8V
OUTPUT
t
3
t
4
Figure 5. Output-Output Skew
1.4V
OUTPUT
OUTPUT
1.4V
t
5
Figure 6. Input-Output Propagation Delay
V
DD/2
INPUT
VDD/2
OUTPUT
t
6
Document #: 38-07140 Rev. *H
Page 8 of 17
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CY2305
CY2309
Switching Waveforms (continued)
Figure 7. Device-Device Skew
VDD/2
CLKOUT, Device 1
CLKOUT, Device 2
VDD/2
t7
Document #: 38-07140 Rev. *H
Page 9 of 17
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CY2305
CY2309
Typical Duty Cycle[8] and I Trends[9] for CY2305-1 and CY2309-1
DD
Duty Cycle Vs VDD
Duty Cycle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
60
58
56
54
52
50
48
46
44
42
40
58
56
54
52
50
48
46
44
42
40
33 MHz
66 MHz
100 MHz
133 MHz
33 MHz
66 MHz
100 MHz
3
3.1
3.2
3.3
3.4
3.5
3.6
3
3.1
3.2
3.3
3.4
3.5
3.6
VDD (V)
VDD (V)
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
60
58
56
54
52
50
48
46
44
42
40
60
58
56
54
52
50
48
46
44
42
40
-40C
0C
-40C
0C
25C
70C
85C
25C
70C
85C
20
40
60
80
100
120
140
20
40
60
80
100
120
140
Frequency (MHz)
Frequency (MHz)
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
140
120
100
80
140
120
100
80
33 MHz
66 MHz
100 MHz
33 MHz
66 MHz
100 MHz
60
60
40
40
20
20
0
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
# of Loaded Outputs
# of Loaded Outputs
Notes
8. Duty Cycle is taken from typical chip measured at 1.4V.
9.
I
data is calculated from I = I
+ nCVf, where I
is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply
DD
DD
CORE
CORE
Voltage (V); f = frequency (Hz)).
Document #: 38-07140 Rev. *H
Page 10 of 17
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CY2305
CY2309
Typical Duty Cycle[8] and IDD Trends[9] for CY2305-1H and CY2309-1H
Duty Cycle Vs VDD
Duty Cycle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
60
58
56
58
56
54
52
50
48
46
44
42
40
54
52
50
48
46
44
42
40
33 MHz
66 MHz
100 MHz
133 MHz
33 MHz
66 MHz
100 MHz
3
3.1
3.2
3.3
3.4
3.5
3.6
3
3.1
3.2
3.3
3.4
3.5
3.6
VDD (V)
VDD (V)
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
60
58
56
54
52
50
48
46
44
42
40
60
58
56
54
52
50
48
46
44
42
40
-40C
0C
-40C
0C
25C
70C
85C
25C
70C
85C
20
40
60
80
100
120
140
20
40
60
80
100
120
140
Frequency (MHz)
Frequency (MHz)
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
160
140
120
100
80
160
140
120
100
80
33 MHz
66 MHz
100 MHz
33 MHz
66 MHz
100 MHz
60
60
40
40
20
20
0
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
# of Loaded Outputs
# of Loaded Outputs
Document #: 38-07140 Rev. *H
Page 11 of 17
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CY2305
CY2309
Test Circuits
Test Circuit # 2
Test Circuit # 1
V
DD
V
1 kΩ
1 kΩ
DD
0.1 μ F
CLK out
0.1 μ F
OUTPUTS
GND
OUTPUTS
10 pF
C
LOAD
V
DD
V
DD
0.1 μ F
GND
0.1 μ F
GND
GND
For parameter t8 (output slew rate) on -1H devices
Ordering Information for CY2305
Ordering Code
Package Type
Operating Range
Commercial
CY2305SC-1[10]
CY2305SC-1T[10]
CY2305SI-1[10]
8-pin 150-mil SOIC
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
Commercial
Industrial
CY2305SI-1T[10]
CY2305SC-1H[10]
CY2305SC-1HT[10]
CY2305SI-1H[10]
CY2305SI-1HT[10]
Pb-Free
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
Industrial
Commercial
Commercial
Industrial
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
8-pin 150-mil SOIC – Tape and Reel
Industrial
CY2305SXC-1[10]
CY2305SXC-1T[10]
CY2305SXI-1[10]
CY2305SXI-1T[10]
CY2305SXC-1H[10]
CY2305SXC-1HT[10]
CY2305SXI-1H[10]
CY2305SXI-1HT[10]
CY2305ESXC-1
CY2305ESXC-1T
CY2305ESXI-1
8-pin 150-mil SOIC
Commercial
Commercial
Industrial
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
Industrial
Commercial
Commercial
Industrial
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
Industrial
Commercial
Commercial
Industrial
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
CY2305ESXI-1T
CY2305ESXC-1H
CY2305ESXC-1HT
CY2305ESXI-1H
CY2305ESXI-1HT
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
Industrial
Commercial
Commercial
Industrial
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
8-pin 150-mil SOIC – Tape and Reel
Industrial
Note
10. Not recommended for new designs.
Document #: 38-07140 Rev. *H
Page 12 of 17
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CY2305
CY2309
Ordering Information for CY2309
Ordering Code
Package Type
Operating Range
Commercial
CY2309SC-1[10]
CY2309SC-1T[10]
CY2309SI-1[10]
16-pin 150-mil SOIC
16-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC
Commercial
Industrial
CY2309SI-1T[10]
CY2309SC-1H[10]
CY2309SC-1HT[10]
CY2309ZC-1H[10]
CY2309ZC-1HT[10]
CY2309SI-1H[10]
CY2309SI-1HT[10]
Pb-Free
16-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC
Industrial
Commercial
Commercial
Commercial
Commercial
Industrial
16-pin 150-mil SOIC – Tape and Reel
16-pin 4.4-mm TSSOP
16-pin 4.4-mm TSSOP – Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC – Tape and Reel
Industrial
CY2309SXC-1[10]
CY2309SXC-1T[10]
CY2309SXI-1[10]
CY2309SXI-1T[10]
CY2309SXC-1H[10]
CY2309SXC-1HT[10]
CY2309SXI-1H[10]
CY2309SXI-1HT[10]
CY2309ZXC-1H[10]
CY2309ZXC-1HT[10]
CY2309ZXI-1H[10]
CY2309ZXI-1HT[10]
CY2309ESXC-1
CY2309ESXC-1T
CY2309ESXI-1
16-pin 150-mil SOIC
Commercial
Commercial
Industrial
16-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC
Industrial
Commercial
Commercial
Industrial
16-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC – Tape and Reel
16-pin 4.4-mm TSSOP
Industrial
Commercial
Commercial
Industrial
16-pin 4.4-mm TSSOP – Tape and Reel
16-pin 4.4-mm TSSOP
16-pin 4.4-mm TSSOP – Tape and Reel
16-pin 150-mil SOIC
Industrial
Commercial
Commercial
Industrial
16-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC
CY2309ESXI-1T
CY2309ESXC-1H
CY2309ESXC-1HT
CY2309ESXI-1H
CY2309ESXI-1HT
CY2309EZXC-1H
CY2309EZXC-1HT
CY2309EZXI-1H
CY2309EZXI-1HT
16-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC
Industrial
Commercial
Commercial
Industrial
16-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC – Tape and Reel
16-pin 4.4-mm TSSOP
Industrial
Commercial
Commercial
Industrial
16-pin 4.4-mm TSSOP – Tape and Reel
16-pin 4.4-mm TSSOP
16-pin 4.4-mm TSSOP – Tape and Reel
Industrial
Document #: 38-07140 Rev. *H
Page 13 of 17
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CY2305
CY2309
Package Drawing and Dimensions
8 Lead (150 Mil) SOIC - S08
Figure 8. 8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
51-85066-*C
0.0138[0.350]
0.0192[0.487]
Figure 9. 16-Lead (150-Mil) SOIC S16
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
9
16
0.010[0.254]
0.016[0.406]
X 45°
0.386[9.804]
0.393[9.982]
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0°~8°
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
51-85068-*B
Document #: 38-07140 Rev. *H
Page 14 of 17
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CY2305
CY2309
Package Drawing and Dimensions (continued)
Figure 10. 16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
1
MAX.
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05gms
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
16
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.85[0.033]
0.95[0.037]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
4.90[0.193]
5.10[0.200]
51-85091-*A
Document #: 38-07140 Rev. *H
Page 15 of 17
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CY2305
CY2309
Document History Page
Document Title: CY2305/CY2309 Low-Cost 3.3V Zero Delay Buffer
Document Number: 38-07140
Orig. of Submission
REV.
ECN
Description of Change
Change
Date
**
110249
111117
SZV
10/19/01
03/01/02
Change from Spec number: 38-00530 to 38-07140
*A
CKN
Added t6B row to the Switching Characteristics Table; also added the letter
“A” to the t6A row
Corrected the table title from CY2305SC-IH and CY2309SC-IH to
CY2305SI-IH and CY2309SI-IH
*B
117625
HWT
10/21/02
Added eight-pin TSSOP packages (CY2305ZC-1 and CY2305ZC-1T) to the
ordering information table.
Added the Tape and Reel option to all the existing packages:
CY2305SC-1T, CY2305SI-1T, CY2305SC-1HT, CY2305SI-1HT,
CY2305ZC-1T, CY2309SC-1T, CY2309SI-1T, CY2309SC-1HT,
CY2309SI-1HT, CY2309ZC-1HT, CY2309ZI-1HT
*C
*D
*E
121828
131503
214083
RBI
RGL
RGL
12/14/02
12/12/03
Power up requirements added to Operating Conditions information
Added Lead-free for all the devices in the ordering information table
See ECN Added a Lead-free with the new coding for all SOIC devices in the ordering
information table
*F
*G
*H
291099
390582
2542461
RGL
RGL
See ECN Added TSSOP Lead-free devices
See ECN Added typical values for jitter
AESA
07/23/08
Updated template. Added Note “Not recommended for new designs.”
Added part number CY2305ESXC-1, CY2305ESXC-1T, CY2305ESXI-1,
CY2305ESXI-1T, CY2305ESXC-1H, CY2305ESXC-1HT, CY2305ESXI-1H,
CY2305ESXI-1HT, CY2309ESXC-1, CY2309ESXC-1T, CY2309ESXI-1,
CY2309ESXI-1T, CY2309ESXC-1H, CY2309ESXC-1HT, CY2309ESXI-1H,
CY2309ESXI-1HT, CY2309EZXC-1H, CY2309EZXC-1HT, CY2309EZXI-1H,
and CY2309EZXI-1HT in ordering information table.
Removed part number CY2305SZC-1, CY2305SZC-1T, CY2305SZI-1,
CY2305SZI-1T, CY2305SZC-1H, CY2305SZC-1HT, CY2305SZI-1H,
CY2305SZI-1HT, CY2309SZC-1, CY2309SZC-1T, CY2309SZI-1,
CY2309SZI-1T, CY2309SZC-1H, CY2309SZC-1HT, CY2309SZI-1H,
CY2309SZI-1HT, CY2309ZZC-1H, CY2309ZZC-1HT, CY2309ZI-1H,
CY2309ZI-1HT, CY2309ZZI-1H, and CY2309ZZI-1HT in Ordering
Information table.
Changed Lead-Free to Pb-Free.
Document #: 38-07140 Rev. *H
Page 16 of 17
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CY2305
CY2309
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07140 Rev. *H
Revised July 23, 2008
Page 17 of 17
Pentium is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
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