CY2309CZXI-1T [CYPRESS]
3.3V Zero Delay Clock Buffer; 3.3V零延迟时钟缓冲器
| 型号： | CY2309CZXI-1T |
| 厂家： | 
CYPRESS |
| 描述： | 3.3V Zero Delay Clock Buffer |
| 文件： | 总14页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2305C
CY2309C
PRELIMINARY
3.3V Zero Delay Clock Buffer
CY2309C. It accepts one reference input and drives out five low
skew clocks. The -1H versions of each device operate up to
100-133 MHz frequencies and have higher drive than the -1
devices. All parts have on-chip PLLs which lock to an input clock
on the REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad.
Features
■ 10 MHz to 100-133 MHz operating range, compatiblewith CPU
and PCI bus frequencies
■ Zero input and output propagation delay
■ Multiple low skew outputs
The CY2309C has two banks of four outputs each that are
controlled by the select inputs as shown in the “Select Input
Decoding for CY2309C” on page 3. If all output clocks are not
required, BankB is three-stated. The input clock is directly
applied to the outputs by the select inputs for chip and system
testing purposes.
■ One input drives five outputs (CY2305C)
■ One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C)
■ 50 ps typical cycle-cycle jitter (15 pF, 66 MHz)
■ Test Mode to bypass phase locked loop (PLL) (CY2309C) only,
see “Select Input Decoding for CY2309C” on page 3
The CY2305C and CY2309C PLLs enter a power down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off. This
results in less than 12.0 μA of current draw for commercial
temperature devices and 25.0 μA for industrial temperature
parts. The CY2309C PLL shuts down in one additional case as
shown in the “Select Input Decoding for CY2309C” on page 3.
■ Available in space saving 16-pin 150 Mil SOIC or 4.4 mm
TSSOP packages (CY2309C), and 8-pin, 150 Mil SOIC
package (CY2305C)
■ 3.3V operation
In the special case when S2:S1 is 1:0, the PLL is bypassed and
REF is output from DC to the maximum allowable frequency. The
part behaves like a non-zero delay buffer in this mode and the
outputs are not three-stated.
■ Industrial temperature available
Functional Description
The CY2305C and CY2309C are die replacement parts for
CY2305 and CY2309.
The CY2305C or CY2309C is available in two or three different
configurations as shown in the “Ordering Information” on
page 11. The CY2305C-1 or CY2309C-1 is the base part. The
CY2305-1H or CY2309-1H is the high drive version of the -1. Its
rise and fall times are much faster than the -1s.
The CY2309C is a low cost 3.3V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC or
TSSOP package. The CY2305C is an 8-pin version of the
Logic Block Diagram for CY2309C
CLKOUT
MUX
PLL
REF
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
S2
Select Input
Decoding
S1
Cypress Semiconductor Corporation
Document Number: 38-07672 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 5, 2007
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
Logic Block Diagram for CY2305C
PLL
CLKOUT
CLK1
REF
CLK2
CLK3
CLK4
Document Number: 38-07672 Rev. *F
Page 2 of 14
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
Pinouts
CY2309C
Figure 1. Pin Diagram - 16 Pin SOIC/TSSOP
SOIC/TSSOP
Top View
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
CLKOUT
CLKA1
CLKA4
CLKA3
VDD
CY2309C
CLKA2
VDD
GND
GND
CLKB4
CLKB3
S1
CLKB1
CLKB2
S2
Table 1. Pin Definition - 16 Pin SOIC/TSSOP
Pin
Signal
Description
1
REF[1]
CLKA1[2]
CLKA2[2]
VDD
Input reference frequency
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V supply
2
3
4
5
GND
Ground
6
CLKB1[2]
CLKB2[2]
S2[3]
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
7
8
9
S1[3]
Select input, bit 1
10
11
12
13
14
15
16
CLKB3[2]
CLKB4[2]
GND
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
VDD
CLKA3[2]
CLKA4[2]
CLKOUT[2]
3.3V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
Table 2. Select Input Decoding for CY2309C
S2
0
S1
0
CLOCK A1–A4
Three state
Driven
CLOCK B1–B4
Three state
Three state
Driven
CLKOUT[4]
Driven
Output Source
PLL
PLL Shutdown
N
N
Y
N
0
1
Driven
PLL
1
0
Driven
Driven
Reference
PLL
1
1
Driven
Driven
Driven
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output is adjusted to change the skew between the reference and output.
Document Number: 38-07672 Rev. *F
Page 3 of 14
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
CY2305C
Figure 2. Pin Diagram - 8 Pin SOIC
SOIC
Top View
1
8
CLKOUT
CLK4
V
DD
REF
CLK2
CLK1
GND
CY2305C
2
3
4
7
6
5
CLK3
Table 3. Pin Description - 8 Pin SOIC
Pin
1
Signal
Description
REF[1]
CLK2[2]
CLK1[2]
GND
Input reference frequency
Buffered clock output
Buffered clock output
Ground
2
3
4
5
CLK3[2]
Buffered clock output
3.3V supply
6
VDD
7
CLK4[2]
Buffered clock output
8
CLKOUT[2]
Buffered clock output, internal feedback on this pin
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal
feedback to the PLL, its relative loading can adjust the input or output delay.
For applications requiring zero input or output delay, all outputs including CLKOUT are equally loaded. Even if CLKOUT is not used,
it must have a capacitive load equal to that on other outputs for obtaining zero input or output delay.
For zero output or output skew, all outputs are loaded equally. For further information refer to the application note entitled “CY2305
and CY2309 as PCI and SDRAM Buffers”.
Document Number: 38-07672 Rev. *F
Page 4 of 14
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
Absolute Maximum Conditions
Supply Voltage to Ground Potential................–0.5V to +4.6V
DC Input Voltage (Except REF) ............–0.5V to VDD + 0.5V
DC Input Voltage REF ...........................–0.5V to VDD + 0.5V
Storage Temperature ................................. –65°C to +150°C
Junction Temperature................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ...........................> 2,000V
Operating Conditions for CY2305CSXC-XX and CY2309CSXC-XX
Operating Conditions table for CY2305CSXC-XX and CY2309CSXC-XX Commercial Temperature Devices.
Parameter
VDD
Description
Min
3.0
0
Max
3.6
70
30
10
7
Unit
V
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
°C
pF
pF
pF
ms
CL
CL
CIN
tPU
Power up time for all VDDs to reach minimum specified voltage
(power ramps are monotonic)
0.05
50
Electrical Characteristics for CY2305CSXC-XX and CY2309CSXC-XX
Electrical Characteristics table for CY2305CSXC-XX and CY2309CSXC-XX Commercial Temperature Devices.
Parameter
Description
Input LOW Voltage[5]
Input HIGH Voltage[5]
Input LOW Current
Input HIGH Current
Output LOW Voltage[6]
Test Conditions
Min
–0.3
2.0
–
Max
0.8
Unit
V
VIL
VIH
IIL
VDD + 0.3
50
V
VIN = 0V
μA
μA
V
IIH
VIN = VDD
–
100
VOL
IOL = 8 mA (–1)
–
0.4
I
OH = 12 mA (–1H)
VOH
Output HIGH Voltage[6]
IOH = –8 mA (–1)
IOL = –12 mA (–1H)
2.4
–
V
I
DD (PD mode)
Power Down Supply Current REF = 0 MHz
Supply Current Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
–
–
12.0
32
μA
IDD
mA
Notes
5. .REF input has a threshold voltage of V /2.
DD
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *F
Page 5 of 14
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
Switching Characteristics for CY2305CSXC-XX and CY2309CSXC-XX
Switching characteristics table for CY2305CSXC-1 and CY2309CSXC-1 Commercial Temperature Devices. All parameters are
specified with loaded outputs.
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
30 pF load
10 pF load
10
10
–
100
133.33
MHz
MHz
Duty Cycle[6] = t2 ÷ t1
Rise Time[6]
Fall Time[6]
Measured at 1.4V, Fout = 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
40.0
50.0
60.0
2.25
2.25
200
%
ns
ns
ps
ps
t3
–
–
–
–
–
–
–
0
t4
t5
Output to Output Skew[6]
t6A
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[6]
±350
t6B
t7
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL
1
–
5
0
8.7
ns
ps
CLKOUT Rising Edge[6]
Bypass Mode, CY2309C device only.
Device to Device Skew[6] Measured at VDD/2 on the CLKOUT pins
of devices
700
tJ
Cycle to Cycle Jitter, peak[6] Measured at 66.67 MHz, loaded outputs
–
–
50
–
175
1.0
ps
tLOCK
PLL Lock Time[6]
Stable power supply, valid clock
presented on REF pin
ms
Switching characteristics table for CY2305CSXC-1H and CY2309CSXC-1H Commercial Temperature Devices. All parameters are
specified with loaded outputs.
Parameter
t1
Name
Description
Min
Typ
Max
Unit
Output Frequency
30-pF load
10-pF load
10
10
–
100
133.33
MHz
MHz
Duty Cycle[6] = t2 ÷ t1
Duty Cycle[6] = t2 ÷ t1
Rise Time[6]
Fall Time[6]
Output to Output Skew[6]
Measured at 1.4V, Fout = 66.67 MHz
Measured at 1.4V, Fout < 50.0 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
40.0
45.0
–
50.0
50.0
–
60.0
55.0
1.5
%
%
t3
ns
ns
ps
ps
t4
–
–
1.5
t5
–
–
200
±350
t6A
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[6]
–
0
t6B
t7
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL
1
–
1
5
0
–
8.7
700
–
ns
ps
CLKOUT Rising Edge[6]
Bypass Mode, CY2309C device only.
Device to Device Skew[6] Measured at VDD/2 on the CLKOUT pins
of devices
t8
Output Slew Rate[6]
Measured between 0.8V and 2.0V using
Test Circuit #2
V/ns
tJ
Cycle to Cycle Jitter, peak[6] Measured at 66.67 MHz, loaded outputs
–
–
–
–
175
1.0
ps
tLOCK
PLL Lock Time[6]
Stable power supply, valid clock
presented on REF pin
ms
Document Number: 38-07672 Rev. *F
Page 6 of 14
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
Operating Conditions for CY2305CSXI-XX and CY2309CSXI-XX
Operating conditions table for CY2305CSXI-XX and CY2309CSXI-XX Industrial Temperature Devices.
Parameter
Description
Min
3.0
–40
–
Max
3.6
85
30
10
7
Unit
V
VDD
TA
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
°C
pF
pF
pF
CL
CL
–
CIN
–
Electrical Characteristics for CY2305CSXI-XX and CY2309CSXI-XX
Electrical characteristics table for CY2305CSXI-XX and CY2309CSXI-XX Industrial Temperature Devices.
Parameter
VIL
Description
Input LOW Voltage[5]
Input HIGH Voltage[5]
Input LOW Current
Test Conditions
Min
–0.3
2.0
–
Max
0.8
Unit
V
VIH
IIL
VDD + 0.3
50.0
V
VIN = 0V
μA
μA
V
IIH
Input HIGH Current
Output LOW Voltage[6]
VIN = VDD
–
100.0
0.4
VOL
IOL = 8 mA (–1)
–
I
OH =12 mA (–1H)
IOH = –8 mA (–1)
OL = –12 mA (–1H)
VOH
Output HIGH Voltage[6]
2.4
–
V
I
IDD (PD mode) Power down Supply Current
IDD Supply Current
REF = 0 MHz
–
–
25.0
35
μA
Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
mA
Document Number: 38-07672 Rev. *F
Page 7 of 14
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
Switching Characteristics for CY2305CSXI-XX and CY2309CSXI-XX
Switching characteristics table for CY2305CSXI-1and CY2309CSXI-1 Industrial Temperature Devices. All parameters are specified
with loaded outputs.
Parameter
t1
Name
Test Conditions
30 pF load
10 pF load
Min
Typ
Max
Unit
Output Frequency
10
10
100
133.33
MHz
MHz
Duty Cycle[6] = t2 ÷ t1
Rise Time[6]
Fall Time[6]
Measured at 1.4V, Fout = 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
40.0
50.0
60.0
2.25
2.25
200
%
ns
ns
ps
ps
t3
–
–
–
–
–
–
–
0
t4
t5
Output to Output Skew[6]
t6A
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[6]
±350
t6B
Delay, REF Rising Edge to Measured at VDD/2. Measured in
1
5
8.7
ns
CLKOUT Rising Edge[6]
Device to Device Skew[6]
PLL Bypass Mode, CY2309C device
only.
t7
Measured at VDD/2 on the CLKOUT
pins of devices
Cycle to Cycle Jitter, peak[6] Measured at 66.67 MHz, loaded
outputs
–
–
–
0
50
–
700
175
1.0
ps
ps
tJ
tLOCK
PLL Lock Time[6]
Stable power supply, valid clock
presented on REF pin
ms
Switching characteristics table for CY2305CSXI-1H and CY2309CSXI-1H Industrial Temperature Device. All parameters are specified
with loaded outputs.
Parameter
t1
Name
Description
Min
Typ
Max
Unit
Output Frequency
30 pF load
10 pF load
10
10
–
100
133.33
MHz
MHz
Duty Cycle[6] = t2 ÷ t1
Duty Cycle[6] = t2 ÷ t1
Rise Time[6]
Fall Time[6]
Output to Output Skew[6]
Measured at 1.4V, Fout = 66.67 MHz
Measured at 1.4V, Fout < 50.0 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
40.0
45.0
–
50.0
50.0
–
60.0
55.0
1.5
%
%
t3
ns
ns
ps
ps
t4
–
–
1.5
t5
–
–
200
±350
t6A
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[6]
–
0
t6B
Delay, REF Rising Edge to Measured at VDD/2. Measured in
1
5
8.7
ns
CLKOUT Rising Edge[6]
Device to Device Skew[6]
Output Slew Rate[6]
PLL Bypass Mode, CY2309C device
only.
t7
Measured at VDD/2 on the CLKOUT
pins of devices
–
1
–
–
0
–
–
–
700
ps
V/ns
ps
t8
Measured between 0.8V and 2.0V
using Test Circuit #2
Cycle to Cycle Jitter, peak[6] Measured at 66.67 MHz, loaded
outputs
tJ
175
1.0
tLOCK
PLL Lock Time[6]
Stable power supply, valid clock
presented on REF pin
ms
Document Number: 38-07672 Rev. *F
Page 8 of 14
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
Switching Waveforms
Figure 3. Duty Cycle Timing
t
1
t
2
1.4V
1.4V
1.4V
Figure 4. All Outputs Rise/Fall Time
3.3V
0V
2.0V
0.8V
2.0V
0.8V
OUTPUT
t
3
t
4
Figure 5. Output-Output Skew
1.4V
OUTPUT
1.4V
OUTPUT
t
5
Figure 6. Input-Output Propagation Delay
V
DD/2
INPUT
VDD/2
OUTPUT
t
6
Figure 7. Device-Device Skew
VDD/2
CLKOUT, Device 1
CLKOUT, Device 2
VDD/2
t7
Document Number: 38-07672 Rev. *F
Page 9 of 14
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
Test Circuits
Test Circuit # 2
Test Circuit # 1
V
DD
V
1 kΩ
1 kΩ
DD
0.1 μ F
CLK out
0.1 μ F
OUTPUTS
GND
OUTPUTS
10 pF
C
LOAD
V
DD
V
DD
0.1 μ F
GND
0.1 μ F
GND
GND
For parameter t8 (output slew rate) on -1H devices
Document Number: 38-07672 Rev. *F
Page 10 of 14
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
Ordering Information
Ordering Code
Pb-Free - CY2305C
CY2305CSXC-1
CY2305CSXC-1T
CY2305CSXC-1H
CY2305CSXC-1HT
CY2305CSXI-1
Package Type
Operating Range
Commercial
8-pin 150 Mil SOIC
8-pin 150 Mil SOIC – Tape and Reel
8-pin 150 Mil SOIC
Commercial
Commercial
Commercial
Industrial
8-pin 150 Mil SOIC – Tape and Reel
8-pin 150 Mil SOIC
CY2305CSXI-1T
CY2305CSXI-1H
CY2305CSXI-1HT
Pb-Free- CY2309C
CY2309CSXC-1
CY2309CSXC-1T
CY2309CSXC-1H
CY2309CSXC-1HT
CY2309CSXI-1
8-pin 150 Mil SOIC – Tape and Reel
8-pin 150 Mil SOIC
Industrial
Industrial
8-pin 150 Mil SOIC – Tape and Reel
Industrial
16-pin 150 Mil SOIC
Commercial
Commercial
Commercial
Commercial
Industrial
16-pin 150 Mil SOIC – Tape and Reel
16-pin 150 Mil SOIC
16-pin 150 Mil SOIC – Tape and Reel
16-pin 150 Mil SOIC
CY2309CSXI-1T
CY2309CSXI-1H
CY2309CSXI-1HT
CY2309CZXC-1
CY2309CZXC-1T
CY2309CZXC-1H
CY2309CZXC-1HT
CY2309CZXI-1
16-pin 150 Mil SOIC – Tape and Reel
16-pin 150 Mil SOIC
Industrial
Industrial
16-pin 150 Mil SOIC – Tape and Reel
16-pin 4.4 mm TSSOP
Industrial
Commercial
Commercial
Commercial
Commercial
Industrial
16-pin 4.4 mm TSSOP – Tape and Reel
16-pin 4.4 mm TSSOP
16-pin 4.4 mm TSSOP – Tape and Reel
16-pin 4.4 mm TSSOP
CY2309CZXI-1T
CY2309CZXI-1H
CY2309CZXI-1HT
16-pin 4.4 mm TSSOP – Tape and Reel
16-pin 4.4 mm TSSOP
Industrial
Industrial
16-pin 4.4 mm TSSOP – Tape and Reel
Industrial
Document Number: 38-07672 Rev. *F
Page 11 of 14
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
Package Drawing and Dimensions
Figure 8. 8-Pin (150 Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
Figure 9. 16-Pin (150 Mil) SOIC S16
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
9
16
0.010[0.254]
0.016[0.406]
X 45°
0.386[9.804]
0.393[9.982]
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0°~8°
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
Document Number: 38-07672 Rev. *F
Page 12 of 14
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
Figure 10. 16-Pin TSSOP 4.40 MM Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
1
MAX.
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05gms
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
16
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.85[0.033]
0.95[0.037]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
4.90[0.193]
5.10[0.200]
Document Number: 38-07672 Rev. *F
Page 13 of 14
[+] Feedback
CY2305C
CY2309C
PRELIMINARY
Document History Page
Document Title: CY2305C CY2309C 3.3V Zero Delay Clock Buffer
Document Number: 38-07672
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
224421
268571
276453
See ECN
See ECN
See ECN
RGL
New datasheet
Added bullet for 5V tolerant inputs in the features
*A
*B
RGL
RGL
Minor Change: Moved one sentence from the features to the Functional
Description
*C
*D
*E
303063
318315
344815
See ECN
See ECN
See ECN
RGL
RGL
RGL
Updated datasheet as per characterization data
Datasheet rewrite
Minor Error: Corrected the header of all the AC/DC tables with the right part
numbers.
*F
1279889
See ECN
KVM
Changed title from “Low Cost 3.3V Zero Delay Buffer” to “3.3V Zero Delay
Clock Buffer”
Specified the VIL minimum value to -0.3V
Specified the VIH maximum value to VDD + 0.3V
Changed DC Input Voltage (REF) maximum value in Absolute Maximum
section
Removed references to 5V tolerant inputs (pages 1 and 2)
Removed Pentium compatibility reference
Added CY2305C block diagram
Added “peak” to the jitter specifications
Changed typical jitter from 75 ps to 50 ps for standard drive devices
For standard drive devices, tightened rise/fall times from 2.5 ns to 2.25 ns
Tightened cycle-to-cycle jitter from 200 ps to 175 ps
Tightened output-to-output skew from 250 ps to 200 ps
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07672 Rev. *F
Revised July 5, 2007
Page 14 of 14
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
2
trademarks referenced herein are property of the respective corporations. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
2
2
2
Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
[+] Feedback
相关型号：
CY2309ESXC-1H
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16
CYPRESS
CY2309ESXC-1T
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16
CYPRESS
CY2309ESXI-1HT
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16
CYPRESS
CY2309EZXC-1HT
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16
CYPRESS
CY2309EZXI-1H
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16
CYPRESS
CY2309EZXI-1HT
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16
CYPRESS
©2020 ICPDF网 联系我们和版权申明