AUIRB24427S_15 [INFINEON]
Matched propagation delay for both channels;
| 型号： | AUIRB24427S_15 |
| 厂家： | 
Infineon |
| 描述： | Matched propagation delay for both channels |
| 文件： | 总20页 (文件大小：796K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AUIRB24427S
Features
Product Summary
Topology
Very low output resistance
Dual Low Side Driver
12.5 V – 24 V
> 6 A
Extended supply voltage range: 12.5V to 24V
TTL/CMOS compatible inputs
CMOS Schmitt-triggered inputs
Matched propagation delay for both channels
Outputs in phase with inputs
Enable function
Under Voltage Lock Out function
Automotive Qualified
Leadfree, RoHS compliant
VOUT
Io+ & I o- (VCC=15V)
Output Resistance
(max)
0.65 Ohm
55ns
tON & tOFF (max)
Typical Applications
Package
Automotive General Purpose Dual
Low Side Driver
Gate transformer driver
Bridge Tied Gate Transformer Driver
DC-DC converters secondary side driver
Hybrid Power Train Driver
PSOIC-8N
Typical Connection Diagram
Logic level
Rg
Rg
EN
NC
OUTA
VCC
input
TO
INA
LOAD
COM
INB
+
-
Vbatt
OUTB
Standard Pack
Note
Orderable Part Number
AUIRB24427STR
Package Type
PSOIC8-N
Form
Tape & Reel
Quantity
2500
Sept 29nd, 2014
1
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM lead. Stresses beyond those listed under "
Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only; and
functional operation of the device at these or any other condition beyond those indicated in the ―Recommended
Operating Conditions‖ is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. The thermal resistance and power dissipation ratings are measured under board mounted
and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified.
Symbol
Definition
Min.
Max.
Units
Vcc
Fixed supply voltage
-0.3
24
VO
VIN
VEN
RthJc
TJ
Output voltage
-0.3
-0.3
-0.3
—
24
5.5
5.5
4
V
Logic input voltage
Logic enable voltage
Thermal resistance, junction to case
Junction temperature
°C/W
°C
—
150
150
300
Storage temperature
TS
-55
—
Lead temperature (soldering, 10 seconds)
TL
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
All voltage parameters are absolute voltage referenced to COM.
Symbol
Definition
Min.
Max.
Units
Vcc
VO
VIN
VEN
TA
Fixed supply voltage
Output voltage
5
0
20
VCC
5
V
Logic input voltage
Logic enable voltage
Ambient temperature
External gate resistance
0
0
5
-40
2.5
125
°C
Rg
VCC to COM bypass capacitance – X7R
dielectric type.
CBP
1
F
Sept 29nd, 2014
2
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Static Electrical Characteristics
Unless otherwise specified, these specifications apply for an operating junction temperature range
of -40°C≤Ta≤125°C and power supply VCC=15 V. The VIN and IIN parameters are referenced to COM and are
applicable to input leads: INA and INB. The VO and IO parameters are referenced to COM and are applicable to the
output leads: OUTA and OUTB.
Symbol
Definition
Min
Typ
Max Units Test Conditions
VIL
Logic ―0‖ input voltage
0.8
VIH
VHYS-IN
VENL
Logic ―1‖ input voltage
Input voltage hysteresis
Logic ―0‖ enable voltage
Logic ―1‖ enable voltage
Enable voltage hysteresis
2.5
0.8
V
0.8
VENH
2.5
0.8
VHYS-EN
ROH+25
ROL+25
ROH+125
ROL+125
VOH+25
VOL+25
VOH+125
VOL+125
IIN+
Source Output resistance
Sink Output resistance
450
Ta=+25C
450
m
Source Output resistance
Sink Output resistance
650
Ta=+125C
650
Output high level voltage Vcc-Vo
Output low level voltage Vo
Output high level voltage Vcc-Vo
Output low level voltage Vo
Logic ―1‖ input bias current
Logic ―0‖ input bias current
Quiescent supply current
450
Ta=+25C, Iout=100mA
450
mV
650
Ta=+125C, Iout=100mA
650
25
50
1
VIN=5V, VCC=15V
VIN=0V, VCC=15V
µA
IIN-
VCC=15V, INA & INB
not switching
IQB
0.5
1.2
1.5
2.5
mA
VCCUVHYS Vcc supply undervoltage hysteresis
VCCUV+
Vcc supply undervoltage turn on threshold
Vcc supply undervoltage turn off threshold
10.5
11.5
10.0
12.6
11
V
A
VCCUV-
IO+
9.0
6
†)
Output high short circuit pulsed current(
Output high short circuit pulsed current(
VCC=15V, PW<10us
VCC=15V, PW<10us
†)
IO-
6
†) Guaranteed by design
(
Sept 29nd, 2014
3
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Dynamic Electrical Characteristics
Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C≤Ta≤125°C
with bias conditions of VCC = 15 V, CL = 4700pF. Refer to Figure T2 for switching time definition and to Figure T3 for
switching time test circuit (page 15).
Symbol
Definition
Min Typ Max Units Test Conditions
Propagation delay characteristics
TON
TOFF
TON-EN
TOFF-EN
tr
Turn-on propagation delay
Turn-off propagation delay
Enable Turn-on propagation delay
Enable Turn-off propagation delay
Turn-on rise time
—
—
—
—
—
—
40
55
40
55
33
33
ns
CBP=10uF
tf
Turn-off fall time
Input/Output table
EN
L
INA
INB
OUTA
OUTB
X
X
L
L
L
H
L
L
L
H
L
H
L
L
H
H
H
This table is held true in the voltages ranges defined in the recommended conditions section.
See also Fig. T1 on page 14.
Sept 29nd, 2014
4
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Functional Block Diagram:
Sept 29nd, 2014
5
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Input/Output/Enable Pin Equivalent Circuit Diagrams
VCC
ESD
Diode
OUTA
OUTB
24V
ESD
Diode
COM
Lead Definitions
PIN Symbol
Description
1
2
3
4
5
6
7
8
EN
INA
COM
INB
OUTB
VCC
OUTA
NC
Enable pin
Logic input for gate driver output (OUTA), in phase
Ground
Logic input for gate driver output (OUTB), in phase
Gate drive output B
Supply voltage
Gate drive output A
No connection
Sept 29nd, 2014
6
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Package Information
Sept 29nd, 2014
7
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Dimensions
Millimiter
Inches
MIN
MAX
1.70
0.10
---
MIN
---
MAX
.067
.004
---
A
A1
A2
b
---
0
0
1.25
0.31
0.17
.049
.012
.007
0.51
0.25
.020
.010
c
D
4.90
.193
D1
E
3.20
3.40
.126
.134
---
6.00 BSC
3.90 BSC
.236 BSC
.153 BSC
E1
E2
e
1.00
---
.039
1.27 BSC
.050 BSC
.010
h
0.25
0.40
0.50
1.27
.020
.050
L
.016
L1
L2
Θ
1.04 REF
0.25 BSC
.041 REF
.010 BSC
0
8
0
8
Recommended PCB footprint
Sept 29nd, 2014
8
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Part Marking Information
Sept 29nd, 2014
9
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Application Information
1. Gate Driver
The AUIRB24427S has been designer as a high current gate driver for single ended applications.
Thanks to its very high output current and low thermal resistance vs. pcb, it is capable to drive Mosfets
with very large input capacitance at frequencies up to fsw=200kHz or higher without the need of negative
supply. The following figure 1 shows the typical device application schematic:
LOAD
Logic level
input
Rg
EN
NC
OUTA
VCC
INA
COM
INB
Vcc
Cbp
LOAD
Rg
OUTB
Figure 1: typical gate driver application
Rg values have to be selected based on the requested tr and tf of the application and may vary between
2.5 and 20while the input capacitance of the Fets can go up to 20nF or more depending on fsw.
Since the very high peak output current, the bypass capacitor Cpb has to be mounted in the close proximity
of the Vcc and COM pins and a ceramic type with low ESR has to be chosen.
2. BT-GTD (Bridge Tied Gate Transformer Driver)
This is a popular configuration that allows driving high side Fets using a low side gate driver, the Fig. 2
shows the typical schematic for a single Fet drive:
Logic level
input
Cdec
EN
NC
OUTA
VCC
Rg,ss
PulseTransf.
Rg,ps
INA
COM
INB
Vcc
Cbp
OUTB
Rg,ps
Figure 2: Bridge Tied Gate Driver configuration
In this configuration the gate transformer parameters have a very important role, most manufacturers
indicate the following in their datasheets:
V*s ratings: this factor must be respected, in bipolar drive application (like the one shown in
Fig.2) a maximum of up to twice that parameter is still acceptable for most manufacturers, this
factor then must be chosen accordingly to the following formula:
Sept 29nd, 2014
10
www.irf.com
© 2014 International Rectifier
AUIRB24427S
ꢀ ꢁꢂꢃꢄꢅꢆꢇꢈꢉꢃꢊꢀ ꢋꢌ ꢍ ꢎꢏꢐꢑꢒꢃꢀꢃꢓ
(1)
ꢔꢕꢖ
where Vprim is the voltage applied to the primary, is the duty cycle and fsw the switching
frequency of the application;
N, turns ratio: usually 1:1, in some cases 1:2 or 1:1:1 (dual driver) this determines the voltage ratio
between primary and secondary;
Lp, primary inductance: this value determines the magnetizing inductance as follows:
ꢗꢘ ꢙ ꢗꢚ ꢀ ꢛ
(2)
where K is the coupling factor between primary and secondary windings.
LLK, leakage inductance: this parameter, usually indicated at primary, is equal to:
ꢗꢜꢝ ꢙ ꢗꢚ ꢀ ꢊꢞ ꢟ ꢛꢌ
(3)
The higher is Lm, the lower is the magnetizing current flowing into the transformer and consequent power
losses into the driver. On the other hand the lower is LLK, the lower and shorter will be the ringing of the
secondary LC network created by LLK, and Ciss of the Fet, damped by Rg,ss and much lower overshot will
appear on the Vgs across the Fet during transition. Then a too high Lm requires a very good mechanical
construction of the gate transformer to achieve high K and consequent low LLK.
In a gate driver application running in the range of 50kHz-200kHz and using the AUIRB24427S, a good
choice is usually a Lm between 300uH and 2mH and a LLK < 1uH. This translate for the formula (2) and (3)
above in a coupling factor K between 0.9940 and 0.9995
For good operation and to reduce unneeded power losses into the AUIRB24427S driver, the magnetizing
current has to be kept ILM < 0.5A, from this then derives a minimum Lm to be calculated as follows:
ꢓ
ꢗꢘꢒꢑꢠ ꢙ ꢢꢎꢣꢡꢤ ꢀ ꢔꢕꢖ
(4)
Where Vg is the gate driving voltage of the Fet
Fig. 2.a show a good design waveform obtained with the following parameters:
Vg=+/-15V, Lm=400uH, LLK=0.4uH, N=1, fsw=100kHz, CissFET =10nF, Rg,ps=3, Rg,ss=4Cdec=1uF
Cdec is the AC coupling capacitor needed to reset the driver transformer flux, its value has to be calculated
in a way that the voltage across it can be considered constant during normal operation. The higher the fsw
the smaller will be Cdec. A ceramic capacitor is normally used.
Sept 29nd, 2014
11
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Figure 3a: Bridge Tied Gate Driver waveforms
The waveforms in Fig. 2a show that:
The lower is LLK, the lower and shorter is the ringing on the Fets gate voltage, particular care must
be paid to guarantee that the max Vgs voltage of the Fet is not exceeded during operation;
The lower is LLK, the shorter is the propagation delay from the driver to the gate of the Fet and the
higher is the peak current into its gate;
The higher is Lm, the lower is ILM; at the primary side the gate peak current, summed to ILM,
constitute the total current flowing out of the gate driver.
Sept 29nd, 2014
12
www.irf.com
© 2014 International Rectifier
AUIRB24427S
3. Driving circuitry design: thermal considerations
The following design example shows how to get a proper design of the gate driving circuitry considering the following
target application data:
Switching frequency 150kHz.
Load capacitance range [10-100] nF.
Supply voltage Vcc=12V.
The switching losses due to the charge/discharge of the capacitive load CL represent the main component of the IC
power dissipation. These losses are proportionally shared between the IC output resistance and the external gate
resistance Rg.
As a consequence the thermal behavior of the IC, with the constraint of a maximum junction temperature equal to
150°C, is one of the key points in dimensioning the system parameters. Figure 3 shows the power that is dissipated
inside the IC as a function of load capacitance CL. The external resistance Rg has been chosen in order to keep the
product RL*Cg as constant and equal to 300ns (refer to Figure 4 for switching circuit schematic).
For a given parameter sizing the value of Pow allows to calculate the junction temperature Tj as:
TJ TA Pow RthJA
(1)
Where TA is the ambient temperature and RthJA is the junction to ambient thermal resistance.
IC dissipated power
0.700
0.600
0.500
0.400
0.300
0.200
0.100
0.000
0
10
20
30
40
50
60
70
80
90
100
C [nF]
Figure 3: Simulated IC power dissipation as a function of load capacitance.
Sept 29nd, 2014
13
www.irf.com
© 2014 International Rectifier
AUIRB24427S
4. Bias and Transient Conditions
The input pins of the IC are protected by ESD events with the circuitry shown into ―Functional block diagram‖
section at par.: Input/Output/Enable Pin Equivalent Circuit Diagrams. This shows that an ESD diode is placed in
between each of these pins and Vcc.
In case Vcc voltage will be lower than one of the voltage applied to these pins the diode will conduct. Because of
its power dissipation the junction temperature will increase. In order to avoid dangerous working conditions it is
recommended to keep the Vcc voltage always higher or equal to the INA/INB/Enable pin voltages; it is remind
that input voltage must respect the defined absolute maximum rating limits.
5. System functionality with improved thermal behavior.
The PSOIC8N package is characterized by a metal thermal pad whose functionality is to reduce the junction to
case thermal resistance. In order to better exploit this feature it is necessary to reduce as much as possible the
thermal pad to PCB thermal resistance (RthTP-PCB in. Fig. 4).
Two possible ways are suggested:
a- Foresee a footprint on layout that allows to solder the thermal pad to the PCB.
b- Use thermal material filling the air gap in between the thermal pad and the PCB.
J
Plastic Case
Rthj-TP
Solder
Paste
TP
Thermal Pad
RthTP-PCB
PCB
PCB
RthPCB-a
Ambient
Figure 4: Steady state equivalent thermal circuit.
6. Square input pulse distortion
The following chapter provides a characterization of pulse width distortion. This is defined as the ratio between
the output pulse width with respect to input pulse width. Characterization is done with no load on OUTA and
OUTB and it is applicable to both INA, INB and EN input pulses.
Fig. 5a and 5b show the output pulse length with respect to input pulse length. In particular, Fig. 5a describes the
pulse distortion in case of a short turn-on input pulse (e.g. low duty cycle condition); while Fig. 5b shows the
pulse distortion in case of a turn-off input pulse (e.g. high duty cycle condition).
Sept 29nd, 2014
14
www.irf.com
© 2014 International Rectifier
AUIRB24427S
250
200
150
100
50
REAL
a
IDEAL
0
0
50
100
150
200
250
Input pulse width [ns]
250
200
150
100
50
REAL
b
IDEAL
0
0
50
100
150
200
250
Input pulse width [ns]
Fig. 5 Output pulse distortion in case of a short turn-on input pulse (a) and turn-off input pulse (b).
Sept 29nd, 2014
15
www.irf.com
© 2014 International Rectifier
AUIRB24427S
7. Bypass capacitor
The bypass capacitor stores an electrical charge that is released to the power line whenever a transient voltage
spike occurs. It provides a low-impedance supply source and it minimizes the noise generated by the switching
of the outputs.
It is recommended to place the bypass capacitor as close as possible to the gate driver in order to improve its
effectiveness by reducing the effect of parasitic inductance of PCB lines.
The value of bypass capacitor is related to:
a- the current that the gate driver has to provide to the OUTA/B loads during turn-on switching condition;
b- the speed at which the output pin is driven;
c- the maximum allowed drop on power supply pins.
For instance, if it considered that outputs OUTA and OUTB provide 6A source current with 20ns rise time and the
maximum wished drop on VCC pin is 0.1V, then the bypass capacitance can be calculated as:
T
V
20ns
0.1V
C n*I
2*6A
2.4F
(1)
Where n is the number of outputs that are switching at the same time. In this case it has been considered that OUTA
and OUTB are driven in phase.
Equation 1 does not contain the information about capacitance ESR that introduces a further drop in the power
supply voltage. As a consequence it is recommended to use low ESR capacitances (e.g. X7R dielectric material).
Additional Details
Figure T1: Input/output Timing Diagram
Sept 29nd, 2014
16
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Figure T2: Switching Time Waveform Definitions
VCC
EN
NC
OUTA
VCC
EN
CBP
Vbatt
IN
IN
+
-
INA
COM
INB
VCC
GND
GND
OUTB
Cgb
Cga
Parameter
TON
Definitio
EN
5V
5V
IN
Turn-on propagation delay
Turn-off propagation delay
Enable Turn-on propagation
delay
Pulse 0V to 5V
Pulse 5V to 0V
5V
TOFF
Pulse 0V to 5V
TON-EN
Enable Turn-off propagation
delay
Pulse 5V to 0V
5V
TOFF-EN
Figure T3: Switching Time Test Circuit and test conditions
Sept 29nd, 2014
17
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Qualification Information
Automotive
(per AEC-Q100)
Qualification Level
Comments: This family of ICs has passed an Automotive
qualification. IR’s Industrial and Consumer qualification level
is granted by extension of the higher Automotive level.
MSL3, 260°C
PSOIC8-N
Moisture Sensitivity Level
(per IPC/JEDEC J-STD-020)
Class M2 (+/-150V)
(per AEC-Q100-003)
Class H2 (+/-2500 V)
(per AEC-Q100-002)
Class C4 (+/-1000 V)
(per AEC-Q100-011)
Class II, Level A
Machine Model
ESD
Human Body Model
Charged Device Model
IC Latch-Up Test
RoHS Compliant
(per AEC-Q100-004)
Yes
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Sept 29nd, 2014
18
www.irf.com
© 2014 International Rectifier
AUIRB24427S
IMPORTANT NOTICE
Unless specifically designated for the automotive market, International Rectifier Corporation and its subsidiaries (IR) reserve the
right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any
time and to discontinue any product or services without notice. Part numbers designated with the ―AU‖ prefix follow automotive
industry and / or customer specific requirements with regards to product discontinuance and process change notification. All
products are sold subject to IR’s terms and conditions of sale supplied at the time of order acknowledgment.
IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with IR’s
standard warranty. Testing and other quality control techniques are used to the extent IR deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
IR assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using IR components. To minimize the risks with customer products and applications, customers should provide
adequate design and operating safeguards.
Reproduction of IR information in IR data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alterations is
an unfair and deceptive business practice. IR is not responsible or liable for such altered documentation. Information of third
parties may be subject to additional restrictions.
Resale of IR products or serviced with statements different from or beyond the parameters stated by IR for that product or service
voids all express and any implied warranties for the associated IR product or service and is an unfair and deceptive business
practice. IR is not responsible or liable for any such statements.
IR products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the
body, or in other applications intended to support or sustain life, or in any other application in which the failure of the IR product
could create a situation where personal injury or death may occur. Should Buyer purchase or use IR products for any such
unintended or unauthorized application, Buyer shall indemnify and hold International Rectifier and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use,
even if such claim alleges that IR was negligent regarding the design or manufacture of the product.
Only products certified as military grade by the Defense Logistics Agency (DLA) of the US Department of Defense, are designed
and manufactured to meet DLA military specifications required by certain military, aerospace or other applications. Buyers
acknowledge and agree that any use of IR products not certified by DLA as military-grade, in applications requiring military grade
products, is solely at the Buyer’s own risk and that they are solely responsible for compliance with all legal and regulatory
requirements in connection with such use.
IR products are neither designed nor intended for use in automotive applications or environments unless the specific IR products
are designated by IR as compliant with ISO/TS 16949 requirements and bear a part number including the designation ―AU‖.
Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, IR will not be
responsible for any failure to meet such requirements.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
101 N. Sepulveda Blvd., El Segundo, California 90245
Tel: (310) 252-7105
Sept 29nd, 2014
19
www.irf.com
© 2014 International Rectifier
AUIRB24427S
Rev
1v7
Description
Updated datasheet parameters according to standard lots test results.
OUTx_x splitted overt
June, 26th 2013
UVLO+ increased the max to 12.6V
Toff increased to 45ns from 40ns
Toff-EN increased to 48ns from 40ns
Introduced VOH/L parameters
Changed Fig. T2.
Added application sections:
1- pulse width distortion
2- Bypass capacitance
1v8
Updated pulse width distortion section based on new R0E silicon.
September, 23rd 2013 Added min VCC in recommended table. Updated Toff delay page 4
Added CBP min in recommended table.
1v9
Nov. 15th
2v0
Updated comments on page 13 and 3
Updated Rdson Max on page 1
Updated Vhys on page 3, removed tube packaging and updated typical applications on
page 1, updated qualification information
Dec 2013
Updated date, added Important Notice page, DR3 version
2v1
Updated Ton & Toff value on page 1, updated Toff limits on page 4
Mar 18th 2014
2v2
Updated Tr & Tf value on page 4. Last DR3 version
Mar 24th 2014
2V3
Updated application sections adding typical and BT-GTD circuits. Updated typical
application list on page 1
Part Marking drawing updated
May 23rd 2014
Sept.29,2104
Sept 29nd, 2014
20
www.irf.com
© 2014 International Rectifier
相关型号：
©2020 ICPDF网 联系我们和版权申明