MK1714-02RTR [IDT]
Clock Generator, 200MHz, CMOS, PDSO20, 0.150 INCH, SSOP-20;
| 型号： | MK1714-02RTR |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 200MHz, CMOS, PDSO20, 0.150 INCH, SSOP-20 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总8页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
SPREAD SPECTRUM MULTIPLIER CLOCK
MK1714-02
Description
Features
The MK1714-02 is a low cost, high performance clock
synthesizer with selectable multipliers and percentages of
spread designed to generate high frequency clocks with low
EMI. Using analog/digital Phase Locked Loop (PLL)
techniques, the device accepts an inexpensive,
fundamental mode, parallel resonant crystal or clock input
to produce a spread or dithered output. This reduces the
EMI amplitude peaks at the odd harmonics by several dB.
The OE pin puts both outputs into a high impedance state
for board level testing. The PD pin powers down the entire
chip and the outputs are held low.
• Packaged in 20-pin tiny SSOP
• Available in Pb (lead) free package
• Operating voltage of 3.3 V or 5 V
• Multiplier modes of x1, x2, x3, x4, x5, and x6
• Inexpensive 10 - 25 MHz crystal or clock input
• OE pin tri-states the outputs for board testing
• Power down pin stops the outputs low
• Selectable frequency spread
• Spread can be turned on or off
• Advanced, low power CMOS process
• Duty cycle of 40/60
• Industrial temperature range available
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
VDD
2
5
S4:0
PD
PLL Clock
Multiplier and
Low EMI Enable
Spread
Spectrum
Circuitry
Clock Out
X1
Input
Crystal
Crystal or
Oscillator
REF
Clock
X2
4
OE (both outputs)
XSEL
GND
IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK
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Pin Assignment
X2
X1/ICLK
VDD
VDD
S4
1
20
19
18
17
16
15
14
13
12
11
REF
OE
2
3
PD
4
GND
S0
5
S3
6
NC
GND
GND
S2
7
S1
8
GND
LEE
XSEL
9
CLK
10
20 pin (150 mil) SSOP (QSOP)
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number Name
Type
1
2
3
4
5
X2
X1
XO
XI
Crystal connection. Connect to parallel mode crystal. Leave open for clock.
Crystal connection. Connect to parallel mode crystal or clock.
VDD
VDD
S4
Power Connect to VDD. Must be same value as other VDD.
Power Connect to VDD. Must be same value as other VDD.
Input Select pin 4. Determines multiplier and spread amount per table on following page. Internal
pull-down.
6
S3
Input Select pin 3. Determines multiplier and spread amount per table on following page. Internal
pull-up.
7
8
9
GND
GND
S2
Power Connect to ground.
Power Connect to ground.
Input Select pin 2. Determines multiplier and spread amount per table on following page. Internal
pull-up.
10
11
12
13
14
CLK
XSEL
LEE
GND
S1
Output Clock output dependent on input, multiplier, and spread amount per table on following page.
Input Connect to VDD for crystal input, or GND for CLK input. Internal pull-down.
Input Low EMI Enable. Turns on spread spectrum on CLK when high. Internal pull-up.
Power Connect to ground.
Input Select pin 1. Determines multiplier and spread amount per table on following page. Internal
pull-up.
17
18
GND
PD
Power Connect to ground.
Input Power down. Turns off chip when low. Outputs stop low. Leave open or connected to VDD if
power down is not required.
19
20
OE
Input Output enable. Tri-states all outputs when low. Internal pull-up.
REF
Output Reference clock output from crystal oscillator. This clock is not spread.
Note: When changing the input frequency, the LEE pin must be set low for minimum of 10µs to allow the PLL to lock to the
new frequency. Alternatively, the PD pin may be set low while changing frequencies.
IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK
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Clock Output Select Table (MHz)
S4 S3 S2 S1 S0
Input Range
40 - 80
60 - 120
40 - 80
80 - 150
10 - 30
20 - 60
10 - 25
20 - 60
20 - 30
40 - 75
40 - 100
40 - 75
20 - 40
20 - 60
10 - 20
10 - 30
20 - 37.5
20 - 40
10 - 30
20 - 30
5 - 20
Multiplier
x1
x1
Output Range
40 - 80
Direction
C
Amount (%)
±0.75
3.3/5V
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
3.3V
Both
Both
Both
Both
Both
Both
Both
3.3V
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
60 -120
40 - 80
DC
C
+0.25, -0.75
±1.25
x1
x1
80 - 150
20 - 60
C
±0.75
x2
x2
x2
x2
x3
x2
x1
C
±0.75
40 - 120
20 - 50
C
±0.5
DC
DC
C
+0.25, -1.5
+0.5, -1
±0.5
40 - 120
60 - 90
80 - 150
40 - 100
80 - 150
20 - 40
C
±0.75
DC
DC
DC
DC
DC
DC
DC
DC
C
+0.25, -1.5
+0.25, -1.5
+0.5, -2.0
+0.25, -1.5
+0.5, -2.0
+0.25, -1.5
+0.25, -1.25
+0.25, -1.5
±0.75
x2
x1
x1
x1
x1
x4
x3
x1
x1
x2
x3
x4
20 - 60
10 - 20
10 - 30
80 - 150
60 - 120
10 - 30
20 - 30
D
-0.5
10 - 40
DC
D
+0.25, -2.25
-0.25, -2.25
±0.75
20 - 50
20 - 37.5
80 - 150
10 - 25
10 - 20
10 - 20
20 - 50
10 - 25
10 - 20
10 - 20
10 - 30
60 - 150
80 - 150
80 - 150
40 - 100
50 - 100
60 - 120
20 - 50
C
x1
DC
C
+0.25, -1.25
±0.75
x4
x5
x6
x1
x4
x5
x6
x1
C
±0.75
C
±0.75
C
±0.75
40 - 100
50 - 100
60 - 120
10 - 30
DC
DC
D
+0.25, -1.5
+0.25, -1.25
-1.5
C
±0.75
For S4:S0, 0 = connect to GND, 1 = connect to VDD.
Direction: C = center spread, D = down spread, DC = down + center spread. Amount = spread amount. For example, for a 40 MHz output
clock spread down 1%, the lowest frequency is 39.60 MHz.
Contact IDT with your exact output frequency for details on spread direction and amount.
IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK
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the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
External Components
The MK1714-02 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI the 33Ω series termination resistor, if
needed, should be placed close to the clock output.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ωresistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the MK1714-02. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
Crystal Tuning Load Capacitors
Crystal Load Capacitors
Powerup Considerations
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) been the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
To insure proper operation of the spread spectrum
generation circuit, some precautions must be taken in the
implementation of the MK1714-02.
1) An input signal should not be applied to ICLK until VDD
is stable (within 10% of its final value). This requirement can
be easily met by operating the MK1714-02 and the ICLK
source from the same power supply.
2) LEE should not be enabled (taken high) until after the
power supplies and input clock are stable. This requirement
can be met by direct control of LEE by system logic; for
example, a “power good” signal. Another solution is to leave
LEE unconnected to anything but a 0.01µF capacitor to
ground. The pull-up resistor on LEE will charge the
capacitor and provide approximately a 700µs delay until
spread spectrum is enabled.
The value (in pF) of these crystal caps should equal
(C -6)*2. In this equation, C = crystal load capacitance in
L
L
pF. Example: For a crystal with a 16 pF load capacitance,
each crystal capacitor would be
[16 - 6]*2 = 20 pF.
PCB Layout Recommendations
3) If the input frequency is changed during operation,
disable spread spectrum until the input clock stabilizes at
the new frequency.
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1714-02. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7V
-0.5V to VDD+0.5V
-40 to +85° C
-65 to +150° C
175°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
° C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.0
+5.5
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V or 5 V, Ambient Temperature -40 to +85° C
Parameter
Symbol
VDD
Conditions
Min.
Typ.
Max. Units
Operating Voltage
3.0
5.5
V
mA
mA
V
Supply Current
IDD
No load, at 3.3 V
26
40
IDD
No load, at 5 V
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
V
Select inputs, OE, PD
Select inputs, OE, PD
2
IH
V
0.8
0.4
V
IL
V
I
I
= -8 mA
= 8 mA
VDD-0.4
V
OH
OH
OL
V
V
OL
I
Each output
Except X1
50
mA
kΩ
OS
On Chip Pull-up Resistor,
inputs
R
500
PU
On-Chip Pull-down Resistor,
outputs
R
S4 pin only
500
7
kΩ
PD
Input Capacitance
Except X1, X2
pF
IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK
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AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V or 5 V, Ambient Temperature -40 to +85° C
Parameter
Input Crystal Frequency
Input Clock Frequency
Output Rise Time
Symbol
Conditions
Min.
10
Typ. Max. Units
25
150
1.5
1.5
MHz
MHz
ns
10
t
0.8 to 2.0 V
OR
Output Fall Time
t
2.0 to 0.8 V
CLK
ns
OF
One Sigma Jitter
40
ps
Absolute Jitter
CLK
160
50
Output Clock Duty Cycle
Output Frequency
at VDD/2
40
2
60
%
200
MHz
ppm
Output Frequency Synthesis
Error
1
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
135
93
° C/W
° C/W
° C/W
° C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
78
Thermal Resistance Junction to Case
60
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Package Outline and Package Dimensions (20 pin SSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
20
Millimeters
Inches
Min
Symbol
Min
1.35
0.10
--
Max
1.75
0.25
1.50
0.30
0.25
8.75
6.20
4.00
Max
.069
.010
.059
A
A1
A2
b
.053
.0040
--
E1
E
INDEX
AREA
0.20
0.18
8.55
5.80
3.80
0.008
.007
.337
.228
.150
0.012
.010
.344
.244
.157
C
D
E
1
2
E1
e
D
0.635 Basic
0.025 Basic
L
0.40
1.27
.016
.050
α
0°
8°
0°
8°
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
-40 to 85 °C
-40 to 85 °C
0 to +70° C
0 to +70° C
-40 to 85 °C
-40 to 85 °C
MK1714-02R*
MK1714-01RTR*
MK1714-02RI*
MK1714-02RITR*
MK1714-02RLF
MK1714-01RLFTR
MK1714-02RILF
MK1714-02RILFTR
MK1714-02R
MK1714-02R
MK1714-02RI
MK1714-02RI
MK1714-02RL
MK1714-02RL
MK171402RIL
MK171402RIL
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
*NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK
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MK1714-02
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SSCG
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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