MK1716-01RLFT [IDT]
Clock Generator, 133.33MHz, CMOS, PDSO28, 0.150 INCH, LEAD FREE, SSOP-28;
| 型号： | MK1716-01RLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 133.33MHz, CMOS, PDSO28, 0.150 INCH, LEAD FREE, SSOP-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总8页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MK1716-01
SERIAL PROGRAMMABLE CLOCK WITH SPREAD SPECTRUM
Description
Features
The MK1716-01 is a versatile serial programmable
clock source which takes up very little board space.
• Packaged in 28-pin SSOP
• Operating voltage 3.3 V
The device can simultaneously generate two groups of
4 output clocks and a reference clock output. Both
clock groups (CLKA and CLKB) are derived from a
single PLL, and have the ability to incorporate Spread
Spectrum frequency modulation for reduced system
EMI. Each group has control of independent PLL
output divide values. Outputs may be programmed on
the fly, and will lock to a new frequency in 10 ms or less.
• Serially programmable: user determines the output
frequency via a 3-wire interface
• Highly accurate frequency generation
•M/N Multiplier PLL: M = 1..2048, N = 1..1024
• Eliminates the need for custom Quartz Oscillators
• Input crystal frequency of 5-27 MHz
• Optional programmable on-chip crystal capacitors
• Output clock frequencies of 250 kHz to 133.33 MHz
Each of the two groups are powered by a separate
VDDIO voltage. The reference clock uses the fixed
VDD voltage. VDDIO may vary from 2.5 V to VDD.
• Spread Spectrum frequency modulation for reduced
system EMI
The devices includes a OE pin which tri-states the
output clocks and when tied low.
•Center or down spread 0.5% min to 4% total
•Selectable 32 kHz and 120 kHz modulation rate
• Advanced, low power, sub-micron CMOS process
• Separate VDD ‘s for each bank of 4 outputs
•Output skew <250 ps within output bank
• OE control on outputs
TM
ICS’ VersaClock software allows the user to
generate MK1716-01 device optimizing configuration
code for target output frequencies and spread
spectrum amounts.
Block Diagram
VDD
4
VDDIOA
DIV A
CLKA
STROBE
PLL
with
Spread
SCLK
DATA
4
VDDIOB
SpectrumCircuit
DIV B
CLKB
Crystal or
clock input
4
X1/ICLK
X2
Clock
Buffer/
Crystal
Ocsillator
REF OUT
External capacitors are
required with a crystal input.
6
GND
OE
MDS 1716-01 D
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Revision 051504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1716-01
SERIAL PROGRAMMABLE CLOCK WITH SPREAD SPECTRUM
Pin Assignment
Note:
DATA
X2
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
Clock A and Clock B can be at the same frequency or
not, but must be powered by separate VDDs.
2
STROBE
SCLK
OE
X1/ICLK
REFOUT
VDD
3
4
5
VDD
VDD
6
VDD
GND
7
VDD
GND
8
GND
GND
CLKB
CLKB
CLKB
9
GND
10
11
12
13
14
CLKA
CLKA
CLKA
CLKA
CLKB
VDDIOB
VDDIOA
Pin Descriptions
Pin
Number
Pin
Name
Pin
Pin Description
Type
Input
XO
1
2
DATA
X2
Serial shift register data input.
Connect to crystal. Leave open for clock input.
3
X1/ICLK
REFOUT
VDD
XI
Connect this pin to a crystal or external clock input.
4
Output Reference clock output.
5-6
7-9
10-13
14
P
P
Connect to +3.3 V.
Connect to ground.
GND
CLKA
Output Output clock.
VDDIOA
VDDIOB
CLKB
P
P
Power supply to CLKA.
Power supply to CLKB.
15
16-19
20-21
22-24
25
Output Output clock.
GND
P
Connect to ground.
VDD
P
Connect to +3.3 V.
OE
Input
Input
Input
Output enable active high.
Serial shift register clock.
26
SRCLK
STROBE
27
Strobe to load data. See timing diagram. Use external 250 kOhm
pull-up.
28
GND
Input
Connect to ground.
MDS 1716-01 D
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Revision 051504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1716-01
SERIAL PROGRAMMABLE CLOCK WITH SPREAD SPECTRUM
Configuring the MK1716-01
Initial State: The MK1716-01 may be configured to have up to nine frequency outputs, utilizing a single PLL
and on-board spread spectrum circuitry. Unprogrammed, the part has the following outputs, related to the
reference input clock:
Default Outputs
Output
Frequency
Clock 1-9 (Pins 4, 10 - 19)
Reference output
The STROBE pin must have an external 250 kOhm pull-up resistor to acheive the Initial State.
The input crystal range for the MK1716-01 is 5 MHz to 27 MHz.
The MK1716-01 can be programmed to set the output functions and frequencies. 160 data bits generated
TM
by the VersaClock software are written in DATA pin in this order: MSB (left most bit) first.
As show in Figure 2, after these 160 bits are clocked into the MK1716-01, taking STROBE high will send
this data to the internal latch and the CLK output will lock within 10 ms.
Note: STROBE utilizes a transparent latch that is latched when in the high state. If STROBE is in the high
state and SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will
change accordingly. Although this will not damage the MK1716-01, it is recommended that STROBE be
kept low while DATA is being clocked into the MK1716-01 in order to avoid unintended changes on the
output clocks.
AC Parameters for Writing to the MK1716-01
Parameter
Condition
Setup time
Min.
10
Max.
Units
ns
t
SETUP
t
Hold time after SCLK
Data wait time
10
ns
HOLD
t
10
ns
W
t
Strobe pulse width
SCLK Frequency
40
ns
S
30
MHz
DATA
tsetup
Bit160 Bit159 Bit158
Bit3
Bit2
Bit1
thold
SCLK
tw
ts
STROBE
Figure 2. Timing Diagram for Programming the MK1716-01
MDS 1716-01 D
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Revision 051504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1716-01
SERIAL PROGRAMMABLE CLOCK WITH SPREAD SPECTRUM
External Components
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to each clock
output.
STROBE Pull-up Resistor
In order for the device to start up in the default state, a
250 kOhm pull-up resistor is required.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
MK1716-01 must be isolated from system power
supply noise to perform optimally.
MK1716-01 Configuration Capabilities
The architecture of the MK1716-01 allows the user to
easily configure the device to a wide range of output
frequencies, for a given input reference frequency.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 2048 and N = 1 to 1024.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The MK1716-01 also provides separate output divide
values, from 2 through 20, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Each output frequency can be represented as:
Output Freq. = (Ref. Freq)*(M/N)/Output Divide
Each output clock bank has an separate voltage drive
control pin (VDDIOA and VDDIOB) that sets the output
clock voltage swing.
The value (in pF) of these crystal caps should equal
(C -6 pF)*2. In this equation, C = crystal load
L
L
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
ICS VersaClock Software
ICS applies years of PLL optimization experience into a
user friendly software that accepts the user’s target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
MDS 1716-01 D
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Revision 051504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1716-01
SERIAL PROGRAMMABLE CLOCK WITH SPREAD SPECTRUM
target output frequencies. The user may evaluate
spread should be applied. In this case, the maximum
output accuracy, performance trade-off scenarios in
seconds.
frequency, including modulation, is the target
frequency. The effective average frequency is less than
the target frequency.
Spread Spectrum Modulation
The MK1716-01 operates in both center spread and
down spread modes. For center spread, the frequency
can be modulated between 0.125% to 2.0%. For
down spread, the frequency can be modulated
between -0.25% to -4.0%.
The MK1716-01 utilizes frequency modulation (FM) to
distribute energy over a range of frequencies. By
modulating the output clock frequencies, the device
effectively lowers energy across a broader range of
frequencies; thus, lowering a system’s
electro-magnetic interference (EMI). The modulation
rate is the time from transitioning from a minimum
frequency to a maximum frequency and then back to
the minimum.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates,
if a common VCO frequency can be identified.
Spread Spectrum Modulation Rate
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is
equal in the positive and negative directions. The
effective average frequency is equal to the target
frequency. In applications where the clock is driving a
component with a maximum frequency rating, down
The spread spectrum modulation frequency applied to
the output clock frequency may occur at a variety of
rates. For applications requiring the driving of
“down-circuit” PLLs, Zero Delay Buffers, or those
adhering to PCI standards, the spread spectrum
modulation rate should be set to 30-33 kHz. For other
applications, a 120 kHz modulation option is available.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1716-01. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Parameter
Condition
Min.
Typ.
Max.
7
Units
V
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
VDD + 0.5
VDD + 0.5
150
V
Clock Outputs
V
Storage Temperature
Soldering Temperature
°C
°C
Max 10 seconds
260
MDS 1716-01 D
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Revision 051504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1716-01
SERIAL PROGRAMMABLE CLOCK WITH SPREAD SPECTRUM
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
+70
+3.6
4
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
+3.0
V
ms
DC Electrical Characteristics
VDD=3.3 V 10% Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.00
3.60
V
Configuration Dependent
See VersaClock
mA
TM
Operating Supply Current
Input High Voltage
Ex. 14.31818 MHz crystal,
VDD=VDDIO=3.3V,
OE = 0
55
15
mA
mA
IDD
VDDIO Voltage
VDDIOA and VDDIOB
ICLK only
2.25
VDD
(VDD/2)-1
0.8
V
V
V
V
V
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
V
(VDD/2)+1
IH
V
ICLK only
IL
V
VDD-0.5
IH
V
OE, SCLK, DATA,
STROBE
IL
Output High Voltage
Output Low Voltage
V
I
I
I
= -8 mA
= 8 mA
= -4 mA
2.4
V
V
V
OH
OH
OL
OH
V
0.4
OL
Output High Voltage,
CMOS level
V
VDD-0.4
OH
Short Circuit Current
CLK outputs
+70
20
mA
Nominal Output
Impedance
Z
Ω
OUT
Input Capacitance
C
OE pin
4
pF
IN
Internal Pull-down
Resistor
R
CLK outputs
510
kΩ
PD
Internal Pull-up Resistor
R
OE pin
240
kΩ
PU
MDS 1716-01 D
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Revision 051504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1716-01
SERIAL PROGRAMMABLE CLOCK WITH SPREAD SPECTRUM
AC Electrical Characteristics
VDD = 3.3 V 10%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
F
Fundamental crystal
5
27
MHz
IN
Input clock
VDD=3.3 V
2
50
MHz
MHz
Output Frequency
0.25
133.33
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Power-up Time
t
20% to 80%, Note 1
80% to 20%, Note 1
Note 2
0.8
0.8
ns
ns
%
OR
t
OF
40
49-51
3
60
10
STROBE goes high until
stable CLK out
ms
OE goes high until
stable CLK out, PLL
already running
50
ns
Maximum Output Jitter,
short term
t
t
Reference clock, Note 1
300
200
150
150
ps
ps
ps
ps
%
j
Maximum Output Jitter,
short term
All other clocks, Note 1
configuration dependent
j
Skew on the same bank
Same voltage and
frequency
Skew bank to bank
Same voltage and
frequency
Spread Spectrum
Center or down spread
0.5
4.0
Modulation Amount
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
135
93
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
78
Thermal Resistance Junction to Case
θ
60
MDS 1716-01 D
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Revision 051504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1716-01
SERIAL PROGRAMMABLE CLOCK WITH SPREAD SPECTRUM
Package Outline and Package Dimensions (28-pin SSOP, 150 Mil. Wide Body)
Package dimensions are kept current with JEDEC Publication No. 95
28
Millimeters
Inches
Symbol
Min
Max
1.75
0.25
1.50
0.30
0.25
10.00
6.20
4.00
Min
Max
A
A1
A2
b
1.35
0.10
--
0.20
0.18
9.80
5.80
3.80
0.053
0.004
--
0.008
0.007
.386
0.069
0.010
0.059
0.012
0.010
.394
E1
E
INDEX
AREA
c
D
E
0.228
0.150
0.244
0.157
1
2
E1
e
.635 Basic
.025 Basic
D
L
0.40
0°
1.27
8°
0.016
0°
0.050
8°
α
aaa
--
0.10
--
0.004
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
Ordering Information
Part / Order Number
Marking
MK1716-01R (top line)
YYWW (2nd line)
Shipping Packaging
Tubes
Package
28-pin SSOP
28-pin SSOP
Temperature
0 to +70° C
0 to +70° C
MK1716-01R
MK1716R-01RT
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 1716-01 D
8
Revision 051504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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