MK1725GLF [ICSI]
Quad Output Spread Spectrum Clock Generator; 四路输出扩频时钟发生器
| 型号： | MK1725GLF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Quad Output Spread Spectrum Clock Generator |
| 文件： | 总6页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MK1725
Quad Output Spread Spectrum Clock Generator
Description
Features
The MK1725 generates 4 high-quality, high-frequency
spread spectrum clock outputs. It is designed to
replace spread spectrum clock generators and a buffer
in many digital consumer applications. Using ICS’
patented Phase Locked Loop (PLL) techniques, the
device runs from a lower frequency clock or crystal
input.
• Packaged in 16-pin TSSOP
• Available in Pb (lead) free package
• Replaces a spread spectrum clock generator and a
buffer
• Input clock or crystal frequency of 20-34 MHz
• Output frequency of 20-136 MHz
• Four spread spectrum clock outputs
• Duty cycle of 45/55
• Operating voltage of 3.3 V
• Advanced, low power CMOS process
The MK1725 has a 16 location ROM table which
provides maximum flexibility for system designers. The
chip also has a power down pin which can be used to
reduce power.
Block Diagram
VDD
3
4
S3:0
PLL/Clock
Synthesis
4
and
CLK1:4
Spread
Spectrum
Circuitry
X1/ICLK
20-34 MHz
crystal or
clock
Crystal
Oscillator
X2
Optional crystal
capacitors.
3
GND
PDTS
MDS 1725 C
1
Revision 021605
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●www.icst.com
MK1725
Quad Output Spread Spectrum Clock Generator
Pin Assignment
CLK Output Selection Table
S3
S2
S1
S0
CLK1:4
Spread %
X1
S0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
Multiplier
VDD
PDTS
S2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
1
0
1
0
1
1
0
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
1
-1%
-0.5%
1
S3
1
+/- 0.5%
+/- 0.25%
-1%
VDD
GND
S1
1
VDD
GND
CLK4
CLK3
2
2
-0.5%
CLK1
CLK2
2
+/- 0.5%
+/- 0.25%
-1%
2
16 pin (173 mil) TSSOP
4
4
-0.5%
4
+/- 0.5%
+/- 0.25%
OFF
4
1
2
OFF
4
OFF
TEST
TEST
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
Connect to a 20 - 34 MHz crystal or clock input.
1
2
X1
S0
Input
Input
Select pin 0. Determines frequency and spread amount on
output clocks as per table above. Internal pull-down.
3
S3
Input
Select pin 3. Determines frequency and spread amount on
output clocks as per table above. Internal pull-down.
4
5
6
VDD
GND
S1
Power Connect to +3.3V.
Power Connect to ground.
Input
Select pin 1. Determines frequency and spread amount on
output clocks as per table above. Internal pull-down.
7
8
9
CLK1
CLK2
CLK3
Output Clock 1 output. Frequency and spread amount are determined
by table above. Weak internal pull-down when tri-state.
Output Clock 2 output. Frequency and spread amount are determined
by table above. Weak internal pull-down when tri-state.
Output Clock 3 output. Frequency and spread amount are determined
by table above. Weak internal pull-down when tri-state.
MDS 1725 C
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Revision 021605
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●www.icst.com
MK1725
Quad Output Spread Spectrum Clock Generator
Pin
Number
Pin
Name
Pin
Type
Pin Description
10
CLK4
Output Clock 4 output. Frequency and spread amount are determined
by table above. Weak internal pull-down when tri-state.
11
12
13
GND
VDD
S2
Power Connect to ground.
Power Connect to +3.3V.
Input
Select pin 2. Determines frequency and spread amount on
output clocks as per table above. Internal pull-down.
14
Power Down Tri-state. Powers down entire chip and tri-states
outputs when low. Internal pull-up resistor.
PDTS
Input
15
16
VDD
X2
Power Connect to +3.3V.
Input 20MHz-34MHz crystal input. Float for clock input.
External Components
capacitance, each crystal capacitor would be 24 pF
[(18-6) x 2] = 24.
Decoupling Capacitor
As with any high performance mixed-signal IC, the
MK1725 must be isolated from system power supply
noise to perform optimally.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
3) To minimize EMI the 33Ω series termination resistor
(if needed) should be placed close to the clock outputs.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the MK1725. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
The value (in pF) of these crystal caps should equal
(CL -6)*2. In this equation, CL= crystal load capacitance
in pF. Example: For a crystal with an 18 pF load
MDS 1725 C
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Revision 021605
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●www.icst.com
MK1725
Quad Output Spread Spectrum Clock Generator
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1725. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
5 V
-0.5 V to VDD+0.5 V
0 to +70°C
-65 to +150°C
125°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature
0
Power Supply Voltage (measured in respect to GND)
+3.135
+3.3
+3.465
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70°C
Parameter
Operating Voltage
Symbol
VDD
IDD
VIH
Conditions
Min.
Typ.
3.3
Max. Units
3.135
3.465
V
mA
V
Supply Current
20M in S3:0=[0100]
Input selects
Input selects
ICLK
22
Input High Voltage
2
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
VDD/2+1
V
Input Low Voltage
VIL
ICLK
VDD/2-1
V
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance
VOH
VOH
VOL
IOS
IOH = -4 mA
IOH = -12 mA
IOL = 12 mA
Clock outputs
VDD-0.4
2.4
V
V
0.4
V
70
5
mA
pF
Ω
CIN
Nominal Output Impedance
Internal Pull-up Resistor
Internal Pull-down Resistor
ZOUT
RPU
RPD
20
PDTS pin
360
510
kΩ
kΩ
Clock outputs; S3:0
MDS 1725 C
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Revision 021605
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●www.icst.com
MK1725
Quad Output Spread Spectrum Clock Generator
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.0 V 5%, Ambient Temperature 0 to +70°C
Parameter
Input Frequency
Symbol
fIN
Conditions
Crystal or clock input
20% to 80%, Note 1
80% to 20%, Note 1
Min.
Typ. Max. Units
20
34
MHz
ns
Output Rise Time
tOR
1.2
1.0
50
Output Fall Time
tOF
ns
Output Clock Duty Cycle
At VDD/2, Note 1
1X, 2X modes
45
40
55
60
%
at VDD/2, Note 1
4X mode
50
%
Absolute Clock Period Jitter
Modulation Frequency
Output to Output Skew
Output Enable Time
tJ
Cycle to cycle, Note 1
150
ps
kHz
ps
fmod
25
50
Non-spread modes
250
tOE
tOD
PDTS high to output
spread profile stable
2.6
10
ms
Output Disable Time
PDTS low to tri-state
ns
Note 1: Measured with a 15 pF load.
Thermal Characteristics
Parameter
Symbol
Conditions
Still air
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
78
70
68
37
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Marking Diagram
16
9
MK1725GL
######
YYWW
1
8
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year and the week number that the part was assembled.
3. “L” denotes Pb (lead) free package.
4. Bottom marking: (origin). Origin = country of origin of not USA.
MDS 1725 C
5
Revision 021605
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●www.icst.com
MK1725
Quad Output Spread Spectrum Clock Generator
Package Outline and Package Dimensions (16 pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches
Max
16
Symbol
Min
--
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
C
D
E
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
6.40 BASIC
4.30 4.50
0.65 Basic
1
2
E1
e
L
D
0.45
0°
0.75
8°
0.018
0°
0.030
8°
α
aaa
--
0.10
--
0.004
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
Ordering Information
Part / Order Number
Marking
see page 5
Shipping Packaging
Tubes
Package
16-pin TSSOP
Temperature
0 to +70 °C
MK1725GLF
MK1725GLFT
Tape and Reel
16-pin TSSOP
0 to +70 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit
Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of
third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice.
ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 1725 C
6
Revision 021605
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●www.icst.com
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