IDTIDT71P79804250BQ [IDT]
18Mb Pipelined DDR⑩II SIO SRAM Burst of 2; 18MB流水线DDR⑩II SIO SRAM突发的2
| 型号： | IDTIDT71P79804250BQ |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
| 文件： | 总23页 (文件大小：629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71P79204
IDT71P79104
IDT71P79804
IDT71P79604
18Mb Pipelined
DDR™II SIO SRAM
Burst of 2
Description
Features
◆ 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)
◆ Separate, Independent Read and Write Data Ports
- Supports concurrent transactions
The IDT DDRIITM Burst of two SIO SRAMs are high-speed syn-
chronous memories with independent, double-data-rate (DDR), read
and write data ports with two data items passed with each read or write.
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the DDRII SIO are unidirectional and can be optimized
for signal integrity at very high bus speeds. Memory bandwidth is higher
than DDR SRAM with bi-directional data buses as separate read and
write ports eliminate bus turn around cycle. Separate read and write
ports also enable easy depth expansion. Each port can be selected
independantly with a R/W input shared among all SRAMs and provide
a new LD load control signal for each bank. The DDRII SIO has scal-
able output impedance on its data output bus and echo clocks, allowing
the user to tune the bus for low noise and high performance.
◆ Dual Echo Clock Output
◆ 2-Word Burst on all SRAM accesses
◆ MultiplexedAddress Bus
- One Read or one Write request per clock cycle
◆ DDR (Double Data Rate) Data Bus
- Two word burst data per clock
◆ Depth expansion through Control Logic
◆ HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V
to 1.9V.
◆ Scalable output drivers
- Can drive HSTL, 1.8V TTLor any voltage level from 1.4V to 1.9V.
- Output Impedance adjustable from 35 ohms to 70 ohms
◆ 1.8V Core Voltage (VDD)
◆ 165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package
◆ JTAG Interface
The DDRII SIO has a single SDR address bus with multiplexed
read and write addresses. The read/write and load control inputs are
received on the first half of the clock cycle. The byte and nibble write
signals are received on both halves of the clock cycle simultaneously
with the data they are controlling on the data input bus.
The DDRII SIO has echo clocks, which provide the user with a
clock that is precisely timed to the data output, and tuned with matching
impedance and signal quality. The user can use the echo clock for
downstream clocking of the data. Echo clocks eliminate the need for the
user to produce alternate clocks with precise timing, positioning, and
signal qualities to guarantee data capture. Since the echo clocks are
Functional Block Diagram
(Note1)
DATA
REG
DATA
REG
(Note1)
D
WRITE DRIVER
(Note2)
(Note3)
ADD
REG
(Note2)
SA
(Note4)
(Note4)
(Note1)
18M
MEMORY
ARRAY
Q
LD
R/W
BWx
CTRL
LOGIC
K
CLK
GEN
CQ
K
CQ
C
SELECT OUTPUT CONTROL
C
6432 drw 16
Notes:
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
NOVEMBER 2005
1
©2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
DSC-6432/01
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
generated by the same source that drives the data output, the relation- the correlation of the rising and falling edges of the echo clock and will
ship to the data is not significantly affected by voltage, temperature and improve the duty cycle of the individual signals.
process, as would be the case if the clock were generated by an outside
source.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within the
tolerances designated.
All interfaces of the DDR II SIO are HSTL, allowing speeds beyond
SRAM devices that use any form of TTL interface. The interface can be
scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if
necessary. The device has a VDDQ and a separate Vref, allowing the
user to designate the interface operational voltage, independent of the
device core voltage of 1.8V VDD. The output impedance control allows
the user to adjust the drive strength to adapt to a wide range of loads and
transmission lines.
Read and Write Operations
DDRII SIO devices internally store the two words of the burst as a
single wide word and the words will retain their burst order. There is no
ability to address an individual word level in a burst, as is possible in the
DDRII common I/O devices. The byte and nibble write signals can be
used to prevent writing to any individual bytes, or combined to prevent
writing word(s) of the burst.
Read operations are initiated by holding Read/Write control input
(R/W) high, the load control input (LD) low and presenting the read
address to the address port during the rising edge of K, which will latch
the address. The data will then be read and will appear at the device
output at the designated time in correspondence with the C andC clocks.
Write operations are initiated by holding the Read/Write control input
(R/W) low, the load control input (LD) low and presenting the write
address to the address port during the rising edge of K, which will latch
the address. On the following rising edge of K, the first word of the two
word burst must be present on the data input bus DQ[x:O], along with the
appropriate byte write or nibble write (BWx or NWx) inputs. On the
following rising edge of K, the second half of the data write burst will be
accepted at the device input with the designated (BWx orNWx) inputs.
Clocking
The DDRII SIO SRAM has two sets of input clocks, namely the K,
K clocks and the C, C clocks. In addition, the DDRII SIO has an output
“echo” clock, CQ, CQ.
The K and K clocks are the primary device input clocks. The K
clock is, used to clock in the control signals (LD, R/W andBWx orNWx),
the address, and the first word of the data burst during a write operation.
The K clock is used to clock in the control signals (BWx orNWx) and the
second word of the data burst during a write operation. The K and K
clocks are also used internally by the SRAM. In the event that the user
disables the C andC clocks, the K andK clocks will also be used to clock
the data out of the output register and generate the echo clocks.
The C andC clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C must be presented to the SRAM within the timing tolerances. The
output data from the DDRII SIO will be closely aligned to the C and C
input, through the use of an internal DLL. When C is presented to the
DDRII SIO SRAM, the DLL will have already internally clocked the data
to arrive at the device output simultaneously with the arrival of the C
Output Enables
TheDDRIISIOSRAMautomaticallyenablesanddisablestheQ[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the Q outputs will come up in a high impedance
clock. The C and second data item of the burst will also correspond.
state.
Single Clock Mode
The DDRII SIO SRAM may be operated with a single clock pair. C
and C may be disabled by tying both signals high, forcing the outputs
and echo clocks to be controlled instead by the K and K clocks.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive imped-
ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to VDDQ.
DLL Operation
The DLL in the output structure of the DDRII SIO SRAM can be
used to closely align the incoming clocks C and C with the output of the
data, generating very tight tolerances between the two. The user may
disable the DLLby holding Doff low. With the DLLoff, the C and C (or
K and K if C and C are not used)will directly clock the output register of
the SRAM. With the DLL off, there will be a propagation delay from the
time the clock enters the device until the data appears at the output.
Echo Clock
The echo clocks, CQ andCQ, are generated by the C and C clocks
(or K, K if C, C are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of CQ. The rising edge ofC generates
the rising edge of CQ and the falling edge of CQ. This scheme improves
6.242
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Definitions
Symbol
Pin Function
Description
Data input signals, sampled on the rising edge of K and K clocks during valid write operations
2M x 8 -- D[7:0]
2M x 9 -- D[8:0]
1M x 18 -- D[17:0]
512K x 36 -- D[35:0]
Input
Synchronous
D[X:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising
edge of K clocks during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on the same
edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and
Input
BW
BW
0
, BW
1
Synchronous not written in to the device.
controls DQ[8:0]
controls DQ[8:0] and BW
controls DQ[8:0], BW
2, BW
3
2M x 9 -- BW
0
1M x 18 -- BW
0
1
controls DQ[17:9]
512K x 36 -- BW
0
1
controls DQ[17:9], BW
2
controls DQ[26:18] and BW3 controls DQ[35:27]
Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects.
Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is written
into the device during the current portion of the write operations. Nibbles not written remain unaltered. All the
Input
NW0 NW1
Synchronous nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the
corresponding nibble of data to be ignored and not written in to the device.
2M x 8--NW0 controls D[3:0] and NW1 controls D[7:4]
Input
SA
Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on
Output
Q[X:0]
the rising edge of both the C and C clocks during Read operations or K and K when operating in single clock
Synchronous
mode. When the Read port is deselect ed, Q[X:0] are automatically three-stated.
Load Control Logic. Sampled on the rising edge of K. If LD is low, a two word burst read or write operation will
Input
Synchronous
be initiated as designated by the R/W input. If LD is high during the rising edge of K, operations in progress will
LD
R/W
C
complete, but new operations will not be initiated.
Read or Write Control Logic. If LD is low during the rising edge of K, the R/W indicates whether a new operation
Input
Synchronous
should be a read or write. If R/W is high, a read operation will be initiated, if R/W is low, a write operation will be
initiated. If the LD input is high during the rising edge of K, the R/W input will be ignored.
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and
Input Clock C can be used together to deskew the flight times of various devices on the board back to the controller. See
application example for further details.
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and
Input Clock
C can be used together to deskew the flight times of various devices on the board back to the controller. See
C
application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive
out data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
K
Input Clock
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive
out data through Q[X:0] when in single clock mode.
K
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data
CQ, CQ
Output Clock outputs and can be used as a data valid indication. These signals are free running and do not stop when the
output data is three stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and
ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode.
ZQ
Input
This pin cannot be connected directly to GND or left unconnected.
6432 tbl 02a
6.42
3
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Definitions continued
Symbol Pin Function
Description
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL
turned off will be different from those listed in this data sheet. There will be an increased propagation delay
from the incidence of C and C to Q, or K and K to Q as configured. The propagation delay is not a tested
parameter, but will be similar to the propagation delay of other SRAM devices in this speed grade.
Input
Doff
TDO
TCK
TDI
Output
Input
Input
Input
TDO pin for JTAG.
TCK pin for JTAG.
TDI pin for JTAG. An internal resistor will pull TDI to VDD when the pin is unconnected.
TMS pin for JTAG. An internal resistor will pull TMS to VDD when the pin is unconnected.
No connects inside the package. Can be tied to any voltage level.
Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs as well
TMS
NC
Input
VREF
Reference as AC measurement points.
Power
V
DD
Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Supply
Ground
VSS
Ground for the device. Should be connected to ground of the system.
Power
Supply
Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or
scaled to the desired output voltage.
VDDQ
6432 tbl 02b
6.442
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79204 (2M x 8)
1
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
6
K
7
8
9
10
11
V
SS/
V
SS/
SA
NC
NC
NC
NC
SA
NC
NC
NC
NC
NC
NC
CQ
A
B
C
D
E
F
R/W
SA
NW
1
LD
SA
SA (2)
SA (1)
NC
NC
NC
SA
K
NC
NC
NC
Q3
NW
0
VSS
SA
SA
VSS
D3
D4
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
D2
Q2
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
ZQ
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
G
H
J
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
V
DDQ
NC
NC
NC
NC
NC
NC
SA
VREF
NC
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
Q1
D1
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
K
L
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
Q0
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
D0
M
N
P
R
D7
VSS
SA
SA
SA
SA
C
SA
SA
SA
VSS
NC
NC
NC
NC
Q7
SA
SA
SA
SA
NC
TCK
SA
TMS
TDI
C
6432 tbl 12
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.42
5
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79104 (2M x 9)
1
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
6
7
8
9
10
11
V
SS/
V
SS/
SA
NC
NC
NC
NC
NC
SA
NC
BW
SA
SA
NC
NC
NC
NC
NC
NC
CQ
A
B
C
D
E
F
R/W
SA
K
LD
SA
SA (2)
SA (1)
NC
NC
K
NC
NC
NC
Q3
VSS
SA
VSS
D3
D4
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
D2
Q2
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
ZQ
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
G
H
J
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
V
DDQ
NC
NC
NC
NC
NC
NC
SA
VREF
NC
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
Q1
D1
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
NC
K
L
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
Q0
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
D0
M
N
P
R
D7
VSS
SA
SA
SA
SA
C
SA
SA
SA
VSS
NC
NC
Q7
SA
SA
SA
SA
D8
Q8
TCK
SA
TMS
TDI
C
6432 tbl 12a
165-ball FBGA Pinout
Top View
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.642
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79804 (1M x 18)
1
2
3
4
5
6
7
8
9
10
11
V
SA
SS
(3)
/
NC/
SA
VSS/
SA
R/W
NC
SA
CQ
A
B
C
D
E
F
CQ
BW1
K
LD
(1)
(2)
NC
NC
NC
NC
NC
NC
Q
9
D9
SA
NC
SA
K
SA
NC
NC
NC
NC
NC
NC
NC
Q8
BW0
NC
D10
VSS
SA
SA
VSS
Q7
D8
D
11
Q10
VSS
VSS
VSS
VSS
VSS
NC
D7
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
D6
Q6
Q
12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
D
13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
D5
G
H
J
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
V
DDQ
NC
NC
NC
NC
NC
NC
SA
VREF
ZQ
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
Q4
D4
Q14
VDDQ
VDD
VSS
VDD
VDDQ
D3
Q3
K
L
Q
15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
Q2
NC
D16
VSS
VSS
VSS
VSS
VSS
Q1
D2
M
N
P
R
D
17
Q16
VSS
SA
SA
SA
SA
C
SA
SA
SA
VSS
NC
D1
NC
Q17
SA
SA
SA
SA
D0
Q0
TCK
SA
TMS
TDI
C
6432 tbl 12b
165-ball FBGA Pinout
Top View
NOTES:
1. A3 is reserved for the 36Mb expansion address.
2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII SIO Burst of 2 (71P79804) devices.
3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII SIO Burst of 2 (71P79804) devices.
6.42
7
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79604 (512K x 36)
1
2
3
4
5
BW
BW
6
K
7
8
9
10
11
V
SS/
NC/
NC/
V
SS/
CQ
A
B
C
D
E
F
CQ
R/W
SA
2
3
BW
1
LD
SA
SA (4)
SA (2)
SA (1)
SA (3)
Q27
Q18
D18
K
D17
Q17
Q8
BW
0
D
27
Q
28
D
19
V
SS
SA
SA
SA
V
SS
D
16
Q
7
D8
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
D
30
D
22
Q
22
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
Q
13
D
13
D5
G
H
J
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
Doff
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q
4
D4
Q
32
D
32
Q
23
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
Q
12
D
3
Q3
K
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
D
33
Q
34
D
25
V
SS
V
SS
V
SS
V
SS
V
SS
D
10
Q
1
D2
M
N
P
R
D34
D26
Q25
VSS
SA
SA
SA
SA
C
SA
SA
SA
VSS
Q10
D9
D1
Q35
D35
Q26
SA
SA
SA
SA
Q
9
D0
Q0
TDO
TCK
SA
SA
TMS
TDI
C
6432 tbl 12c
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A9 is reserved for the 36Mb expansion address.
2. A3 is reserved for the 72Mb expansion address.
3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 DDRII SIO Burst of 2 (71P79604)
devices.
4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 DDRII SIO Burst of 2 (71P79604)
devices.
6.842
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1) (2)
Capacitance (TA = +25°C, f = 1.0MHz)(1)
Symbol
Rating
Value
Unit
Symbol
Parameter
Conditions
Max.
Unit
Supply Voltage on VDD with
Respect to GND
C
IN
Input Capacitance
5
6
7
pF
V
TERM
–0.5 to +2.9
V
V
DD = 1.8V
CCLK
Clock Input Capacitance
Output Capacitance
pF
VDDQ = 1.5V
Supply Voltage on VDDQ with
Respect to GND
VTERM
–0.5 to VDD+0.3
–0.5 to VDD +0.3
–0.5 to VDDQ +0.3
V
V
CO
pF
6432 tbl 06
Note:
Voltage on Input terminals with
respect to GND
VTERM
1. Testedatcharacterizationandretestedafteranydesignorprocesschangethat
may affect these parameters.
Voltage on output and I/O
terminals with respect to GND
VTERM
Recommended DC Operating
Conditions
T
BIAS
Temperature Under Bias
Storage Temperature
–55 to +125
–65 to +150
+ 20
°C
°C
TSTG
Symbol
Parameter
Min.
1.7
1.4
0
Typ.
1.8
1.5
0
Max. Unit
IOUT
Continuous Current into Outputs
mA
VDD
Power Supply Voltage
1.9
1.9
0
V
V
V
V
6432 tbl 05
Notes:
V
DDQ I/O Supply Voltage
Ground
REF Input Reference Voltage
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
maycausepermanentdamagetothedevice. Thisisastressratingonlyand
functionaloperationofthedeviceattheseoranyotherconditionsabovethose
indicatedintheoperationalsectionsofthisspecificationisnotimplied.Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
V
SS
V
-
V
DDQ/2
0 to +70
-40 to +85
-
o
c
Commercial
Industrial
Ambient
TA
Te mp e rature (1)
o
c
2. VDDQmustnotexceedVDDduringnormaloperation.
6432 tbl 04
Note:
1. During production testing, the case temperature equals the ambient
temperature.
Write Descriptions(1,2)
Signal
BW
L
0
BW
X
L
1
BW
X
X
L
2
BW
X
X
X
L
3
NW
0
NW
X
1
Write Byte 0
Write Byte 1
Write Byte 2
Write Byte 3
Write Nibble 0
Write Nibble 1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
L
6432 tbl 09
Notes:
1) All byte write (BWx) and nibble write (NWx) signals are sampled on
the rising edge of K and again on K. The data that is present on the data bus\
in the designated byte/nibble will be latched into the input if the corresponding
BWx or NWx is held low. The rising edge of K will sample the first byte/nibble
of the two word burst and the rising edge of K will sample the second byte
nibble of the two word burst.
2) The availability of the BWx orNWx on designated devices is described in the
pin description table.
3) The DDRII SIO Burst of two SRAM has data forwarding. Aread request that
is initiated on cycle following a write request to the same address will produce
the newly written data in response to the read request.
6.42
9
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Application Example
SRAM #1
SRAM #4
ZQ
Q
ZQ
Q
250
Ω
250
D
D
V
T
K
K
SA
BW1
BW0
K
SA R/W
LD
LD R/W BW
0
C
K
BW
1
C
C
C
R
Data In
Data Out
Address
R
R
R
R
R
V
T
LD
R/W
BWx/NWx
V
T
VT
MEMORY
CONTROLLER
R
R
Return CLK
Source CLK
Return CLK
Source CLK
VT = VREF
R = 50Ω
6432 drw 20
61.402
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Note
uA
Input Leakage Current
Output Leakage Current
I
IL
V
DD = Max VIN = VSS to VDDQ
-2
-2
+2
+2
Output Disabled
uA
IOL
Com'l
1050
950
850
950
850
750
650
800
700
600
420
375
335
300
Ind
1100
1000
900
980
900
800
700
850
750
650
450
410
370
335
250MH
Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
I
DD = Max,
OUT = 0mA (outputs open),
Cycle Time > tKHKH Min
Operating Current
(x36): DDR
I
DD
200MHz
167MHz
267MHz
mA
1
1
1
2
V
DD = Max,
OUT = 0mA (outputs open),
Cycle Time > tKHKH Min
250MH
Z
Operating Current
(x18): DDR
IDD
I
mA
mA
mA
200MHz
167MHz
250MH
Z
VDD = Max,
Operating Current
(x9,x8): DDR
IDD
IOUT = 0mA (outputs open),
200MHz
167MHz
267MHz
Cycle Time > tKHKH Min
Device Deselected (in NOP state)
250MH
Z
IOUT = 0mA (outputs open),
Standby Current: NOP
ISB1
f=Max,
200MHz
167MHz
All Inputs <0.2V or > VDD -0.2V
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
RQ = 250Ω, IOH = -15mA
RQ = 250Ω, IOL = 15mA
V
DDQ/2-0.12
DDQ/2-0.12
DDQ-0.2
SS
V
DDQ/2+0.12
DDQ/2+0.12
DDQ
V
V
V
V
3,7
4,7
5
V
OH1
OL1
OH2
OL2
V
V
V
IOH = -0.1mA
V
V
V
IOL = 0.1mA
V
0.2
6
V
6432 tbl 10c
NOTES:
1. Operating Current is calculated with 50% read cycles and 50% write cycles.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
6.42
11
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Input Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Input High Voltage, DC
Input Low Voltage, DC
Input High Voltage, AC
Input Low Voltage, AC
NOTES:
Symbol
Min
Max
Unit Notes
V
IH (DC
IL (DC)
IH (AC)
IL (AC)
)
V
REF +0.1
V
DDQ +0.3
V
V
V
V
1,2
1,3
4,5
V
-0.3
V
REF -0.1
V
V
REF +0.2
-
V
-
V
REF -0.2
4,5
6432 tbl 10d
1. These are DC test criteria. DC design criteria is VREF + 50mV. TheAC VIH/VILlevels are defined separately for measuring timing
parameters.
2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min))
3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min))
4. This conditon is forAC function test only, not forAC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the currentAC level through the targetAC level, VIL(AC) or VIH(AC)
b) Reach at least the targetAC level.
c)After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Overshoot Timing
Undershoot Timing
20% tKHKH (MIN)
VIH
VDD +0.5
VDD +0.25
VSS
VDD
VSS-0.25V
VSS-0.5V
VIL
6432 drw 22
6432 drw 21
20% tKHKH (MIN)
61.422
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
AC Test Conditions
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level
Symbol
Value
1.7-1.9
Unit
V
V
DD
DDQ
IH
IL
V
1.4-1.9
V
V
(VDDQ/2) + 0.5
(VDDQ/2) - 0.5
V
Input Low Level
V
V
Input Reference Level
Input Rise/Fall Time
Output Timing Reference Level
NOTE:
VREF
TR/TF
V
DDQ/2
0.3/0.3
DDQ/2
V
ns
V
V
6432 tbl 11a
1. Parameters are tested with RQ=250Ω
Input Waveform
(VDDQ/2) + 0.5V
Test points
VDDQ/2
VDDQ/2
(VDDQ/2) - 0.5V
6432 drw 07
Output Waveform
Test points
VDDQ/2
V
DDQ/2
6432 drw 08
AC Test Loads
DDQ/2
V
Ω
RL = 50
VDDQ/2
REF
V
OUTPUT
=50
Ω
Z0
Device
Under
Test
Ω
Q = 250
R
ZQ
6432 drw 04
6.42
13
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(3,7)
(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, Commercial and Industrial Temperature Ranges)
267MHz
250MHz
200MHz
167MHz
Min.
Max
Min.
Max
Min.
Max
Min.
Max
Symbol
Parameter
Unit
Notes
Clock Parameters
t
KHKH
KC var
KHKL
KLKH
KHKH
KHKH
KHCH
KC lock
Clock Cycle Time (K,K,C,C)
Clock Phase Jitter (K,K,C,C)
Clock High Time (K,K,C,C)
Clock LOW Time (K,K,C,C)
Clock to clock (K→K,C→C)
Clock to clock (K→K,C→C)
Clock to data clock (K→C,K→C)
DLL lock time (K, C)
3.75
-
6.30
4.00
-
6.30
5.00
-
7.88
6.00
-
8.40
ns
ns
t
-
0.20
0.20
0.20
1,5
8
t
1.50
1.50
1.69
1.69
0.00
1024
30
-
1.60
1.60
1.80
1.80
0.00
1024
30
-
2.00
2.00
2.20
2.20
0.00
1024
30
-
2.40
2.40
2.70
2.70
0.00
1024
30
-
ns
t
-
-
-
-
ns
8
t
-
-
-
-
ns
9
t
-
-
-
-
ns
9
t
1.69
1.80
2.30
2.80
ns
t
-
-
-
-
-
-
-
-
cycles
ns
2
t
KC reset K static to DLL reset
Output Parameters
t
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CHQZ
CHQX1
C,C HIGH to output valid
C,C HIGH to output hold
-
0.45
-
0.45
-
0.45
-
0.50
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
t
-0.45
-
-
0.45
-
-0.45
-
-
0.45
-
-0.45
-
-
0.45
-
-0.50
-
-
0.50
-
t
C,C HIGH to echo clock valid
C,C HIGH to echo clock hold
CQ,CQ HIGH to output valid
CQ,CQ HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
t
-0.45
-
-0.45
-
-0.45
-
-0.50
-
t
0.30
-
0.30
-
0.35
-
0.40
-
t
-0.30
-
-0.30
-
-0.35
-
-0.40
-
t
0.45
-
0.45
-
0.45
-
0.50
-
3,4,5
3,4,5
t
-0.45
-0.45
-0.45
-0.50
Set-Up Times
t
AVKH
Address valid to K,K rising edge
R/W inputs valid to K,K rising edge
0.50
0.50
-
-
0.50
0.50
-
-
0.60
0.60
-
-
0.70
0.70
-
-
ns
ns
6
tIVKH
Data-in and BWx/NWx valid to K, K
rising edge
tDVKH
0.35
-
0.35
-
0.40
-
0.50
-
ns
Hold Times
t
KHAX
K,K rising edge to address hold
K,K rising edge to R/W inputs hold
0.50
0.50
-
-
0.50
0.50
-
-
0.60
0.60
-
-
0.70
0.70
-
-
ns
ns
6
tKHIX
K, K rising edge to data-in and
BWx/NWx hold
tKHDX
0.35
-
0.35
-
0.40
-
0.50
-
ns
6432 tbl 11
NOTES:
1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worse case at totally different test conditions (0°C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70°C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. During production testing, the case temperature equals TA.
8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
9. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
61.442
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles
NOP
NOP
Read A0
(burst of 2)
2
Read A1
Write A2
Write A3
Read A4
(burst of 2) (burst of 2) (burst of 2) (burst of 2)
4
8
1
3
6
7
5
K
tKHKL
tKLKH
tKHKH
tKHKH
K
LD
R/W
A
tIVKH
tKHIX
A3
A4
A1
A2
A0
tKHDX
tDVKH
tKHDX
tDVKH
tAVKH tKHAX
D20
Q10
D21
Q11
D
D30 D31
Q41
Q40
Q01
Qx1
Q00
Q
C
tCHQV
tCQHQV
tCHQZ
tCHQX
tCHQV
tKHCH
tCHQX
tKHCH
tCHQX1
tKHKH
tKHKL
tKLKH
tKHKH
C
tCHCQV
tCHCQX
CQ
tCHCQV
tCHCQX
CQ
6432 drw 09a
6.42
15
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
IEEE 1149.1 TESTACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible TestAccess
Port (TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during
manufacturingandsystemdiagnostics. InconformancewithIEEE1149.1,
the SRAM contains aTAPcontroller, Instruction register, Bypass Regis-
ter and ID register. TheTAPcontroller has a standard 16-state machine
that resets internally upon power-up; therefore, the TRST signal is not
required. It is possible to use this device without utilizing the TAP. To
disable theTAPcontroller without interfacing with normal operation of the
SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and
TDI are designed so an undriven input will produce a response identical
to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0
Instruction
TDO Output
Notes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
Boundary Scan Register
Identification register
Boundary Scan Register
Do Not Use
IDCODE
2
1
5
4
5
5
A,D
SAMPLE-Z
RESERVED
K,K
C,C
SRAM
CORE
Q
CQ
CQ
SAMPLE/PRELOAD Boundary Scan register
RESERVED
RESERVED
BYPASS
Do Not Use
Do Not Use
TDI
BYPASS Reg.
TDO
Bypass Register
3
Identification Reg.
6432 tbl 13
Instruction Reg
Control Signal
TAP Controller
.
NOTES:
1. Places Qs in Hi-Z in order to sample all input data regardless of
other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the
serial shift of the external TDI data.
s
TMS
TCK
3. Bypass register is initialized to Vss when BYPASS instruction is
invoked. The Bypass Register also holds serially loaded TDI
when existing the Shift DR states.
6432 drw 18
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
TAP Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
0
Select IR
0
0
1
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
0
1
Exit 1 DR
0
Exit 1 IR
0
Pause DR
1
Pause IR
1
0
0
0
Exit 2 DR
1
Exit 2 IR
1
1
0
Update DR
0
Update IR
1
6432 drw 17
61.462
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Scan Register Definition
Part
Instrustion Register
Bypass Register
ID Register
32 bits
Boundry Scan
107 bits
512K x36
1Mx18
3 bits
3 bits
3 bits
1 bit
1 bit
1 bit
32 bits
107 bits
2Mx8/x9
32 bits
107 bits
6432 tbl 14
Identification Register Definitions
INSTRUCTION FIELD
ALL DEVICES
DESCRIPTION
PART NUMBER
Revision Number (31:29)
0x0
Revision Number
512Kx36
1Mx18
2Mx9
DDRII SIO BURST OF 2 71P79604S
0x0298
0x0299
0x029A
0x029B
71P79804S
71P79104S
71P79204S
Device ID (28:12)
2Mx8
Allows unique identification of SRAM
vendor.
IDT JEDEC ID CODE (11:1)
0x033
1
Indicates the presence of an ID register.
ID Register Presence Indicator (0)
6432 tbl 15
6.42
17
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Boundary Scan Exit Order
ORDER
PIN ID
ORDER
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PIN ID
10D
9E
ORDER
73
PIN ID
2C
3E
2D
2E
1E
2F
1
6R
2
6P
74
3
6N
10C
11D
9C
75
4
7P
76
5
7N
77
6
7R
9D
78
7
8R
11B
11C
9B
79
3F
8
8P
80
1G
1F
9
9R
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10B
11A
Internal
9A
82
3G
2G
1J
83
84
85
2J
10M
11N
9M
9N
8B
86
3K
3J
7C
87
6C
88
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
8A
89
11L
11M
9L
7A
90
7B
91
6B
92
10L
11K
10K
9J
6A
93
5B
94
5A
95
4A
96
9K
5C
97
10J
11J
11H
10G
9G
4B
98
3A
99
2N
2P
1H
100
101
102
103
104
105
106
107
1A
1P
2B
3R
4R
4P
11F
11G
9F
3B
1C
1B
10F
11E
10E
5P
3D
3C
5N
5R
1D
6432 tbl 16
6432 tbl 17
6432 tbl 18
61.482
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
JTAG DC Operating Conditions
Parameter
Symbol
Min
Ty p
Max
Unit
Note
Output Power Supply
V
DDQ
DD
IH
IL
IL
IL
OL
OH
OL
1.4
1.7
1.3
- 0.3
- 5
-
1.8
-
1.9
1.9
V
V
Power Supply Voltage
V
Input High Level
V
V
DD + 0.3
V
Input Low Level
V
-
0.5
V
TCK Input Leakage Current
TMS, TDI Input Leakage Current
TDO Output Leakage Current
Output High Voltage (IOH = -1mA)
I
-
+ 5
uA
uA
uA
V
I
- 15
- 5
-
+ 15
+ 5
I
-
V
V
DDQ - 0.2
-
VDDQ
1
Output Low Voltage (IOL = 1mA)
V
VSS
-
0.2
V
1
6432 tbl 19
NOTE:
1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor
connected to ZQ.
JTAG AC Test Conditions
Parameter
Symbol
Min
1.8
Unit
V
Note
Input High Level
VIH
Input Low Level
VIL
0
V
Input Rise/Fall Time
TR/TF
1.0/1.0
0.9
ns
V
Input and Output Timing Reference Level
1
6432 tbl 20
Note: 1. For SRAM outputs seeAC test output load on page 13.
JTAG Input Test WaveForm
JTAG AC Test Load
1.8 V
0.9 V
Test points
0.9 V
0.9 V
0 V
6432 drw 23
50ohm
Z0 = 50ohm
TDO
,
JTAG Output Test WaveForm
6109 drw 24
Test points
0.9 V
0.9 V
6432 drw 23a
6.42
19
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
TCK Cycle Time
t
CHCH
CHCL
CLCH
MVCH
CHMX
DVCH
CHDX
SVCH
CHSX
CLQV
-
-
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
t
t
-
t
-
t
5
-
t
5
-
t
5
-
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
t
5
-
t
5
-
t
0
10
6432 tbl 21
JTAG Timing Diagram
TCK
TMS
tCHCH
t
CHCL
tCLCH
tMVCH
t
CHMX
tDVCH
tCHDX
TDI/
SRAM
INPUTS
tSVCH
tCHSX
SRAM
OUTPUTS
tCLQV
TDO
6432drw 19
62.402
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
6.42
21
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
Ordering Information
X
XXX
S
XXX
BQ
IDT
Process/
Temperature
Range
Device
Type
Power Speed
Package
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BQ
165 Fine Pitch Ball Grid Array (fBGA)
Clock Frequency in MegaHertz
267
250
200
167
*
IDT71P79204 2M x 8 DDR II SIO SRAM
IDT71P79104 2M x 9 DDR II SIO SRAM
IDT71P79804 1M x 18 DDR II SIO SRAM
IDT71P79604 512K x 36 DDR II SIO SRAM
6432 drw 15
*
Only offered in the x18 option.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2774
for Tech Support:
sramhelp@idt.com
800-345-7015 or 408-284-4555
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
QDRSRAMsandQuadDataRateRAMscompriseanewfamilyofproductsdevelopedbyCypressSemiconductor,IDT,andMicronTechnology,Inc.
62.422
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2
Commercial and Industrial Temperature Ranges
RevisionHistory
REV
DATE
PAGES
DESCRIPTION
0
1
07/26/05
11/30/05
p. 1-21
ReleasedFinaldatasheet
p. 11,14,22 Added267MHzspeedgrade tothe DCandACElectricalCharacteristics tables andordering
information.
6.42
23
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