IDTP9120-00NBGI [IDT]
Triple Channel Synchronous Step- Down Switcher with Integrated FET;
| 型号： | IDTP9120-00NBGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Triple Channel Synchronous Step- Down Switcher with Integrated FET |
| 文件： | 总24页 (文件大小：1028K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Triple Channel Synchronous Step-
Down Switcher with Integrated FET
Advanced Datasheet
IDTP9120
Features
. Input Voltage Range: 2.7V to 5.5V
Description
IDTP9120 is a fully integrated power management IC
. Three step-down converters with integrated FETs
designed to provide three programmable voltage rails from a
single 5V or 3.3V input rail with high efficiency and low
quiescent currents in sleep mode or no-load condition.
.
.
.
Buck1: 2A
Buck2: 2A
Buck3: 3A
The device offers selectable direct buck enable inputs or
programmable sequencing with power good and power on
reset generation.
. Buck 3 to operate in Buck or Switch mode
. Factory Programmable Output Voltage: 0.8 - 3.4V
. Automatic PFM/PWM or forced PWM mode
. Switching frequency 2MHz
. Optional Programmable Sequence Mode
. Power Good and/or Power On Reset Output
. -40°C to +85°C operating temperature range
. Package: QFN 24-ld 4 x 4mm x 0.8mm (NBG24)
To support low power operation, the IDTP9120 supports
both sleep and standby modes.
The IDTP9120 is available in a 4mm x 4mm, 24-ld, QFN
package and is guaranteed to operate over the ambient
temperature range -40°C to +85°C.
Applications
Point of Load Regulation in a variety of low power
applications:
. Solid State Disk Drive (SSD) Power Management
. Low Power USB powered applications
. Set Top Box / TV Power Supply
. Portable Gaming
Simplified Application Diagram
INPUT VOLTAGE
INPUT VOLTAGE
VIN
FB1
VIN
FB1
LX1
PVIN1
PVIN2
PVIN3
LX1
VOUT1
VOUT2
VOUT3
PVIN1
PVIN2
PVIN3
VINSEL
VOUT1
VOUT2
VOUT3
PGND1
PGND1
VREF(optional)
FB2
LX2
FB2
LX2
VREF(optional)
VGND
VGND
VINSEL
DEVSLPIN
GPI3
DEVSLPIN
GPI3
PGND2
PGND2
FB3
LX3
FB3
LX3
GPIO14
GPIO15
GPO16
GPIO17
GPIO14
GPIO15
GPO16
GPIO17
PGND3
PGND3
IDTP9120 with VINSEL (pin 4) in Buck Configuration for VOUT3
IDTP9120 with VINSEL (pin 4) in Switch Configuration for VOUT3
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© 2014 Integrated Device Technology, Inc.
IDTP9120
Advanced Datasheet
ORDERING GUIDE
Table 1 – Ordering Summary
AMBIENT TEMP.
RANGE
PART NUMBER MARKING
PACKAGE1
SHIPPING CARRIER QUANTITY
P9120-00NBGI
P9120-xxNBGI
P9120-xxNBGI8
P9120-00NBGI
P9120-xxNBGI
P9120-xxNBGI
QFN-24 4x4x0.75mm 24-ld
QFN-24 4x4x0.75mm 24-ld
QFN-24 4x4x0.75mm 24-ld
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Tray
Tray
Tape and Reel
490
490
2,500
IDT P 91 20 – xx NBG I 8
T&R option:
8=T&R, Blank=no
Temperature Grade:
I=-40C to +85C
Package Code
Configuration ID
Device ID
PMIC Code
Power Prefix
Additional Ordering Information:
The IDTP9120 will be sampled in “-00” configuration, with all user configurable OTP registers at default state (0). Once a final
customer configuration has been defined, a configuration specific “-xx” ID will be assigned and used for order and marking.
ABSOLUTE MAXIMUM RATINGS
Stresses above the ratings listed below can cause permanent damage to the IDTP9120. These ratings are stress ratings only. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed
only over the recommended operating temperature range.
Table 2 – Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN
MAX
UNIT
PVIN1, PVIN2, PVIN3 to PGND
Regulator input voltage
Supply for device
Regulator Switch Nodes
Regulator Feedback pins
-0.3
-0.3
-0.3
-0.3
-0.3
6.0
6.0
6.0
3.6
6.0
125
150
260
V
V
V
V
V
°C
°C
°C
VIN to GND
LX1, LX2, LX3
FB1, FB2, FB3
All other pins
TJ
Operating Junction Temperature
Storage Temperature
Soldering Temperature (10 seconds)
TS
TSOLDER
1 See Package Information (Page 24) for additional details.
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IDTP9120
Advanced Datasheet
Table 3- Package Thermal Resistivity
SYMBOL
DESCRIPTION
CONDITIONS
Junction to Ambient
Junction to Board
Value
Units
Thermal Resistance (QFN-24)
JA
ΨJB
PD
40
23
C/W
C/W
W
Thermal Characterization Parameter (QFN-24)
Maximum Package Power Dissipation
(HBM) Human Body Model (all pins except 20, 21)
(HBM) Human Body Model (only pins 20, 21)
(CDM) Charged Device Model (all pins)
2.5
2000V
500V
500V
ESD Rating
Per JEDEC spec, the QFN-24 package is rated at MSL3. This thermal rating was calculated based on a JEDEC standard 4-layer board with dimensions 3in x 4.5in in still air
conditions. Actual thermal resistance will be affected by PCB size, solder joint quality, PCB layer count, copper thickness, air flow, altitude, and other unlisted variables. For
the QFN-24 package, the 2.8mm X 2.8mm EP is connected to ground plane with a matrix of 3x3 PCB thermal VIAs plated through from Top to Bottom layers. Actual thermal
resistance will be affected by PCB size, solder joint quality, PCB layer count, copper thickness, air flow, altitude, and other unlisted variables.
ELECTRICAL CHARACTERISTICS
Table 4 – General Electrical Characteristics
Typical values at 25°C, unless noted. VPVIN1 = VPVIN2 = V PVIN3 = Vin= 5V. CO(BUCK1) = CO(BUCK2) = 10µF, CO(BUCK3) = 20μF, L1=L2=L3 =1.0μH.
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© 2014 Integrated Device Technology, Inc.
IDTP9120
Advanced Datasheet
Symbol
Parameter
Conditions
Min
2.7
Typ
Max
5.5
Unit
V
Input voltage range
2.95
2.65
4.35
3.95
3
3.05
2.75
4.45
4.05
V
UVLO threshold, VIN rising
UVLO threshold, VIN falling
UVLO threshold, VIN rising
UVLO threshold, VIN falling
VINSEL>1V, Buck3 in Switch
(3.3V) Mode
VVIN
2.7
4.4
4.0
V
V
VINSEL=0V, Buck3 in Buck (5V) Mode
V
Device in sleep mode (Vref disable,
Devslpin floating).
<1
μA
IQ(VIN)
VIN quiescent current
Device in active mode, all Bucks = OFF
All inputs
108
0.85
1.25
1
μA
V
VIL
VIH
IPD
IPU
0.65
5
Low Level Input Voltage
High Level Input Voltage
Pull Down Current
All inputs
1.45
10
V
GPIO14,15,17, and GPI3
DEVSLPIN @ VIN=5V
μA
μA
8
Pull Up Current
Selectable for GPIO14,15,17, GPO16
and GPI3
RPU
TSD
VPG
50
135
10
kΩ
°C
%
Pull Up Resistor
Thermal Shutdown
% of selected output voltage in Buck
Mode, % of VPVIN3 in Switch mode
PG Detection Threshold
In push-pull configuration, VOL=0.4V,
VFBx ≥ 1.8V
4
mA
mA
V
IOD
Max Drive Output
In open drain configuration, VOL=0.4V
12
Reference Voltage Output
Voltage
VREF
CVREF
IVREF
VFB(BUCK1)/2
0.1
μF
mA
Output Capacitor VREF
Reference Voltage Output
Current
1.0
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IDTP9120
Advanced Datasheet
ELECTRICAL CHARACTERISTICS
Table 5 – Buck1 Electrical Characteristics
VO(BUCK1) = 1.8V.
Typical values at 25°C, unless noted. VPVIN1 = VPVIN2 = V PVIN3 = Vin= 5V. CO(BUCK1) = CO(BUCK2) = 10µF, CO(BUCK3) = 20μF, L1=L2=L3 =1.0μH.
Symbol
VPVIN1
Parameter
Input voltage range
Output voltage range
Regulation voltage accuracy
Line Regulation
Conditions
Min
2.7
0.8
-2
Typ
Max
5.5
3.4
2
Unit
V
V
%
VPVIN1 = 3.0V to 5V
0.01
0.04
0.5
%/V
mV/A
VO(BUCK1)
Load Regulation
IOUT1 = 0.2A to 2A, PWM mode
Offset voltage in PFM mode
VO(PFM) = VO(PWM) + Voffset
PFM mode
15
25
mV
μA
A
IQ(BUCK1)
Quiescent Current Adder
Enabled, No load, PFM mode
TJ < 115°C
Continuous operating DC
current
IOP(BUCK1)
1.8
ILIM(BUCK1)
R(on)
Peak Inductor Current
2
2.5
A
High side switch
110
56
650
2
153
78
mΩ
mΩ
Ω
Low side switch
RDIS(BUCK1)
fSW(BUCK1)
Tssr(BUCK1)
IFB1
Output discharge resistance
Switching frequency
Soft-start ramp rate
FB1 input bias current
Output Capacitor
500
1.89
4
900
2.1
12
PWM mode
MHz
mV/μs
μA
8
6
8
CO(BUCK1)
LO(BUCK1)
10
1
μF
Output Inductor
μH
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© 2014 Integrated Device Technology, Inc.
IDTP9120
Advanced Datasheet
ELECTRICAL CHARACTERISTICS
Table 6 – Buck2 Electrical Characteristics
VO(BUCK2) = 1.2V.
Typical values at 25°C, unless noted. VPVIN1 = VPVIN2 = V PVIN3 = Vin= 5V. CO(BUCK1) = CO(BUCK2) = 10µF, CO(BUCK3) = 20μF, L1=L2=L3 =1.0μH.
Symbol
VPVIN2
Parameter
Input voltage range
Output voltage range
Regulation voltage accuracy
Line Regulation
Conditions
Min
2.7
0.8
-2
Typ
Max
5.5
3.4
2
Unit
V
V
%
VPVIN2 = 3.0V to 5V
0.01
0.04
0.5
%/V
mV/A
VO(BUCK2)
Load Regulation
IOUT2 = 0.2A to 2A, PWM mode
Offset voltage in PFM mode
VO(PFM) = VO(PWM) + Voffset
PFM mode
15
25
mV
μA
A
IQ(BUCK2)
Quiescent Current Adder
Enabled, No load, PFM mode
TJ < 115°C
Continuous operating DC
current
IOP(BUCK2)
1.8
ILIM(BUCK2)
R(on)
Peak Inductor Current
2
2.5
A
High side switch
110
56
650
2
153
78
mΩ
mΩ
Ω
Low side switch
RDIS(BUCK2)
fSW(BUCK2)
Tssr(BUCK2)
IFB2
Output discharge resistance
Switching frequency
Soft-start ramp rate
FB2 input bias current
Output Capacitor
500
1.89
4
900
2.1
12
PWM mode
MHz
mV/μs
μA
8
6
8
CO(BUCK2)
LO(BUCK2)
10
1
μF
Output Inductor
μH
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IDTP9120
Advanced Datasheet
ELECTRICAL CHARACTERISTICS
Table 7– Buck3 –Electrical Characteristics
VO(BUCK3) = 3.3V
Typical values at 25°C, unless noted. VPVIN1 = VPVIN2 = V PVIN3 = Vin= 5V. CO(BUCK1) = CO(BUCK2) = 10µF, CO(BUCK3) = 20μF, L1=L2=L3 =1.0μH.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
In Buck Mode (VINSEL=LOW)
VPVIN3
2.7
0.8
-2
5.5
3.4
2
V
V
Input voltage range
Output voltage range
Regulation voltage accuracy
%
Line Regulation
Load Regulation
VPVIN3 = 3.6V to 5V
0.01
0.4
0.15
0.5
%/V
mV/A
VO(BUCK3)
IOUT3 = 0.2A to 2.4A, PWM mode
PFM mode
Offset voltage in PFM mode
VO(PFM) = VO(PWM) + Voffset
15
28
mV
IQ(BUCK3)
Quiescent Current Adder
Enabled, No load, PFM mode
μA
IOP(BUCK3)
Continuous operating DC current TJ < 115°C
Peak Inductor Current
2.3
A
ILIM(BUCK3)
R(on)
2.6
3
A
High side switch
64
45
650
2
93
61
mΩ
mΩ
Ω
Low side switch
RDIS(BUCK3)
fSW(BUCK3)
Tssr(BUCK3)
IFB3
Output discharge resistance
500
900
2.1
12
Switching frequency
Soft-start ramp rate
FB3 input bias current
Output Capacitor
PWM mode
1.89
MHz
mV/μs
μA
8
9
11
CO(BUCK3)
LO(BUCK3)
20
1
μF
Output Inductor
μH
In Switch Mode (VINSEL=HIGH), CO(BUCK3) = 10μF, VPVIN3 = 3.3V
VPVIN3
2.7
3.6
2.4
V
Input voltage range
ISHDN(BUCK3) Shutdown current
1
μA
μA
IQ(BUCK3)
IOP(BUCK3)
ILIM(BUCK3)
R(on)
Quiescent Current
No load
10
Continuous operating DC current TJ < 115°C
Current Limitation
A
2.8
3
A
High side switch
64
93
mΩ
Ω
RDIS(BUCK3)
Tssr(BUCK3)
CO(BUCK3)
Output discharge resistance
Soft-start ramp rate
300
800
16
2
mV/μs
μF
Output Capacitor
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© 2014 Integrated Device Technology, Inc.
IDTP9120
Advanced Datasheet
PIN CONFIGURATION AND DESCRIPTION
FB3 18
1
2
3
4
VGND
VREF
GPI3
GPIO17
17
IDTP9120
EP
GPO16
GPIO15
GPIO14
FB2
16
15
14
13
VINSEL
5
6
DEVSLPIN
FB1
Figure 1, Device Pinout (Top View), 0.5mm pitch QFN-24, 4x4x0.75mm
Table 8 – Pin Functions by Pin Number
#
Label
Type Description
1
2
3
VGND
VREF
GPI3
GND Device ground connection
A
Reference output [VREF=VOUT(Buck1)/2]
DI
General Purpose Input (see Modes of Operation, page 9)
Logic input to select function of Channel 3 (Logic Low = Buck operation, High = Switch operation)
and UVLO thresholds.
4
VINSEL
DI
5
6
DEVSLPIN
FB1
DI
A
Logic input to activate sleep mode (Logic Low = Normal operation, Floating = Sleep operation).
Feedback connection Buck 1
7
LX1
A
Inductor connection Buck 1
8
9
PGND1
PVIN1
PVIN2
PGND2
LX2
GND Power ground Buck 1
PWR Power supply input Buck 1
PWR Power supply input Buck 2
GND Power ground Buck 2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
EP
A
A
Inductor connection Buck 2
Feedback connection Buck 2
FB2
GPIO14
GPIO15
GPO16
GPIO17
FB3
PGND3
LX3
LX3
DIO General Purpose Input / Output (see Modes of Operation, page 9)
DIO General Purpose Input / Output (see Modes of Operation, page 9)
DO
DIO General Purpose Input / Output (see Modes of Operation, page 9)
Feedback connection Buck 3 (Buck Mode) or Output (Switch Mode)
General Purpose Output (see Modes of Operation, page 9)
A
GND Power ground Buck 3
A
Inductor connection Buck 3 (Buck Mode) or Output (Switch Mode)
A
PVIN3
PVIN3
VIN
PWR
PWR
Power supply input Buck 3
PWR Device supply input
GND Exposed pad, connect to heat sink ground plane
EP
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IDTP9120
Advanced Datasheet
FUNCTIONAL DESCRIPTION:
Overview
Modes of Operation
The IDTP9120 support several modes to control the 3
Buck regulators and to generate status information like PG
(power good) or POR (power on reset).
Device Power States
Device operates in three basic power states controlled by
the DEVSLPIN pin and one optional state (standby) when
in Mode 3.
Various device features can be configured during
production using one time programmable fuse memory
(OTP). During evaluation, the options can be evaluated
using the IDTP9120 Evaluation Kit (IDTP9120-EVAL).
Regulator Control Options (Mode 0..3)
The IDTP9120 supports four different control options for
the Buck regulator. The functionality of GPI3,
GPIO14,15,17 and GPO16 is different for each of the
options. (MODE[1:0] = OTP Bank3[1:0])
The IDTP9120 OTP memory is organized into four fuse
banks with 34 bits each. Bank0 and 1 are used for IDT
internal trimming and calibration. Bank2 and 3 are used
for customer specific device configuration.
DEVSLPIN (pin5)=HIGH
or Floating
SLEEP
VIN>VUVLO
NO
POWER
DEVSLPIN (pin5)=LOW
ON
STANDBY (GPIO14 pin14) =HIGH
STANDBY
VIN<VUVLO
STANDBY (GPIO14 pin 14) =LOW
Mode 3 only
Figure 2. Device Power States
Table 9 – Buck Control Options
MODE[1:0]
0
DESCRIPTION
GPI3
GPIO14
EN1
GPIO15
GPO16
GPIO17
Buck regulators controlled by
individual enable pins (EN1, EN2,
EN3)
NC
EN2
PORB
EN3
(Default)
1
2
Special Sequencing Option.
NC
COLDBOOT SOCREADY
PORB
PG2
DEVSLPRLY
PG3
Buck regulators controlled by master MEN
enable pin (MEN) w/ sequence
PORB
PG1
3
Buck regulators controlled by master MEN
enable pin (MEN) w/ sequence and
standby mode support
STANDBY
PG1
PG2
PG3/PORB
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© 2014 Integrated Device Technology, Inc.
IDTP9120
Advanced Datasheet
Mode1 – Special Sequencing Option
Mode0 – Individual Buck control
With IDTP9120 configured for mode1, a specific state
machine will control the regulators. The sequence has
been implemented for specific controllers used in solid
state disk (SSD) applications. The sequencing details are
documented in the following state diagrams. For further
details on the “Special Sequencing Option”, please
contact IDT.
With IDTP9120 configured for mode0, all three regulators
are individually controlled via ENx input pin. The PORB
output can be configured to indicate various power up
conditions.
Device Start Up:
VIN (5V/3.3V)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Input supply ramps-up.
DEVSLPIN is pulled low, device starts-up.
Device started-up, VOUT2 starts-up.
VOUT2 ramped-up, VOUT3 starts-up.
VOUT3 ramped-up, VOUT1 starts-up.
PORB de-asserts high.
VOUT2 (1.2V)
VOUT1 (1.8V)
VOUT3 (3.3V)
COLDBOOT
PORB
X
SOCREADY (from controller) asserts high.
X
DEVSLPIN
High-z
X
Note: Buck Voltages and Sequence shown is
default and can be re-programmed.
DEVSLPRLY
SOCREADY
Status ignored
1
2
3
4
5
6
7
Active mode
Figure 3, Mode1 - Device Start Up
Device enters DevSlp:
VIN (5V/3.3V)
VOUT2 (1.2V)
(1)
(2)
DEVSLPIN asserts high.
If SOCREADY is high, DEVSLPRLY is asserted high.
Otherwise DEVSLPIN is ignored,
VOUT1 (1.8V)
VOUT3 (3.3V)
COLDBOOT
DEVSLPRLY remains low.
(3)
Device is waiting for SOCREADY to de-assert low.
SOCREADY is expected to go low within 500ms.
PORB
DEVSLPIN
DEVSLPRLY
SOCREADY
(4)
(5)
(6)
(7)
(8)
PORB is asserted low.
DEVSLPRLY de-asserts low.
VOUT2 shuts down.
VOUT2 ramped-down. VOUT3 shuts down.
VOUT1 shuts down.
<10ms pulses ignored
1
3
4
5
6
7
8
2
Figure 4, Mode1 - Device enters DevSlp
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IDTP9120
Advanced Datasheet
VIN (5V/3.3V)
VOUT2 (1.2V)
VOUT1 (1.8V)
Device exits DevSlp:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
DEVSLPIN de-asserts low.
COLDBOOT de-asserts high, VOUT2 starts-up.
VOUT2 ramped-up, VOUT3 starts-up.
VOUT3 ramped-up, VOUT1 starts-up.
VOUT1 ramped-up, PORB de-asserts high.
Device is waiting for SOCREADY to assert high.
COLDBOOT asserts low.
VOUT3 (3.3V)
COLDBOOT
PORB
DEVSLPIN
DEVSLPRLY
SOCREADY
1
2
3
4
5
6
7
<10ms pulses ignored
Figure 5. Mode1 - Device enters DevSlp
Device shut-down:
UVLO
VIN (5V/3.3V)
(1)
VIN falls below the UVLO threshold,
VOUT2 (1.2V)
VOUT1 (1.8V)
PORB asserts low.
After 2ms delay, VOUT1 ramps down.
VOUT3 ramps down.
(2)
(3)
(4)
VOUT3 (3.3V)
COLDBOOT
VOUT2 and VREF ramp down.
PORB
DEVSLPIN
DEVSLPRLY
SOCREADY
Status ignored
Status ignored
4
1
2
3
Figure 6. Mode1 - Device shut-down
Mode2 – Master Enable pin (MEN) with sequence
With IDTP9120 configured for mode2, a configurable state
machine will ramp up/down all 3 regulators controlled by
the MEN pin. The PORB output can be configured to
indicate various power up conditions. Individual Power
Good output pins indicate the regulator output being
established.
Mode3 – Master Enable pin (MEN) with sequence
and Standby Mode
With IDTP9120 configured for mode3, a configurable state
machine will ramp up/down all 3 regulators controlled by
the MEN pin. The PORB output can be configured to
indicate various power up conditions. Individual Power
Good output pins indicate the regulator output being
established.
In addition to mode2, mode3 supports the STANDBY
mode entered by asserting the STANDBY pin. During
standby, Buck1,2 and/or 3 will be turned off without
sequencing. The configuration is programmable via OTP.
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© 2014 Integrated Device Technology, Inc.
IDTP9120
Advanced Datasheet
Pin Description
DEVSLPIN
VGND
This pin allows the IC to enter and exit SLEEP mode. Sleep
mode is the lowest power state of the device and is activated
when DEVSLPIN is logic HIGH. The device will be in “normal
operation” when DEVSLPIN is logic LOW. See figure 2 – Device
Power States. For 1uA sleep mode operation, leave this pin
floating. In floating operation, it is internally pulled up to ~1.5V.
If pulled to Vin (between 3.0V and 6.0V), leakage current will
flow between ~10uA to ~18uA respectively.
VGND is the ground pin for the bias and control portion of the
integrated circuit. The trace from this pin, to a dedicated ground
plane, should be made as short as possible.
EP
This is the exposed pad on the bottom side of the IC. It must be
connected to a top or bottom circuit board ground plane to
maximize the thermal dissipation performance of the IC.
VINSEL
VREF
This pin allows the function of Buck 3 to be changed to a Switch
function. Logic LOW on this pin puts the channel into Buck
configuration, and a Logic HIGH on this pin puts the channel
into Switch configuration. The UVLO threshold is also
dependent on the VINSEL configuration. See Table 4 – General
Electrical Characteristics for details.
The Vref pin tracks the output voltage of Buck 1, at half its value.
A 2.2µF 6.3V rated X7R capacitor must be connected at this pin
when enabled. This feature should be disabled in the OTP
setting and left floating when not needed.
FB1, FB2, FB3
FB1, FB2, FB3 are the respective feedback pins of the output
voltage for each buck converter. The LSB of the outputs for
each channel is 25mV from 0.8000V to 3.3375V. In the layout,
the feedback traces should be kept as short as possible and
should never run parallel to the inductors nor to the inductor
trace leading to the inductor switching pin. Feedback traces
should always cross inductors and inductor traces on separate
planes and at right angles.
PVIN1, PVIN2, PVIN3
PVINx is each buck converters’ respective power supply input.
They provide power to the internal MOSFETs for the switch
mode regulator. Their operating range is 2.7V to 5.5V, and a
10µF capacitor must be placed as close as possible to each of
the respective pins. A second 10µF capacitor should be used
with PVIN3 because of the greater current sourcing capability of
this channel. Because the capacitance value decreases with
voltage, a 10V rated X7R ceramic capacitors must be used.
X7R is preferred over X5R because the derating with X7R is
less. For best performance, each of these power supply inputs
is to be connected together on a dedicated circuit board power
plane, and the trace going from these pins, to the dedicated
power plane, must be made as short as possible. Y5V
capacitors are not recommended because of their general low
performance with respect to temperature, voltage derating, and
higher resistance at high frequencies, minimizing their ability to
filter out high frequency noise.
LX1, LX2, LX3
LX1, LX2, LX3 are the switching pins of the respective buck
converters. The IDTP9120 is optimized for 1µH small footprint
chip inductors, and connect to the switching pins. The inductors
must be placed as close as possible to the LX pins themselves.
GPI3, GPIO14, GPIO15, GPO16, GPIO17
These pins have multiple functions, see Table 9 for device
mode depended mode function.
VIN
VIN is the power supply input for the bias and control portion of
the integrated circuit. It too has an operating range of 2.7V to
5.5V, and a 2.2µF 10V rated X7R capacitor must be placed as
close as possible to its pin. VIN should also be tied to the same
power plane that the PVINx pins are tied to with as short a trace
as possible. Do not use Y5V capacitors.
PGND1, PGND2, PGND3
These are the dedicated ground pins for each of the respective
power supplies. The traces from these pins, to a dedicated
ground plane must be made as short and wide as possible.
March 12, 2014
© 2014 Integrated Device Technology, Inc.
12
IDTP9120
Advanced Datasheet
Component Selection
The IDTP9120 is a high performance triple DC-DC step down
converter that satisfies the solution size demands of miniature
portable electronic devices. It has two 2A outputs and one 3A
output in a 4mm x 4mm QFN package. Only three external
components are required per channel (Cin, Cout, L). Because it
is designed to automatically switch to a pulse frequency
modulation scheme at light loads, the IDTP9120 is able to
maintain high efficiency across the entire load range while
providing ultra-fast load transient response.
Inductor Selection
The IDTP9120 has been designed for use with a 1.0µH inductor.
A larger value inductor will produce lower output voltage ripple,
but a slightly smaller inductor value will produce faster transient
response. The best compromise is a 1.0µH inductor. The
inductor must be rated for the maximum peak current. Selection
of the inductor needs to ensure maximum operating current not
just the DC current, and can be rated for a 40°C temperature
rise. This maximum operating current or peak current for a buck
converter can be calculated using equation 1
Input Capacitor
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇ ꢈ ꢉꢊ ꢋ ꢍꢌꢎ
eq (1);
A 10µF ceramic capacitor or greater must be placed close to
each PVIN pin for each channel for bypassing. For the VIN pin,
a 2.2µF 10V capacitor is sufficient because the VIN pin is
powering the low power internal circuitry of the IC.
where r is the inductor current ripple ratio and equal to eq (2).
ꢔꢕꢖꢗ
ꢒꢓ
Output Capacitor
ꢔꢘꢙ
ꢏ ꢄ ꢐꢅꢆꢇ ꢈ ꢑꢚꢛꢜꢝꢈꢞꢈꢟ
ꢠ
eq (2);
A 10µF or greater ceramic capacitor must be placed close to
each output inductor. Increasing the output capacitance will
lower output ripple and improve load transient response but
could also increase solution size or cost. The voltage rating of
the output capacitor must be at least 6.3V.
where L and f are the inductor and switching frequency.
Simplifying gives equation 3:
ꢔꢕꢖꢗ
ꢒꢓ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇ ꢋ ꢐꢅꢆꢇ ꢈ ꢑ ꢔꢘꢙ ꢠ
eq (3).
ꢍꢈꢞꢈꢟ
Equation 3 shows that the peak inductor current is inversely
related to the switching frequency and inductance. In other
words, the lower the switching frequency or inductance, the
higher the peak current. Peak current also increases as input
voltage increases. The value of the inductor depends on the
application. A validated inductor is the Toko 1239AS-H-1R0M.
March 12, 2014
13
© 2014 Integrated Device Technology, Inc.
IDTP9120
Advanced Datasheet
Typical Operating Characteristics
Typical values at 25°C, unless noted. VPVIN1 = VPVIN2 = V PVIN3 = Vin= 5V. CO(BUCK1) = CO(BUCK2) = 10µF, CO(BUCK3) = 20μF, L1=L2=L3 =1.0μH.
Efficiency vs Load Current
Vin=5V, Vo1=1.8V
Efficiency vs Load Current
Vin=5V, Vo2=1.2V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
0.001
0.01
0.1
Load Current (A)
auto PFM/PWM
1
0.001
0.01
0.1
Load Current (A)
1
Figure 7. Channel 1 Efficiency
Figure 8. Channel 2 Efficiency
Efficiency vs Load Current
Vin=5V, Vo3=3.3V
Line Regulation
Vo3=3.3V
1.0%
0.5%
0.0%
-0.5%
-1.0%
100
90
80
70
60
50
40
30
20
10
0
0.001
0.01
0.1
1
4.5
5
5.5
Load Current (A)
Vin (V)
auto PFM/PWM
0.8A
1.0A
1.2A
1.4A
1.6A
1.8A
Figure 9. Channel 3 Efficiency
Figure 10. Channel 3 Line Regulation
March 12, 2014
© 2014 Integrated Device Technology, Inc.
14
IDTP9120
Advanced Datasheet
Line Regulation
Vo1=1.8V
Line Regulation
Vo2=1.2V
0.100%
0.050%
0.000%
-0.050%
-0.100%
0.100%
0.050%
0.000%
-0.050%
-0.100%
4.5
5
5.5
4.5
5
5.5
Vin (V)
Vin (V)
0.8A
1.0A
1.2A
1.4A
1.6A
1.8A
0.8A
1.0A
1.2A
1.4A
1.6A
1.8A
Figure 12. Channel 2 Line Regulation
Figure 11. Channel 1 Line Regulation
Load Regulation
Vin=5V, Vo1=1.8V
Load Regulation
Vin=5V, Vo2=1.2V
0.10%
0.05%
0.00%
-0.05%
-0.10%
0.10%
0.05%
0.00%
-0.05%
-0.10%
0
1
2
3
0
1
2
3
Load Current (A)
Load Current (A)
Ch1 Vout=1.8V
Ch2 Vo=1.2V
Figure 13. Channel 1 Load Regulation
Figure 14. Channel 2 Load Regulation
March 12, 2014
15
© 2014 Integrated Device Technology, Inc.
IDTP9120
Advanced Datasheet
Load Regulation
Vin=5V, Vo3=3.3V
0.10%
0.05%
0.00%
-0.05%
-0.10%
0
1
2
3
Load Current (A)
Ch3 Vo=3.3V
Figure 15. Channel 3 Load Regulation
Figure 16. Channel 1 Load Transient Response
Figure 17. All Channel Startup Waveforms
Figure 18. Channel 1 Switch Node Switching Frequency
March 12, 2014
© 2014 Integrated Device Technology, Inc.
16
IDTP9120
Advanced Datasheet
Sleep Mode Quiescent Current
QuiescentCurrent Over Temperature
Vref Disable, Devslpin Floating, No Load, PFM Mode, Vin=5V
5
4
3
2
1
0
120
100
80
60
40
20
0
-40
-20
0
20
40
60
80
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Temperature(°C)
Vin (V)
DEVSLPIN pin floating, Vref=Disable
Quiescent Current Over Temperature
Figure 19. Sleep Quiescent Current
Figure 20. Quiescent Current Over Temperature
March 12, 2014
17
© 2014 Integrated Device Technology, Inc.
IDTP9120
Advanced Datasheet
OTP Register Mapping
The following table lists all configurable OTP registers available in the IDTP9120.
The registers can be programmed for evaluation purpose using the IDTP9120 Evaluation Kit (IDTP9120-EVAL) with the
included GUI software. The final production configuration will be programmed by IDT during final test.
(Bank T0)
Trim Bits
(Default)
Parametric Trim Descriptions
T0[29]
(0)
DEVSLP Mode Support: Sets device behavior when supply is initially
applied.
0 : Device always powers up independent of DEVSLPIN pin state.
SSD (Solid State Disk) application mode.
1 : Device powers up only when DEVSLPIN is low.
(Bank T1)
Trim Bits
(Default)
Parametric Trim Descriptions
T1[22:21]
(00)
Buck1 Slope Compensation Select: Device option for Buck 1. To be
selected based on inductor value and expected PWM duty cycle.
00 : Slope comp=Nominal
01 : Slope comp=+20%
10 : Slope comp=+100%
11 : Slope comp=+40%
T1[24:23]
(00)
Buck2 Slope Compensation Select: Device option for Buck 2. To be
selected based on inductor value and expected PWM duty cycle.
00 : Slope comp=Nominal
01 : Slope comp=+20%
10 : Slope comp=+100%
11 : Slope comp=+40%
T1[26:25]
(00)
Buck3 Slope Compensation Select: Device option for Buck 3. To be
selected based on inductor value and expected PWM duty cycle.
00 : Slope comp=Nominal
01 : Slope comp=+20%
10 : Slope comp=+100%
11 : Slope comp=+40%
March 12, 2014
© 2014 Integrated Device Technology, Inc.
18
IDTP9120
Advanced Datasheet
(Bank T2)
Trim Bits
(Default)
Parametric Trim Descriptions
T2[0]
(0)
Buck1 Transconductance Selection: Relevant for all modes
0 : Nominal
1 : 3x transconductance
T2[1]
(0)
Buck1 Bandwidth Selection: Relevant for all modes
0 : Nominal
1 : 2x bandwidth
T2[2]
(0)
Buck1 Forced PWM Mode: Relevant for all modes
0 : Auto-switching between PWM & PFM modes
1 : Forced PWM mode
T2[3]
(0)
Buck2 Transconductance Selection:
0 : Nominal
1 : 3x transconductance
T2[4]
(0)
Buck2 Bandwidth Selection:
0 : Nominal
1 : 2x bandwidth
T2[5]
(0)
Buck2 Forced PWM Mode:
0 : Auto-switching between PWM & PFM modes
1 : Forced PWM mode
T2[6]
(0)
Buck3 Transconductance Selection:
0 : Nominal
1 : 3x transconductance
T2[7]
(0)
Buck3 Bandwidth Selection:
0 : Nominal
1 : 2x bandwidth
T2[8]
(0)
Buck3 Forced PWM Mode:
0 : Auto-switching between PWM & PFM modes
1 : Forced PWM mode
T2[10:9]
(00)
Power-Off Sequencer Delay 1: Relevant only when mode[1:0]≠’00’
00 : 0.5ms
01 : 1ms
10 : 2ms
11 : 4ms
T2[12:11]
(00)
Power-Off Sequencer Delay 2: Relevant only when mode[1:0]≠’00’
00 : 0.5ms
01 : 1ms
10 : 2ms
11 : 4ms
March 12, 2014
19
© 2014 Integrated Device Technology, Inc.
IDTP9120
Advanced Datasheet
(Bank T2)
Trim Bits
(Default)
Parametric Trim Descriptions
T2[15:13]
(000)
Buck Power-Off Sequence Selection: Relevant only when
mode[1:0]≠’00’
000 : Buck2 Buck3 Buck1
001 : Buck2 Buck1 Buck3
010 : Buck1 Buck2 Buck3
011 : Buck1 Buck3 Buck2
100 : Buck3 Buck1 Buck2
101 : Buck3 Buck2 Buck1
110 : Buck1 Buck2 & Buck3
111 : Buck2 Buck1 & Buck3
T2[18:16]
(000)
PORB Output Boolean Operator Selection: PG=Power Good
000 : PG1 & PG2 & PG3
001 : PG1
010 : PG2
011 : PG3
100 : PG1 & PG2
101 : PG1 & PG3
110 : PG2 & PG3
111 : reserved
T2[19]
(0)
GPI3 Internal Pull-up Enable:
0 : Disable (1mA pull-down to VGND)
1 : Enable (100kΩ pull-up to VIN)
T2[20]
Unused
T2[21]
(0)
GPIO14 Internal Pull-up Enable:
0 : Disable (1mA pull-down to VGND when pin configured as input)
1 : Enable (50kΩ pull-up to supply voltage selected by gpio14_vio)
T2[22]
(0)
GPIO14 Open-Drain Output Select:
Relevant only when pin configured as output.
0 : Push-pull output
1 : Open-drain output
T2[23]
(0)
GPIO14 I/O Voltage Select: For both input buffer and push-pull output
driver.
0 : VOUT3 (FB3)
1 : VOUT1 (FB1)
T2[24]
(0)
GPIO15 Internal Pull-up Enable:
0 : Disable (1mA pull-down to VGND when pin configured as input)
1 : Enable (50kΩ pull-up to supply voltage selected by gpio15_vio)
T2[25]
(0)
GPIO15 Open-Drain Output Select:
Relevant only when pin configured as output.
0 : Push-pull output
1 : Open-drain output
T2[26]
(0)
GPIO15 I/O Voltage Select: For both input buffer and push-pull output
driver.
0 : VOUT3 (FB3)
1 : VOUT1 (FB1)
T2[27]
(0)
GPO16 Internal Pull-up Enable:
0 : Disable
1 : Enable (50kΩ pull-up to supply voltage selected by gpo16_vo)
March 12, 2014
© 2014 Integrated Device Technology, Inc.
20
IDTP9120
Advanced Datasheet
T2[28]
(0)
GPO16 Open-Drain Output Select:
0 : Push-pull output
1 : Open-drain output
T2[29]
(0)
GPO16 Output Voltage Select: For push-pull output driver.
0 : VOUT3 (FB3)
1 : VOUT1 (FB1)
T2[30]
(0)
GPIO17 Internal Pull-up Enable:
0 : Disable (1mA pull-down to VGND when pin configured as input)
1 : Enable (50kΩ pull-up to supply voltage selected by gpio17_vio)
T2[31]
(0)
GPIO17 Open-Drain Output Select:
Relevant only when pin configured as output.
0 : Push-pull output
1 : Open-drain output
T2[32]
(0)
GPIO17 I/O Voltage Select: For both input buffer and push-pull output
driver.
0 : VOUT3 (FB3)
1 : VOUT1 (FB1)
T2[33]
(0)
VREF Output Disable:
0 : VREF = 0.5 x VOUT1(FB1)
1 : VREF output disabled
(Bank T3)
Trim Bits
(Default)
Parametric Trim Descriptions
T3[1:0]
(00)
Device I/O Configuration and Control:
00 : Individual regulator enable via pins
01 : Special Sequence mode
10 : Master enable control with programmable sequencing
11 : Master enable control with programmable sequencing
+ SLEEP mode support
T3[2]
(0)
TSD & UVLO Fault Disable:
Used for device characterization and burn-in only.
0 : Fault event shuts down all Buck regulators (programmed
sequence)
1 : Fault ignored
T3[5:3]
(000)
Buck Power-On Sequence Selection: Relevant only when
mode[1:0]≠’00’
000 : Buck2 Buck3 Buck1
001 : Buck3 Buck1 Buck2
010 : Buck3 Buck2 Buck1
011 : Buck1 Buck3 Buck2
100 : Buck2 Buck1 Buck3
101 : Buck1 Buck2 Buck3
110 : Buck2 & Buck3 Buck1
111 : Buck1 & Buck3 Buck2
T3[6]
(0)
Buck1 SLEEP Mode Support: Relevant only when mode[1:0]=‘11’
0 : Buck1 not affected by SLEEP mode
1 : Buck1 supports SLEEP mode control
March 12, 2014
21
© 2014 Integrated Device Technology, Inc.
IDTP9120
Advanced Datasheet
(Bank T3)
Trim Bits
(Default)
Parametric Trim Descriptions
T3[7]
(0)
Buck2 SLEEP Mode Support: Relevant only when mode[1:0]=‘11’
0 : Buck2 not affected by SLEEP mode
1 : Buck2 supports SLEEP mode control
T3[8]
(0)
Buck3 SLEEP Mode Support: Relevant only when mode[1:0]=‘11’
0 : Buck3 not affected by SLEEP mode
1 : Buck3 supports SLEEP mode control
T3[10:9]
(00)
Power-On Sequencer Delay 1: Relevant only when mode[1:0]≠’00’
00 : 0.5ms
01 : 1ms
10 : 2ms
11 : 4ms
T3[12:11]
(00)
Power-On Sequencer Delay 2: Relevant only when mode[1:0]≠’00’
00 : 0.5ms
01 : 1ms
10 : 2ms
11 : 4ms
T3[19:13]
(0x00)
Vout1:
000d : 1.800V(Vout1) / 1.200V(Vout2) / 3.300V(Vout3)
001d : 0.800V
002d : 0.825V
003d : 0.850V
(1.800V)
T3[26:20]
(0x00)
Vout2:
(1.200V)
:
:
:
:
T3[33:27]
(0x00)
Vout3:
(3.300V)
100d : 3.275V
101d : 3.300V
102d : 3.325V
≥103d : 3.3375V
March 12, 2014
© 2014 Integrated Device Technology, Inc.
22
IDTP9120
Advanced Datasheet
APPLICATION INFORMATION
Figure 21. Minimum component schematic of IDTP9120.
BILL OF MATERIALS
#
Description
IDTP9120-00NBGI 4X4QFN
1uH 2520/1008
Package Manufacturer Part Number
IC1
L1-L3
IDT
TOKO 1239AS-H-1R0M
C0805C106K8RACTU
C1206C106K9RACTU
06036C225KAT2A
C1-C3, C10 10uF, 10v, X7R 0805/2012
C4-C7
C8-C9
10uF, 6.3v, X7R 1206/3216
2.2uF, 10v, X7R 0603/1608
March 12, 2014
23
© 2014 Integrated Device Technology, Inc.
IDTP9120
Advanced Datasheet
PACKAGE INFORMATION
Please refer to the documents located under http://www.idt.com/package/nbg24 for detailed package outline, recommended
footprint, carrier and RoHS information. IDTP9120 is using the P1-NBG24 package option (EP size: 2.8mm)
www.IDT.com
6024 Silver Creek Valley Road
San Jose, California 95138
Tel: 800-345-7015
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All
information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the
described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided
without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of
merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT
or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly
affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks u20141os and designs, are the property of IDT or their respective third
party owners.
© Copyright 2014. All rights reserved.
Error! Unknown document property name.
© 2014 Integrated Device Technology, Inc.
24
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