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IDTIPGG5V9882T [IDT]

3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR; 3.3V EEPROM的可编程时钟发生器
IDTIPGG5V9882T
型号： IDTIPGG5V9882T
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
3.3V EEPROM的可编程时钟发生器

时钟发生器 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器
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中文：  中文翻译
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IDT5V9882T  
3.3V EEPROM  
PROGRAMMABLE CLOCK  
GENERATOR  
FEATURES:  
DESCRIPTION:  
• Three internal PLLs  
TheIDT5V9882Tisaprogrammableclockgeneratorintendedforhigh  
performancedata-communications,telecommunications,consumer,and  
networking applications. There are three internal PLLs, each individually  
programmable,allowingforthreeuniquenon-integer-relatedfrequencies.  
The frequencies are generated from a single reference clock. The  
reference clock can come from one of the two redundant clock inputs. A  
glitchless automatic or manual switchover function allows any one of the  
redundant clocks to be selected during normal operation.  
• Internal non-volatile EEPROM  
• FAST mode I2C serial interfaces  
• Input Frequency Ranges: 1MHz to 400MHz  
• Output Frequency Ranges: 4.9kHz to 500MHz  
• Reference Crystal Input with programmable oscillator gain and  
programmable linear load capacitance  
− Crystal Frequency Range: 8MHz to 50MHz  
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider  
• 10-bit post-divider blocks  
The IDT5V9882T can be programmed through the use of the I2C  
interfaces. The programming interface enables the device to be pro-  
grammedwhenitisinnormaloperationorwhatiscommonlyknownasin-  
systemprogrammable. AninternalEEPROMallowstheusertosaveand  
restore the configuration of the device without having to reprogram it on  
power-up.  
• Fractional Dividers  
• Two of the PLLs support Spread Spectrum Generation  
capability  
• I/O Standards:  
− Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS  
− Inputs - 3.3V LVTTL/ LVCMOS  
• Programmable Slew Rate Control  
• Programmable Loop Bandwidth Settings  
• Programmable output inversion to reduce bimodal jitter  
• Individual output enable/disable  
• Power-down mode  
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback  
divider. Thisallowstheusertogeneratethreeuniquenon-integer-related  
frequencies. The PLL loop bandwidth is programmable to allow the user  
totailorthePLLresponsetotheapplication. Forinstance,theusercantune  
the PLL parameters to minimize jitter generation or to maximize jitter  
attenuation. Spread spectrum generation and fractional divides are  
allowed on two of the PLLs.  
• 3.3VVDD  
• Available in TSSOP package  
Thereare10-bitpostdividersonfiveofthesixoutputbanks. Twoofthe  
six output banks are configurable to be LVTTL, LVPECL, or LVDS. The  
otherfouroutputbanksareLVTTL. TheoutputsareconnectedtothePLLs  
via the switch matrix. The switch matrix allows the user to route the PLL  
outputstoanyoutputbank. Thisfeaturecanbeusedtosimplifyandoptimize  
the board layout. In addition, each output's slew rate and enable/disable  
function can be programmed.  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JUNE 2010  
1
c
2010 Integrated Device Technology, Inc.  
DSC 7064/2  
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
FUNCTIONALBLOCKDIAGRAM  
XTALOUT  
OSC.  
XTALIN/REFIN  
OUT1  
P2 Divider  
10-Bit  
/2  
/2  
OUT2  
PLL 0  
PLL 1  
PLL 2  
(1)  
OUT3  
P4 Divider  
10-Bit  
OUT3(1)  
P6 Divider  
10-Bit  
/2  
OUT4  
EEPROM  
Control Block for  
Multi-Purpose I/O, Programming, Features  
I 2 C_MFC  
NOTE:  
1. OUT3 pair can be configured to be LVDS, LVPECL, or two single-ended LVTTL outputs.  
2
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
PINCONFIGURATION  
SHUTDOWN/OE/  
SUSPEND  
OUT2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
VDD  
VDD  
I2C_MFC  
XTALIN/REFIN  
XTALOUT  
OUT1  
GIN1/SCLK  
GIN0/SDAT  
GND  
GND  
OUT3  
OUT4  
10  
9
VDD  
OUT3  
TSSOP  
TOP VIEW  
PINDESCRIPTION  
Pin Name  
Pin#  
I/O  
Type  
Description  
XTALIN/REFIN  
3
I
O
I
LVTTL  
LVTTL  
CRYSTAL_IN-Referencecrystalinputorexternalreferenceclockinput  
XTALOUT  
4
CRYSTAL_OUT-Referencecrystalfeedback  
GIN0/SDAT  
16  
LVTTL  
Multi-purpose inputs. Can be used for Frequency Control or SDAT(I2C).  
Multi-Purpose inputs. Can be used for Frequency Control or SDAT(I2C).  
Enables/disablestheoutputs,PLLsorpowersdownthechip.  
I2C (HIGH) or MFC Mode (MID)  
GIN1/SCLK  
17  
I
LVTTL  
SHUTDOWN/OE/SUSPEND  
20  
I
LVTTL  
3-level(1)  
I2C_MFC  
OUT1  
OUT2  
OUT3  
OUT3  
OUT4  
VDD  
18  
I
5
O
O
O
O
O
LVTTL  
Configurableclockoutput1.Canalsobeusedtobufferthereferenceclock.  
Configurableclockoutput2  
1
LVTTL  
7
8
Adjustable(2)  
Adjustable(2)  
LVTTL  
Configurableclockoutput3,Single-EndedorDifferentialwhencombinedwithOUT3  
Configurablecomplementaryclockoutput3,Single-EndedorDifferentialwhencombinedwithOUT3  
Configurableclockoutput4  
13  
2, 13, 19  
6, 15  
3.3V Power Supply  
GND  
Ground  
NOTES:  
1. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are internally biased to VDD/2. They are not hot-insertable or over voltage tolerant.  
2. Outputs are user programmable to drive single-ended 3.3V LVTTL, differential LVDS, or differential LVPECL interface levels.  
3
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
PLLFEATURESANDDESCRIPTIONS  
D0 Divider  
/ 8-bit  
VCO  
M0 Multiplier  
/ 12-bit  
Spread  
Spectrum  
Modulation  
PLL0 Block Diagram  
D1 Divider  
/ 8-bit  
VCO  
M1 Multiplier  
/ 12-bit  
Spread  
Spectrum  
Modulation  
PLL1 Block Diagram  
D2 Divider  
/ 8-bit  
VCO  
M2 Multiplier  
/ 12-bit  
PLL2 Block Diagram  
4
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
Spread Spectrum  
Pre-Divider (D) Values  
Multiplier (M) Values  
Programmable Loop Bandwidth  
GenerationCapability  
PLL0  
PLL1  
PLL2  
1 - 255  
1 - 255  
1 - 255  
2 - 8190  
2 - 8190  
1 - 4095  
yes  
yes  
yes  
yes  
yes  
no  
WhereFIN isthereferencefrequency,Misthetotalfeedback-dividervalue,  
Disthepre-scalervalue,Pisthetotalpost-dividervalue,andFOUTistheresulting  
output bank frequency. The value 2 in the denominator is due to the divide-  
by-2oneachoftheoutputbanksOUT2-4. NotethatOUT1doesnothaveany  
typeofpost-divider. Also,programminganyofthedividersmaycauseglitches  
ontheoutputs.  
CRYSTALINPUT(XTALIN/REFIN)  
Thecrystaloscillatorsshouldbefundamentalmodequartzcrystals:overtone  
crystals are not suitable. Crystal frequency should be specified for parallel  
resonancewith50Ωmaximumequivalentseriesresonance.  
WhentheXTALIN/REFINpinisdrivenbyacrystal,itisimportanttosetthe  
internal oscillator inverter drive strength and internal tuning/load capacitor  
values correctly to achieve the best clock performance. These values are  
programmablethroughanI2C_MFCinterfacetoallowformaximumcompatibility  
with crystals from various manufacturers, processes, performances, and  
qualities.Theinternalloadcapacitorsaretrueparallel-platecapacitorsforultra-  
linear performance. Parallel-plate capacitors were chosen to reduce the  
frequencyshiftthatoccurswhennon-linearloadcapacitanceinteractswithload,  
bias, supply, and temperature changes. External non-linear crystal load  
capacitors should not be used for applications that are sensitive to absolute  
frequencyrequirements.Thevalueoftheinternalloadcapacitorsaredetermined  
byXTALCAP[7:0]bits,(0x07).Theloadcapacitancecanbesetwitharesolution  
of 0.125 pF for a total crystal load range of 3.5pF to 35.4pF. Check with the  
vendor'scrystalloadcapacitancespecificationfortheexactsettingtotunethe  
internalloadcapacitor. Thefollowingequationgovernshowthetotalinternal  
loadcapacitanceisset.  
Pre-Scaler  
D[7:0] are the bits used to program the pre-scaler for each PLL, D0 for  
PLL0, D1 for PLL1, and D2 for PLL2. The pre-scalers divide down the  
referenceclockwithintegervaluesrangingfrom1to255. Tomaintainlowjitter,  
thedivideddownclockmustbehigherthan400KHz;itisbesttousethesmallest  
Ddividervaluepossible. IfDissetto'0x00',thenthiswillpowerdownthePLL  
andalltheoutputsassociatedwiththatPLL.  
XTAL load cap = 3.5pF + XTALCAP[7:0] * 0.125pF (Eq. 1)  
Parameter  
Bits  
Step  
Min  
Max  
Units  
XTALCAP  
8
0.125  
0
32  
pF  
When using an external reference clock instead of a crystal on the XTAL/  
REFINpin,theinputloadcapacitorsmaybecompletelybypassed.Thisallows  
fortheinputfrequencytobeupto200MHz. Whenusinganexternalreference  
clock,theXTALOUTpinmustbeleftfloating,XTALCAPmustbeprogrammed  
to the default value of "0", and crystal drive strength bit, XDRV (0x06), must  
be set to the default value of "11".  
PRE-SCALER,FEEDBACK-DIVIDER,AND  
POST-DIVIDER  
Each PLL incorporates an 8-bit pre-scaler and a 12-bit feedback divider  
whichallowstheusertogeneratethreeuniquenon-integer-relatedfrequencies.  
For output banks OUT2-OUT4, each bank has a 10-bit post-divider. The  
following equation governs how the frequency on output banks OUT2-4 is  
calculated.  
FOUT = FIN * D (M)  
(Eq. 2)  
P * 2  
5
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
Feedback-Divider  
N[11:0]andA[3:0]arethebitsusedtoprogramthefeedback-dividerforPLL0(N0andA0)andPLL1(N1andA1). Ifspreadspectrumgenerationisenabled  
foreitherPLL0orPLL1,thenthe SS_OFFSET[5:0]bits(0x61,0x69)wouldbefactoredintotheoverallfeedbackdividervalue. SeetheSPREADSPECTRUM  
GENERATIONsectionformoredetailsonhowtoconfigurePLL0andPLL1whenspreadspectrumisenabled. ThetwoPLLscanalsobeconfiguredforfractional  
divideratios. SeeFRACTIONALDIVIDERformoredetails. ForPLL2,onlytheN[11:0]bits(N2)areusedtoprogramitsfeedbackdividerandthereisnospread  
spectrumgenerationandfractionaldividescapability. The12-bitfeedback-dividerintegervaluesrangefrom1to4095.  
The following equations govern how the feedback divider value is set. Note that the equations are different for PLL0/PLL1 and PLL2  
PLL0 and PLL1:  
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] * 1/64  
M = 2*N[11:0] + A[3:0] + 1 (spread spectrum disabled)  
(Eq. 3)  
(Eq. 4)  
A[3:0] = 0000 = -1  
= 0001 = 1  
= 0010 = 2  
= 0011 = 3  
.
.
.
= 1111 = 15  
Note: A[3:0] < (N[11:0] - 1), must be met when using A.  
PLL2:  
M = N[11:0]  
(Eq. 5)  
TheusercanachieveanevenoroddintegerdivideratioforbothPLL0andPLL1bysettingtheA[3:0]bitsaccordinglyanddisablingthespreadspectrum.  
AfractionaldividecanalsobesetforPLL0andPLL1byusingtheA[3:0]bitsinconjunctionwiththeSS_OFFSET[5:0]bits,whichisdetailedintheFRACTIONAL  
DIVIDERsection. NotethattheVCOhasafrequencyrangeof10MHzto1100MHz. To maintainlowjitter,itisbesttomaximizetheVCOfrequency. Forexample,  
if thereferenceclockis100MHzanda200MHzclockisrequired,toachievethebestjitterperformance,multiplythe100MHzby11togettheVCOrunningat  
thehighestpossiblefrequencyof1100MHzandthendivideitdowntoget200MHz. Orifthereferenceclockis25MHzand20MHzistherequiredclock,multiply  
the25MHzby40togettheVCOrunningat1000MHzandthendivideitdowntoget20MHz. IfNissetto'0x00', theVCOwillslewtotheminimumfrequency.  
Post-Divider  
Q[9:0] are the bits used to program the 10-bit post-dividers on output banks OUT2-4. OUT1 bank does not have a 10-bit post-divider or any other post-  
divide along its path. The 10-bit post-dividers will divide down the output banks' frequency with integer values ranging from 1 to 1023.  
Thereistheoptiontochoosebetweendisablingthepost-divider, utilizingadiv/1, adiv/2, orthe10-bitpost-dividerbyusingthePM[1:0]bits.. Eachbank,  
exceptforOUT1,hasasetofPMbits. Whendisablingthepost-divider,noclockwillappearattheoutputs,butwillremainpoweredon. Thevaluesarelisted  
inthetablebelow.  
P
00  
01  
PM[1:0]  
P Post-Divider  
disabled  
To Outputs  
VCO  
00  
01  
10  
11  
/2  
10  
11  
/2  
div/1  
/ (Q+2)  
div/2  
Q[9:0] + 2 (Eq. 6)  
PM[1:0]  
Post-Divider Diagram  
6
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
Notethattheactual10-bitpost-dividervaluehasa2addedtotheintegervalueQandtheoutputsareroutedthroughanotherdiv/2block. Thepost-divider  
shouldneverbedisabledunlesstheoutputbankwillneverbeusedduringnormaloperation. TheoutputfrequencyrangeforLVTTLoutputsarefrom4.9KHz  
to 200MHz. The output frequency range for LVPECL/LVDS outputs are from 4.9KHz to 500MHz.  
SPREADSPECTRUMGENERATION  
PLL0andPLL1supportspreadspectrumgenerationcapability,whichusershavetheoptionofturningonandoff. Spreadspectrumprofile,frequency,and  
spreadarefullyprogrammable(withinlimits). TheprogrammablespreadspectrumgenerationparametersareTSSC[3:0], NSSC[3:0], SS_OFFSET[5:0],  
SD[3:0],DITH,andX2bits. Thesebitsareinthememoryaddressrangeof0x60to0x67forPLL0and0x68to0x6FforPLL1. Thespreadspectrumgeneration  
on PLL0 & PLL1 can be enabled/disabled using the TSSC[3:0] bits. To enable spread spectrum, set TSSC > '0' and set NSSC, SD[3:0], SD[5:0], and the  
A[3:0] in the total M value accordingly. And to disable, set TSSC = '0'.  
TSSC[3:0]  
Thesebitsareusedtodeterminethenumberofphase/frequencydetectorcyclesperspreadspectrumcycle(ssc)steps. Themodulationfrequencycanbe  
calculatedwiththeTSSCbitsinconjunctionwiththeNSSCbits. ValidTSSCintegervaluesforthemodulationfrequencyrange from5to14.  
NSSC[3:0]  
Thesebitsareusedtodeterminethenumberofdelta-encodedsamplesusedforasinglequadrantof thespreadspectrumwaveform. Allfourquadrants  
ofthespreadspectrumwaveformaremirrorimagesofeachother. ThemodulationfrequencyisalsocalculatedbasedofftheNSSCbitsinconjunctionwiththe  
TSSC bits. Valid NSSC integer values range from 1 to 6.  
SS_OFFSET[5:0]  
ThesebitsareusedtoprogramthefractionaloffsetwithrespecttothenominalMintegervalue. Forcenterspread,theSS_OFFSETshouldbesetto'0'so  
thespreadspectrumwaveformisaboutthenominalM(Mnom)value. Fordownspread,theSS_OFFSET>'0'sothespreadspectrumwavformisaboutthe  
(Mideal-1=Mnom)value. Thedownspreadpercentagecanbethoughtofintermsofcenterspread. Forexample,adownspreadof-1%canalsobeconsidered  
as a center spread of ±0.5% but with Mnom shifted down by one and offset. The SS_OFFSET has integer values ranging from 0 to 63.  
SD[3:0]  
Thesebitsareusedtoshapetheprofileofthespreadspectrumwaveform. Thesearedelta-encodedsamplesofthewaveform. Therearetwelvesetsof  
SDsamplesforeachPLL. TheNSSCbitsdeterminehowmanyofthesesamplesareusedforthewaveform. Thesumofthesedelta-encodedsamples(sigma-  
delta-encodedsamples)determinetheamountofspreadandshouldnotexceed(63-SS_OFFSET). Themaximumspreadisinversely proportionaltothe  
nominalMintegervalue.  
DITH  
Thisbitisforditheringthesigma-delta-encodedsamples. Thiswillrandomizetheleast-significantbitoftheinputtothespreadspectrummodulator. Setthe  
bitto'1'toenabledithering.  
X2  
Thisbitwilldoublethetotalvalueofthesigma-delta-encoded-sampleswhichwillincreasetheamplitudeofthespreadspectrumwaveformbyafactoroftwo.  
WhenX2is'0', theamplituderemainsnominalbutifsetto'1', theamplitudeisincreasedbyx2.  
Thefollowingequationsgovernhowthespreadspectrumisset:  
TSSC = TSSC[3:0] + 2 (Eq. 7)  
NSSC = NSSC[3:0] * 2 (Eq. 8)  
SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 9)  
where SJ is the unencoded sample out of a possible 12 and SDK is the delta-encoded sample out of a possible 12.  
Amplitude = (2*N[11:0] + A[3:0] + 1) * Spread% / 100  
(Eq. 10)  
2
if 1 < Amp < 2, then set X2 bit to '1'.  
7
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
Modulation frequency:  
FPFD = FIN / D (Eq. 11)  
FVCO = FPFD * MNOM (Eq. 12)  
FSSC = FPFD / (4 * Nssc * Tssc)  
(Eq. 13)  
Spread:  
ΣΔ = SD0 + SD1 + SD2 + … + SD11  
the number of samples used depends on the NSSC value  
ΣΔ ≤ 63 - SS_OFFSET  
±Spread% =  
ΣΔ * 100  
64 * (2*N[11:0] + A{3:0} + 1)  
(Eq. 14)  
±Max Spread% / 100 = 1 / MNOM or 2 / MNOM (X2=1)  
Profile:  
WaveformstartswithSS_OFFSET, SS_OFFSET+SDJ, SS_OFFSET+SDJ+1, etc.  
Spread Spectrum Using Sinusoidal Profile  
8
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
Example  
FIN = 25MHz, FOUT = 100MHz, Fssc = 33KHz with center spread of ±2%. Find the necessary spread spectrum register settings.  
Sincethespreadiscenter,theSS_OFFSETcanbesetto'0'. SolveforthenominalMvalue;keepinmindthatthenominalMshouldbechosentomaximize  
the VCO. Start with D = 1, using Eq.10 and Eq.11.  
MNOM = 1100MHz / 25MHz = 44  
Using Eq.4, we arbitrarily choose N = 20, A = 3. Now that we have the nominal M value, we can determine TSSC and NSSC by using Eq.12.  
Nssc * Tssc = 25MHz / (33KHz * 4) = 190  
However, using Eq. 7 and Eq.8, we find that the closest value is when TSSC = 14 and NSSC = 6. Keep in mind to maximize the number of samples used  
toenhancetheprofileofthespreadspectrumwaveform.  
Tssc = 14 + 2 = 16  
Nssc = 6 * 2 = 12  
Nssc * Tssc = 192  
UseEq.14todeterminethevalueofthesigma-delta-encodedsamples.  
±2% = ΣΔ * 100  
64 * 44  
ΣΔ = 56.32  
Eitherroundupordowntothenearestintegervalue. Therefore,weendupwith56or57forsigma-delta-encodedsamples. Sincethesigma-delta-encoded  
samplesmustnotexceed63with SS_OFFSETsetto'0', 56or57iswellwithinthelimits. Itisthediscretionoftheuserto definetheshapeof theprofilethat  
isbettersuitedfortheintendedapplication.  
Using Eq.14 again, the actual spread for the sigma-delta-encoded samples of 56 and 57 are ±1.99% and ±2.02%, respectively.  
UseEq.10todetermineiftheX2bitneedstobeset;  
Amplitude = 44 * (1.99 or 2.02) / 100 = 0.44 < 1  
2
Therefore, the X2 = '0 '. The dither bit is left to the discretion of the user.  
The example above was of a center spread using spread spectrum. For down spread, the nominal M value can be set one integer value lower to 43.  
Note that the 5v9882T should not be programmed with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator.  
ThePLLloopbandwidthmustbeatleast10xthemodulationfrequencyalongwithhigherdamping(largerωuz)topreventthespreadspectrumfrombeingfiltered  
andreduceextraneousnoise. RefertotheLOOPFILTERsectionformoredetailonωuz.TheA[3:0]mustbeusedforspreadspectrum,evenifthetotalmultiplier  
value is an even integer.  
FRACTIONALDIVIDER  
There is the option for the feedback-divider to be programmed as a fractional divider for only PLL0 and PLL. By setting TSSC > '0' and SD bits to '0', the  
SS_OFFSETbitswoulddeterminethefractionaldividevalue.SeetheSPREADSPECTRUMGENERATIONsectionformoredetailsontheTSSC,SD,and  
SS_OFFSET bits. The following equation governs how the fractional divide value is set.  
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] *1/64  
9
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
Thespreadspectrumparameterssuchasthemodulationfrequencyandprofilewillnotbeenablednorwillithaveanyimpacton thePLLoutputwhenthe  
PLLisprogrammedforfractionaldivide.  
Thefollowingisanexampleofhowtosetthefractionaldivider.  
Example  
FIN = 20MHz, FOUT1 = 168.75MHz, FOUT2 = 350MHz  
Solving for 350MHz using Eq.2 and Eq.3 with PLL0 and spread spectrum off,  
350MHz = 20MHz * (M / D)  
P * 2  
Forbetterjitterperformance,keepDassmallaspossible  
350MHz * 2 = M = 35  
20MHz  
P
1
Therefore, we have D = 1, M = 35 (N = 16, A = 2) for PLL0 with P = 1 on output bank4 resulting in 350MHz.  
Solving for 168.75MHz with PLL1 and fractional divide enabled:  
168.75MHz = 20MHz * (M / D)  
P * 2  
168.75MHz * 2 = M = 16.875 or 33.75  
20MHz  
P
1
2
The 33.75 value is chosen to achieve the highest VCO frequency possible. Next step is to figure out the setting for the fractional divide using Eq.3.  
33.75 = 2*N + A + 1 + SS_OFFSET * 1/64  
Integer value 33 can be determined by N and A, thus leaving 0.75 left to be solved.  
2*N + A + 1 = 33  
SS_OFFSET = 64 * 0.75 = 48  
Therefore, we have D=1, M=33.75 (N=15, A=2, SS_OFFSET=48) for PLL1 with P=2 on an output bank resulting in 168.75MHz.  
Thefractionaldividercanbedeterminedifitisneededbyfollowingthestepsinthepreviousexample. Notethatthe5v9882T shouldnotbeprogrammed  
with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator. The A[3:0] must be used and set to be greater than  
'2'foramoreaccuratefractionaldivide.  
10  
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
LOOPFILTER  
TheloopfilterforeachPLLcanbeprogrammedtooptimizethejitterperformance. Thelow-passfrequencyresponseofthePLListhemechanismthatdictates  
thejittertransfercharacteristics. Theloopbandwidthcanbeextractedfromthejittertransfer. Anarrowloopbandwidthisgoodforjitterattenuationwhileawide  
loopbandwidthisbestforlowjittergeneration. ThespecificloopfiltercomponentsthatcanbeprogrammedaretheresistorviatheRZ[3:0]bits,polecapacitor  
via the CZ[3:0] bits, zero capacitor via the CP[3:0] bits, and the charge pump current via the IP[2:0] bits.  
Thefollowingequationsgovernhowtheloopfilterisset.  
VDD  
Ip  
UP  
To VCO  
From PFD  
DOWN  
Rz  
Ip  
Cp  
Cz  
Charge Pump and Loop Filter Configuration  
Resistor (Rz) = 0.3KΩ+ RZ[3:0] * 1KΩ  
(Eq. 15)  
Zero capacitor (Cz) = 6pF + CZ[3:0] * 27.2pF (Eq. 16)  
Pole capacitor (Cp) = 1.3pF + CP[3:0] * 0.75pF (Eq. 17)  
Charge pump current (Ip) = 5 * 2IP[2:0] μA  
(Eq. 18)  
Parameter  
Bits  
4
Step  
Min  
0.3  
6
Max  
15.3  
414  
Units  
K Ω  
pF  
RZ  
CZ  
C P  
IP  
1
4
27.2  
0.75  
2n  
4
1.3  
5
12.55  
640  
pF  
3
μA  
PLLloopfilterdesignisbeyondthescopeofthisdatasheet. Refertodesignproceduresfor3-ordercharge-pumpbasedPLLs. Forthesakeofsimplicity,  
thefastestandeasiestwaytocalculatethePLLloopbandwidth(Fc)giventheprogrammableloopfilterparametersisasfollows.  
PLL Loop Bandwidth:  
Charge pump gain (Kφ) = Ip / 2π  
(Eq. 19)  
VCO gain (KVCO) = 950MHz/V * 2π (Eq. 20)  
M=Totalmultipliervalue(SeethePRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERSsectionformoredetail)  
ωc = Rz * Kφ * KVCO * Cz (Eq. 21)  
M * (Cz + Cp)  
Fc = ωc / 2π  
(Eq. 22)  
Note, the phase/frequency detector frequency (FPFD) is typically seven times the PLL closed-loop bandwidth (Fc) but too high of a ratio will reduce your  
phasemarginthuscompromisingloopstability.  
11  
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
To determine if the loop is stable, the phase margin (ωm) would need to be calculated as follows.  
Phase Margin:  
ωz = 1 / (Rz * Cz)  
ωp = Cz + Cp  
Rz * Cz * Cp  
(Eq. 23)  
(Eq. 24)  
φm = (360 / 2π ) * [tan-1(ωc/ ωz) - tan-1(ωc/ ωp)] (Eq. 25)  
Toensurestabilityintheloop,thephasemarginisrecommendedtobe>60°buttoohighwillresultinthelocktimebeingexcessivelylong. Certainloopfilter  
parameterswouldneedtobecompromisedtonotonlymeetarequiredloopbandwidthbuttoalsomaintainloopstability.  
Example  
Fc = 150KHz is the desired loop bandwidth. The total M value is 850. The ratio of ωp/ωc should be at least 4. A rule of thumb that will help to aid the way,  
theωp/ωcratioshouldbeatleast4. GivenFcandM,anoptimalloopfiltersettingneedstobesolvedforthatwillmeetboththePLLloopbandwidthandmaintain  
loopstability.  
The charge pump gain should be relatively small as possible to achieve a low loop bandwidth.  
Ip = 40uA .  
Kφ* KVCO = 950MHz/V * 40uA = 38000A/Vs  
LoopBandwidths  
ωc = 2π * Fc = 9.42x105 s-1  
ωuz = ωp / ωc = 4  
ωc2 = ωp * ωz  
(Eq. 26)  
(Eq. 27)  
ωp = Cz + Cp = ωz (1 + Cz / Cp)  
Rz * Cz * Cp  
Solving for Cz, Cp, and Rz  
Knowing ωc = Rz * Kφ* KVCO * Cz and substituting in the equations from above,  
M * (Cz + Cp)  
Cz >>> Cp, therefore, we can easily derive Cp to be  
Cp = Kφ* KVCO  
= 12.60pF  
M * ωc2 * ωuz  
Similarly for Cz and Rz  
Cz = Kφ* KVCO * (ωuz2 - 1) = Cp * (ωuz2 - 1) = 189pF  
M * ωc2 * ωuz  
Rz =  
M * ωc * ωuz2  
= 22.48KΩ  
Kφ* KVCO * (ωuz2 - 1)  
Basedontheloopfilterparameterequationsfromabove,sincetherearenopossiblevaluesof12.60pFforCp,189pFforCz,and22.48KΩforRz,thenext  
possiblevalueswithintheloopfiltersettingsare12.55pF(CP[3:0]=1111),196.4pF(CZ[3:0]=0111),and15.3KΩ(RZ[3:0]=1111),respectively. Thisloopfilter  
settingwillyieldaloopbandwidthofabout102KHz. Thephasemarginmustbecheckedforloopstability.  
φm = (360 / 2π ) * [tan-1 (6.41x105 s-1 / 3.33x105 s-1) - tan-1 (6.41x105 s-1 / 5.54x106 s-1)] = 56°  
Althoughslightlybelow60°, thephasemarginwouldbeacceptablewithafairlystableloop.  
12  
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
CONFIGURINGTHEMULTI-PURPOSEI/Os  
The 5V9882T can operate in two distinct modes. These modes are controlled by the I2C_MFC pin. The general purpose I/O pins (GIN0 and GIN1) have  
differentusesdependingonthemodeofoperation. Themodesofoperationare:  
1)  
2)  
Manual Frequency Control (MFC) Mode for PLL0 Only  
I2CProgrammingMode  
AlongwiththeGINxpinsarealsoGOUTxoutputpinsthatcantakeupadifferentfunctiondependingonthemodeofoperation. Seetablebelowfordescription.  
Multi-Purpose Pins  
Other Signal Functions  
Signal Description  
I2Cserialdatainput/configselectinput  
I2C clock input / config select input  
GIN0  
GIN1  
SDAT  
SCLK  
EachPLL'sprogrammingregisterscanstoreuptofourdifferentDxandMxconfigurationsincombinationwithtwodifferent PconfigurationsinMFCmodes.  
The post-divider should never be disabled in any of the two P configurations unless the output bank will never be used during normal operation. The PLL's  
loopfiltersettingsalsohasfourdifferentconfigurationstostoreandselectfrom. ThiswillbeexplainedintheMODE1andMODE2sections. TheuseoftheGINx  
pinsinMFCmodecontroltheselectionoftheseconfigurations.  
MODE1 - Manual Frequency Control (MFC) Mode for PLL0 Only  
Inthismode,onlytheconfigurationofPLL0canbechangedduringoperation. TheGIN0andGIN1pinscontroltheselectionofuptofourdifferentD0,M0,  
P, RZ0, CZ0, PZ0, and IP0 stored configurations.  
TheoutputbankswilleachhavetwoPconfigurationsthatcanbeassociatedwitheachofthePLLconfigurations. EachofthetwoPconfigurationshasitsown  
setofPMbits(SeethePRE-SCALERS,FEEDBACK-DIVIDERS,POST-DIVIDERSsectionformoredetailonthePMbits). UsetheODIVbittochoosewhich  
post-dividerconfigurationtoassociatewithaspecificPLLconfiguration. Forexample,ifODIV0_CONFIG0=1,thenwhenConfig0isselectedQx[9:0]_CONFIG1  
isselectedasthepost-dividervaluetobeused. OrifODIV2_CONFIG3=0,thenwhenCONFIG7isselected,Qx[9:0]_CONFIG0isselected. Notethatthere  
is an ODIVx bit for each of the PLL configurations. In this way, the post-divider values can change with the configuration.  
Toenterthismode,I2C_MFCpinmustbeleftfloating.  
GIN1 Pin  
GIN0 Pin  
PLL0 Configuration Selection (Mode 1)  
0
0
Configuration 0: D0_CONFIG0, M0_CONFIG0, and ODIV0_CONFIG0  
0
0
0
1
0
1
Configuration 1: D0_CONFIG1, M0_CONFIG1, and ODIV0_CONFIG1  
Configuration 2: D0_CONFIG2, M0_CONFIG2, and ODIV0_CONFIG2  
Configuration 3: D0_CONFIG3, M0_CONFIG3, and ODIV0_CONFIG3  
MODE2 - I2C Programming Mode  
Inthismode,GIN0,GIN1,GIN3andGIN5becomeSDAT(I2Cdata),SCLK(I2Cclock),SUSPENDandCLK_SELsignalpins,respectively.TheoutputGOUT0  
willbecomeanindicatorforlossofPLLlock(LOSS_LOCK). GOUT1pinwillbecomeanindicatorforlossoftheselectedclock(LOSS_CLKIN). GIN2andGIN4  
are not available to users.  
To enter this mode, I2C_MFC pin must be set HIGH.  
Manual Frequency Control modes  
Multi-Purpose pins  
Mode1  
GIN0  
GIN1  
I2C  
GIN0  
GIN1  
SDAT  
SCLK  
NOTE:  
1. The PLL(s) will lock onto the primary clock and the manual switchover can be controlled  
by the PRIMCLK bit.  
13  
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
Understanding the GIN Signals  
Duringpowerup, thepartwillvirtuallybeinMFCmode2, therefore, thevaluesofGIN1andGIN0willbelatchedandusedforPLLconfigurationselection,  
regardlessofthestateoftheI2C_MFCpin. Thismeansthatwheninprogrammingmode,thePLLconfigurationcanonlybechangedbywritingdirectlytothe  
registersofthecurrentlyselectedconfiguration.WheninMFCmode,configuration0or1shouldbeselectedifyoudonotwanttochangeconfigurationswhen  
entering or leaving programming mode. The GIN pins should be held LOW during power up to select configuration0 as default.  
When not in programming mode, the GIN inputs directly control the selected configuration. The internal GINx signals can be individually disabled via  
programmingtheGINENbits(0x06). WhendisabledbysettingGINENxto"0",theGINxinputsmaybeleftfloating,butduringpowerup,theGINpinswillstill  
latch. DisabledinputsareinterpretedasLOWbytheinternalstatemachines. Evenifdisabled, GIN1andGIN0pinswillbeenabledifrequiredforI2C_MFC  
programmingfunctionswheninprogrammingmode.  
SHUTDOWN/SUSPEND/ENABLEOFOUTPUTS  
Thereare twoexternalpinsalongwithinternalbitsthatcontroltheenabling/disablingoftheoutputbanks. TheSHUTDOWN/SUSPEND/OEpin,alongwith  
theinternalbits,controltheenablinganddisablingoftheoutputbankandPLLs. Thispincanbeprogrammedtofunctionasanoutputenable,PLLpowerdown,  
or global shutdown. The polarity of the SHUTDOWN/OE signal pin can be programmed to be either active HIGH or LOW with the SP bit (0x1C). When SP  
is "0", the pin becomes active HIGH and when SP is "1", the pin becomes active LOW. The SH bit(0x1C) determines the function of the SHUTDOWN/OE  
signalpin. IfSHis"1",thesignalpinisSHUTDOWNand functionsasaglobalshutdown. ThiswilloverridetheOEx(0x1C), OSx(0x1D),andPLLSx(0x1E)  
bits. IfSHis"0",thesignalpinisOEandfunctionsasanenable/disableoftheoutputbanks. Ifusedasanoutputenable/disable,eachoutputbankcanbeindividually  
programmedtobeenabledordisabledbytheOEpin.bysettingOExbitsto"1". IftheOEsignalpinisasserted,theoutputbanksthathastheircorresponding  
OExbitsetto"1"willbedisabled.TheOEMxbitsdeterminetheoutputs'disablestate. Whensetto"0x"theoutputswillbetristated. Whensetto"10",theoutputs  
willbepulledlow. Whensetto"11",theoutputswillbepulledhigh. Invertedoutputswillbeparkedintheoppositestate. IftheOExbitsaresetto"0",thestates  
ofthecorrespondingoutputbankswillnotbeimpactedbythestateoftheOEpin. Toindividuallyenable/disableviaprogramminginsteadoftheOEpin,hard  
wire the OE pin to Vdd or GND (depending if it is active HIGH or LOW) as if to disable the outputs. Then toggle the OEx bits to either "0" to enable or "1" to  
disable.  
Whenthechipisinshutdown,theoutputs,thereferenceoscillator,andtheI2C_MFCpinarepowereddown. TheoutputswillbetristatedandtheI2C_MFC  
pinwillbesettoMFCmode(MIDlevel). Programmingwillnotbeallowed. TheGINxpinsandclockinputsremainoperational. ThePLLisnotdisabled. The  
SHUTDOWN pin must be deasserted in order to program the part or to resume operation.  
The SUSPEND function can be used to power down the PLL and/or output banks. Each output bank can be individually programmed to be enabled or  
disabledbytheSUSPENDsignalpinbysettingtheOSxbitsto"1". IftheSUSPENDsignalpinisasserted,theoutputbanksthathastheircorrespondingOSx  
bitsetto"1"willbepowereddownandoutputstristated. IftheOSxbitsaresetto"0",thestatesofthecorrespondingoutputbankswillnotbeimpactedbythe  
stateoftheSUSPENDpin. ThereisalsoanoptiontosuspendindividualPLLs bysettingthePLLSxbits(0x1E)to"1". ThiswillassociatethePLLtotheSUSPEND  
pin. When the pin is asserted, the corresponding PLLs will be powered down. It will not only power down the PLL but also any output bank associated with  
it. The PLLSx bits will override the OSx bits.  
In the event of a PLL suspend, the PLL must achieve lock again after it has been re-enabled, In the event of a global shutdown, the PLL does not have  
tore-acquirelocksinceitisnotdisabled.  
14  
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
MANUALFREQUENCYCONTROL(MFC)BLOCKDIAGRAM  
OUTPUT MUX  
PLL0  
Prescaler "D"  
CONFIG0  
VCO  
CONFIG1  
CONFIG2  
CONFIG3  
Output Divider P2  
CONFIG0  
CONFIG1  
Multiplier "M"  
CONFIG0  
CONFIG1  
CONFIG2  
CONFIG3  
ODIV  
ODIV  
ODIV  
ODIV  
ODIV  
Output Divider P3  
CONFIG0  
CONFIG1  
ODIV  
MFC = MODE  
NOTES:  
This illustration shows how the configurations are arranged for each PLL. There is an ODIV bit associated with each of the four configurations.  
-
-
GIN0 and GIN1 control four configurations from PLL0.  
ODIV from each configuration determines the selection of two Output Divider Px Configurations.  
15  
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
BLOCKDIAGRAMFORSHUTDOWN/OECONTROLSIGNAL  
OUT1  
OUT2  
PM2  
OE1  
01  
10  
11  
/2  
/2  
Q2  
+ 2  
OE2  
OUT3  
OUT3  
MUX  
01  
10  
11  
/2  
/2  
+ 2  
Q3  
PM3  
OE3  
PM4  
01  
10  
11  
/2  
OUT4  
/2  
+ 2  
Q4  
OE4  
OE MODE  
SHUTDOWN/OE  
Global SHUTDOWN Mode:  
Assert to Shutdown power on the outputs  
and 3-Level Pin  
SP  
SH  
NOTE:  
This illustration shows the internal logic behind the SHUTDOWN/OE pin and the bits associated with it.  
16  
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
POWER UP AND POWER SAVING FEATURES  
Ifaglobalshutdownisenabled, SHUTDOWN/SUSPEND/OEpinasserted, mostofthechipexceptforthePLLswillbepowereddown. Inordertohavea  
completepowerdownofthechip,thePLLsmustbepowereddownviatheSUSPENDfunctionorbysettingthepre-scalerbitsto'0x00'anddisabletheinternal  
GINxsignalsviatheenablebitsatmemoryaddress0x05. Notethattheregisterbitswillnotlosetheirstateintheeventofachippower-down. Theonlypossibility  
thattheregisterbitswilllosetheirstateisifthepartwaspower-cycled. Aftercomingoutof shutdownmode, thePLLswillrequiretimetorelock.  
Duringpowerup,thevaluesofGIN1andGIN0willbelatchedandusedforPLLconfigurationselection,regardlessofthestateoftheI2C_MFC pinandGINx  
beingdisabledviatheGINENxbits. TheGINpinsshouldbeheldLOWduringpoweruptoselectconfiguration0asdefault. Theoutputlevelswillbeatanundefined  
state during power up.  
Thepost-dividershouldneverbedisabledviaPMbitsafter powerup, orelseitwillrendertheoutputbankcompletelynon-functionalduringnormaloperation,  
(unlesstheoutputbankitselfwillnotbeusedatall).  
Duringpowerup, theVDD rampmustbemonotonic.  
CLOCK SWITCH MATRIX AND OUTPUTS  
AllthreePLLoutputsandthecurrentlyselectedinputclocksourceareroutedintoandthroughaclockmatrix.TheuserisabletoselectwhichPLLoutputand  
clock source is routed to which output bank via the SRCx bits (0x34, 0x35). Each output bank has its own set of SRC bits. Refer to the RAM table for more  
information. NotethatOUT1willbebasedoffthereferenceclockandtheonlyoutputbanktogglingunderthedefaultRAMbitsettings.  
Outputs1, 2and4are3.3VLVTTL. Outputsbank3canbe3.3VLVTTL, LVPECLorLVDS. TheLVDSandLVPECLselectionisdeterminedbytheLVLx  
bits(0x54,0x58). Eachoutputbankhasindividualslew-ratecontrol(SLEWxbits). Eachoutputcanbeindividuallyinverted(INVxbits);whenusingLVPECL  
orLVDSmodes,oneoftheoutputsineachLVPECL/LVDSpairshouldbeinverted. AlloutputbanksexceptOUT1haveaprogrammable10-bitpost-divider  
(Qxbits)withtwoselectabledivideconfigurationsviatheODIVxbits.  
Therearefoursettingsfortheprogrammableslewrate,0.7V/ns,1.25V/ns,2V/ns,and2.75V/ns;thisonlyappliestothe3.3VLVTTLoutputs. Thedifferential  
outputsarenotslewrateprogrammable inLVPECLorLVDSmodes. SLEW3mustbesetto2.75V/nsforstableoutputoperation. ForLVTTLoutputfrequency  
rateshigherthan100MHz,aslewrateof2V/nsorgreatershouldbeselected. Eachoutputcanalsobeenabled/disabled,whichisdescribedinthe'SHUTDOWN/  
SUSPEND/ENABLE of OUTPUTS' section. Refer to the RAM table for all binary settings.  
HIGH LEVEL BLOCK DIAGRAM FOR CONFIGURATION SCHEME  
I/Os  
I/Os  
Non-Volatile  
Configuration  
PLLs and Control  
Blocks  
EEPROM  
Cell  
Volatile  
Configuration  
I2C interface  
Programming  
Interface Block  
NOTE: Diagram does not represent actual number of die on chip.  
17  
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
PROGRAMMINGTHEDEVICE  
I2C may be used to program the 5V9882T. The I2C_MFC pin selects the I2C when HIGH.  
Hardwired Parameters for the IDT5V9882T  
Device (slave) address = 7'b1101010  
ID Byte for the 5V9882T = 8'b00010000  
I2C PROGRAMMING  
The 5v9882T is programmed through an I2C-Bus serial interface, and is an I2C slave device. The read and write transfer formats are supported. The first  
byteofdataafterawriteframetothecorrectslaveaddressisinterpretedastheregisteraddress;thisaddressauto-incrementsaftereachbytewrittenorread.  
Theframeformatsareshownbelow.  
SDA  
SCL  
SDA  
SCL  
P
S
Data Frame  
Data is stable during  
clock HIGH  
Stop  
Condition  
Start  
Condition  
Figure 1: Framing  
Each frame starts with a "Start Condition" and ends with an "End Condition". These are both generated by the Master device.  
MSB  
1
LSB  
1
0
1
0
1
0
R/W  
7-bit slave address  
R/W  
ACK from Slave  
0 - Slave will be written by master  
1 - Slave will be read by master  
The first byte transmitted by the Master is the Slave Address followed by the R/W bit.  
The Slave acknowledges by sending a "1" bit.  
Figure 2: First Byte Transmittetd on I2C Bus  
18  
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
EXTERNAL I2C INTERFACE CONDITION  
KEY:  
From Master to Slave  
FromMastertoSlave, butcanbeomittediffollowedbythecorrectsequence  
NormallydatatransferisterminatedbyaSTOPconditiongeneratedbytheMaster. However,iftheMasterstillwishestocommunicateonthebus,itcan  
generatearepeatedSTARTcondition, andaddressanotherSlaveaddresswithoutfirstgeneratingaSTOPcondition.  
From Slave to Master  
SYMBOLS:  
ACK - Acknowledge (SDA LOW)  
NACK - Not Acknowledge (SDA HIGH)  
Sr-RepeatedStartCondition  
S - START Condition  
P - STOP Condition  
PROGWRITE  
S
Address R/W ACK Command Code ACK Register ACK Data ACK  
7-bits 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit 8-bits 1-bit  
P
0
Figure 3: Progwrite Command Frame  
WritescancontinueaslongasaStopconditionisnotsentandeachbytewillincrementtheregisteraddress.  
PROGREAD  
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a known "read" register address  
priortoareadoperationbyissuingthefollowingcommand:  
S
Address R/W ACK Command Code ACK Register ACK  
7-bits 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit  
P
0
Figure 4a: Prior to Progread Command Set Register Address  
TheusercanignoretheSTOPconditionaboveandusearepeatedSTARTconditioninstead,straightaftertheslaveacknowledgementbit(i.e.,followedby  
theProgreadcommand):  
Data_1  
8-bits  
Data_2  
8-bits  
Data_last  
8-bits  
P
Sr Address R/W ACK ID Byte ACK  
7-bits 1-bit 8 bits  
ACK  
1-bit  
ACK  
1-bit  
NACK  
1-bit  
1
1-bit  
Figure 4b: Progread Command Frame  
Note:Figure4babovebyitselfistheProgreadcommandformat. TheIDbyteforthe5V9882Tis10hex. Eachbyterecievedincrementstheregisteraddress.  
19  
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
PROGSAVE  
PROGRESTORE  
P
S
Address R/W ACK Command Code ACK  
7-bits 1-bit 8-bits:xxxxxx10 1-bit  
P
S
Address R/W ACK Command Code ACK  
7-bits 1-bit 8-bits:xxxxxx01 1-bit  
0
0
NOTE:  
PROGWRITE is for writing to the 5v9882T registers.  
PROGREAD is for reading the 5v9882T registers.  
PROGSAVE is for saving all the contents of the 5v9882T registers to the EEPROM.  
PROGRESTORE is for loading the entire EEPROM contents to the 5v9882T registers.  
EEPROMINTERFACE  
TheIDT5V9882TcanalsostoreitsconfigurationinaninternalEEPROM. Thecontentsofthedevice'sinternalprogrammingregisterscanbesavedtothe  
EEPROMbyissuingasaveinstruction(ProgSave)andcanbeloadedbacktotheinternalprogrammingregistersbyissuingarestoreinstruction(ProgRestore).  
ToinitiateasaveorrestoreusingI2C,onlytwobytesaretransferred.TheDeviceAddressisissuedwiththeread/writebitsetto"0",followedbytheappropriate  
commandcode.ThesaveorrestoreinstructionexecutesaftertheSTOPconditionisissuedbytheMaster,duringwhichtimetheIDT5V9882Twillnotgenerate  
Acknowledgebits. The5V9882Twillacknowledgetheinstructionsafterithascompletedexecutionofthem. Duringthattime,theI2Cbusshouldbeinterpreted  
as busy by all other users of the bus.  
Inorderforthesaveandrestoreinstructionstofunctionproperly,theIDT5V9882Tmustnotbeinshutdownmode(SHUTDOWNpinasserted). Intheevent  
ofaninterruptofsomesortsuchasapowerdownofthepartinthemiddleofasaveorrestoreoperation,thecontentstoorfromtheEEPROMwillbepartially  
loaded, and a CRC error will be generated. The CERR bit (0x81) will be asserted to indicate that an error has occurred. The LOSS_LOCK signal will also  
beasserted.  
Onpower-upoftheIDT5V9882T,anautomaticrestoreisperformedtoloadtheEEPROMcontentsintotheinternalprogrammingregisters. Theauto-restore  
willnotfunctionproperlyifthedeviceisinshutdownmode(SHUTDOWNpinasserted). TheIDT5V9882Twillbereadytoacceptaprogramminginstruction  
onceitacknowledgesits7-bitI2Caddress.  
20  
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
I2C BUS DC CHARACTERISTICS  
Symbol  
VIH  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
V
Input HIGH Level  
InputLOWLevel  
Hysteresis of Inputs  
InputLeakageCurrent  
OutputLOWVoltage  
0.7 * VDD  
VIL  
0.3 * VDD  
V
VHYS  
IIN  
0.05 * VDD  
V
±1.0  
0.4  
μA  
V
VOL  
IOL = 3 mA  
I2C BUS AC CHARACTERISTICS FOR STANDARD MODE  
Symbol  
FSCLK  
tBUF  
Parameter  
Min  
0
Typ  
Max  
Unit  
KHz  
μs  
μs  
μs  
ns  
Serial Clock Frequency (SCLK)  
Bus free time between STOP and START  
SetupTime,START  
100  
4.7  
4.7  
4
tSU:START  
tHD:START  
tSU:DATA  
tHD:DATA  
tOVD  
HoldTime, START  
SetupTime,datainput(SDAT)  
HoldTime, datainput(SDAT)(1)  
Outputdatavalidfromclock  
Capacitive Load for Each Bus Line  
Rise Time, data and clock (SDAT, SCLK)  
Fall Time, data and clock (SDAT, SCLK)  
HIGH Time, clock (SCLK)  
LOW Time, clock (SCLK)  
250  
0
μs  
μs  
pF  
3.45  
400  
CB  
tR  
1000  
300  
ns  
tF  
ns  
tHIGH  
4
4.7  
4
μs  
μs  
μs  
tLOW  
tSU:STOP  
SetupTime, STOP  
NOTE:  
1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge  
of SCLK.  
I2C BUS AC CHARACTERISTICS FOR FAST MODE  
Symbol  
FSCLK  
tBUF  
Parameter  
Min  
0
Typ  
Max  
Unit  
KHz  
μs  
μs  
μs  
ns  
Serial Clock Frequency (SCLK)  
Bus free time between STOP and START  
SetupTime,START  
400  
1.3  
0.6  
0.6  
100  
0
tSU:START  
tHD:START  
tSU:DATA  
tHD:DATA  
tOVD  
HoldTime, START  
SetupTime,datainput(SDAT)  
HoldTime, datainput(SDAT)(1)  
Outputdatavalidfromclock  
Capacitive Load for Each Bus Line  
Rise Time, data and clock (SDAT, SCLK)  
Fall Time, data and clock (SDAT, SCLK)  
HIGH Time, clock (SCLK)  
LOW Time, clock (SCLK)  
μs  
μs  
pF  
0.9  
400  
300  
300  
CB  
tR  
20 + 0.1 * CB  
ns  
tF  
20 + 0.1 * CB  
ns  
tHIGH  
0.6  
1.3  
0.6  
μs  
μs  
μs  
tLOW  
tSU:STOP  
SetupTime, STOP  
NOTE:  
1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge  
of SCLK.  
21  
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
VDD  
Description  
Internal Power Supply Voltage  
Input Voltage  
Max  
-0.5 to +4.6  
-0.5 to +4.6  
-0.5 to VDD + 0.5  
150  
Unit  
V
VI  
V
VO  
Output Voltage(2)  
V
TJ  
Junction Temperature  
Storage Temperature  
°C  
°C  
TSTG  
–65 to +150  
NOTE:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. Not to exceed 4.6V.  
(1)  
CAPACITANCE (TA = +25°C, f = 1MHz, VIN = 0V)  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
CIN  
Input Capacitance  
—
4
—
pF  
Crystal Specifications  
XTAL_FREQ  
XTAL_MIN  
XTAL_MAX  
Crystal Frequency  
8
—
3.5  
50  
—
—
—
—
MHz  
pF  
Minimum Crystal Load Capacitance  
Maximum Crystal Load Capacitance  
Crystal Load Capacitance Resolution  
Voltage Swing (peak-to-peak, nominal)  
—
—
—
—
35.4  
0.125  
2.3  
pF  
XTAL_VPP  
V
NOTE:  
1. Capacitance levels characterized but not tested.  
RECOMMENDEDOPERATINGCONDITIONS  
Symbol  
Description  
Min.  
3
Typ.  
Max.  
Unit  
VDD  
PowerSupplyVoltageforLVTTL  
Power Supply Voltage for LVDS/LVPECL  
OperatingTemperature,Ambient  
MaximumLoadCapacitance(LVTTLonly)  
ExternalReferenceCrystal  
3.3  
3.3  
—
—
—
—
—
3.6  
3.465  
+85  
15  
V
3.135  
–40  
—
TA  
CLOAD_OUT  
FIN  
°C  
pF  
8
50  
MHz  
ExternalReferenceClock,Industrial  
1
400  
5
tPU  
Power-uptimeforallVDDstoreachminimumspecifiedvoltage  
(powerrampsmustbemonotonic)  
0.05  
ms  
22  
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
Symbol  
VIHH  
Parameter  
Test Conditions  
I2C_MFC 3-Level Input  
Min.  
Typ.  
—
Max.  
Unit  
V
Input HIGH Voltage Level(1)  
Input MID Voltage Level(1)  
InputLOWVoltageLevel(1)  
VDD – 0.4  
—
VIMM  
I2C_MFC 3-Level Input  
I2C_MFC 3-Level Input  
VIN = VDD  
VDD/2 – 0.2  
—
VDD/2 + 0.2  
V
VILL  
—
—
—
0.4  
200  
+50  
—
V
HIGH Level  
MID Level  
LOW Level  
—
I3  
3-LevelInputDCCurrent  
VIN = VDD/2  
–50  
–200  
—
—
μA  
mA  
mA  
VIN = GND  
—
IDD  
IDDS  
TotalPowerSupplyCurrent  
(3.3V Supply, VDD)  
2 outputs @166MHz; 4 outputs @ 83MHz  
2 outputs @20MHz; 4 outputs @ 40MHz  
120  
40  
—
—
—
Total Power Supply Current in  
ShutdownMode(2)  
GlobalShutdownMode  
—
2
—
(PLLs, dividers, outputs, etc. powereddown)  
NOTES:  
1. These inputs are normally wired to VDD, GND, or left floating. If these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and  
the PLL may require additional tAQ time before all datasheet limits are achieved.  
2. Dividers must reload reprogrammed values via power-on reset or terminal count reload in order to ensure low-power mode.  
DCELECTRICALCHARACTERISTICSFOR3.3VLVTTL(1)  
Symbol  
IOH  
Parameter  
Output HIGH Current  
OutputLOWCurrent  
Input Voltage HIGH  
InputVoltageLOW  
Test Conditions  
Min.  
12  
12  
2
Typ.  
24  
Max.  
—
Unit  
mA  
mA  
V
VOH = VDD - 0.5, VDD = 3.3V ± 0.3V  
VOL = 0.5V, VDD = 3.3V ± 0.3V  
IOL  
24  
—
VIH  
VIL  
—
—
—
—
—
—
—
0.8  
10  
V
IIH  
Input HIGH Current  
InputLOWCurrent  
VIN = VDD  
VIN = 0V  
—
μA  
μA  
μA  
IIL  
—
10  
IOZD  
OutputLeakageCurrent  
3-stateoutputs  
—
10  
NOTE:  
1. See RECOMMENDED OPERATING RANGE table.  
POWERSUPPLYCHARACTERISTICSFORLVTTLOUTPUTS  
Symbol  
Parameter  
Test Conditions  
REF = LOW  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current  
6
12  
mA  
Outputsenabled,Alloutputsunloaded  
VDD = Max., CL = 0pF  
IDDD  
Dynamic VDD Power Supply  
CurrentperOutput  
40  
60  
μA/MHz  
FREFERENCE CLOCK = 33MHz, CL = 15pf  
FREFERENCE CLOCK = 133MHz, CL = 15pf  
FREFERENCE CLOCK = 200MHz, CL = 15pf  
26  
80  
40  
ITOT  
Total Power VDD Supply Current  
120  
170  
mA  
112  
23  
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
DCELECTRICALCHARACTERISTICSFORLVDS  
Symbol  
VOT (+)  
VOT (-)  
Δ VOT  
VOS  
Parameter  
Min.  
247  
-247  
—
Typ.  
—
—
—
1.2  
—
9
Max  
454  
-454  
50  
Unit  
mV  
mV  
mV  
V
DifferentialOutputVoltagefortheTRUEbinarystate  
DifferentialOutputVoltagefortheFALSEbinarystate  
ChangeinVOT betweenComplimentaryOutputStates  
OutputCommonModeVoltage(OffsetVoltage)  
ChangeinVOS betweenComplimentaryOutputStates  
Outputs Short Circuit Current, VOUT+ or VOUT- = 0V or VDD  
DifferentialOutputsShortCircuitCurrent,VOUT+=VOUT-  
1.125  
—
1.375  
50  
Δ VOS  
IOS  
mV  
mA  
mA  
—
24  
IOSD  
—
6
12  
POWERSUPPLYCHARACTERISTICSFORLVDSOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
REF = LOW  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current  
68  
90  
mA  
Outputsenabled,Alloutputsunloaded  
VDD = Max., CL = 0pF  
IDDD  
Dynamic VDD Power Supply  
CurrentperOutput  
30  
45  
μA/MHz  
FREFERENCE CLOCK = 100MHz, CL = 5pf  
FREFERENCE CLOCK = 200MHz, CL = 5pf  
FREFERENCE CLOCK = 400MHz, CL = 5pf  
86  
130  
150  
190  
ITOT  
Total Power VDD Supply Current  
100  
122  
mA  
NOTES:  
1. Output banks 4 and 5 are toggling. Other output banks are powered down.  
2. The termination resistors are excluded from these measurements.  
DCELECTRICALCHARACTERISTICSFORLVPECL  
Symbol  
VOH  
Parameter  
Min.  
VDD - 1.2  
VDD - 1.95  
0.55  
Typ.  
—
Max  
VDD - 0.9  
VDD - 1.61  
0.93  
Unit  
V
Output Voltage HIGH, terminated through 50Ωtied to VDD - 2V  
OutputVoltageLOW, terminatedthrough50ΩtiedtoVDD -2V  
Peak to Peak Output Voltage Swing  
VOL  
—
V
VSWING  
—
V
POWERSUPPLYCHARACTERISTICSFORLVPECLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
REF = LOW  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current  
86  
110  
mA  
Outputsenabled,Alloutputsunloaded  
VDD = Max., CL = 0pF  
IDDD  
Dynamic VDD Power Supply  
CurrentperOutput  
35  
50  
μA/MHz  
FREFERENCE CLOCK = 100MHz, CL = 5pf  
FREFERENCE CLOCK = 200MHz, CL = 5pf  
FREFERENCE CLOCK = 400MHz, CL = 5pf  
120  
130  
140  
180  
190  
210  
ITOT  
Total Power VDD Supply Current  
mA  
NOTES:  
1. Output banks 4 and 5 are toggling. Other output banks are powered down.  
2. The termination resistors are excluded from these measurements.  
24  
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
ACTIMINGELECTRICALCHARACTERISTICS  
(SPREAD SPECTRUM GENERATION = OFF)  
Symbol  
fIN  
Parameter  
Test Conditions  
Min.  
1(1)  
Typ.  
—
Max  
400  
200  
500  
1200  
400  
40  
Unit  
MHz  
MHz  
InputFrequency  
OutputFrequency  
InputFrequencyLimit  
1/t1  
SingleEndedClockoutputlimit(LVTTL)  
DifferentialClockoutputlimit(LVPECL/LVDS)  
VCOoperatingFrequencyRange  
0.0049  
0.0049  
10  
0.35(1)  
0.03  
40  
—
—
fVCO  
fPFD  
fBW  
t2  
VCO Frequency  
PFD Frequency  
LoopBandwidth  
Input Duty Cycle  
Output Duty Cycle  
—
MHz  
MHz  
MHz  
%
PFDoperatingFrequencyRange  
—
Basedonloopfilterresistorandcapacitorvalues  
Duty Cycle for Input  
—
—
60  
t3  
Measured at VDD/2, FOUT ≤200MHz  
Measured at VDD/2, FOUT > 200MHz  
Single-EndedOutputclockriseandfalltime,  
20% to 80% of VDD (Output Load = 15pf)  
Single-EndedOutputclockriseandfalltime,  
20% to 80% of VDD (Output Load = 15pf)  
Single-EndedOutputclockriseandfalltime,  
20% to 80% of VDD (Output Load = 15pf)  
Single-EndedOutputclockriseandfalltime,  
20% to 80% of VDD (Output Load = 15pf)  
LVDS, 20% to 80%  
45  
—
55  
%
40  
—
60  
Slew Rate  
—
2.75  
—
SLEWx(bits) = 00  
Slew Rate  
—
—
—
2
—
—
—
t4(2)  
SLEWx(bits) = 01  
Slew Rate  
V/ns  
1.25  
0.75  
SLEWx(bits) = 10  
Slew Rate  
SLEWx(bits) = 11  
RiseTimes  
—
—
—
—
—
850  
850  
500  
500  
—
—
—
t5  
FallTimes  
ps  
RiseTimes  
LVPECL, 20% to 80%  
—
FallTimes  
—
t6  
t7  
t8  
Outputthree-stateTiming  
Timeforoutputtoenterorleavethree-statemode  
after SHUTDOWN/OE switches  
Peak-to-peakperiodjitter,  
150 +  
1/FOUTX  
150  
—
ns  
ps  
ps  
ClockJitter(3,7)  
OutputSkew(8)  
fPFD > 20MHz  
fPFD < 20MHz  
—
—
—
—
200  
—
CLKoutputsmeasuredatVDD/2  
Skewbetweenoutputtooutput onthesamebank  
(bank 4 and bank 5 only)(4, 5)  
150  
t9  
LockTime  
Locktime(9)  
PLLLockTimefromPower-up(6)  
—
—
10  
20  
20  
ms  
t10  
PLLLocktimefromshutdownmode  
100  
μs  
NOTES:  
1. Practical lower input frequency is determined by loop filter settings.  
2. A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher.  
3. Input frequency is the same as the output with all output banks running at the same frequency.  
4. Skew measured between all output pairs under identical input and output interfaces, same PLL and PLL multiplication and post divider value, transitions and load conditions  
on any one device.  
5. Skew measured between the cross points of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.  
6. Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.  
7. Guaranteed by design but not production tested.  
8. Outputs are aligned upon device power-on. If an output divider ratio is changed (via programming or Manual Frequency Control), then outputs are no longer guaranteed to  
be synchronized.  
9. Actual PLL lock time depends on the loop configuration.  
SPREADSPECTRUMGENERATIONSPECIFICATIONS  
Symbol  
fIN  
Parameter  
Description  
Min.  
1(1)  
Typ.  
Max  
400  
—
Unit  
MHz  
kHz  
InputFrequency  
Mod Freq  
InputFrequencyLimit  
—
33  
fMOD  
ModulationFrequency  
—
fSPREAD  
SpreadValue  
AmountofSpreadValue(Programmable)-DownSpread  
AmountofSpreadValue(Programmable)-CenterSpread  
-0.5, -1, -2.5, -3.5, -4  
-0.5 to +0.5  
%fOUT  
NOTE:  
1. Practical lower input frequency is determined by loop filter settings.  
25  
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
TEST CIRCUITS AND CONDITIONS(1)  
VDD  
CLKOUT  
CLOAD  
0.1 F  
OUTPUTS  
GND  
NOTE:  
1. All VDD pins must be tied together.  
Test Circuits for DC Outputs  
OTHER TERMINATION SCHEME (BLOCK DIAGRAM)  
CLOAD  
CLKOUT  
CLKOUT  
CLKOUT  
OUTPUTS  
GND  
OUTPUTS  
GND  
CLOAD  
RLOAD  
CLOAD  
LVDS: - 100Ω between differential outputs with 5pF  
LVTTL: -15pF for each output  
VDD-2V  
RLOAD  
CLOAD  
CLOAD  
CLKOUT  
OUTPUTS  
GND  
CLKOUT  
RLOAD  
VDD-2V  
LVPECL: - 50Ω to VDD-2V for each output with 5pF  
26  
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
RAM(PROGRAMMINGREGISTER)TABLES  
BIT #  
(Default Settings)  
BIT #  
Default  
ADDR  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Register  
DESCRIPTION  
Hex Value  
0x00  
0x01  
0x02  
0x03  
0x04  
Read-Only  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
01  
GINEN0 to GINEN5=GINx Pins Enable Bits, ("1"=Enable (Default), "0"=No Connect (Internal State will be "Low"));  
Address 0x04, Bits[7:1] are reserved and should bet set to "0".  
Address 0x05, Bits 7, 6 are reserved and should be set to "1'.  
0x05  
0x06  
C3  
GINEN1  
GINEN0  
XDRV=crystal drive strength ("00" = 1.4V, "01" = 2.3V, "10"= 3.2V pk-pk swing typical, "11"=XTAL_IN with external clock-default); When  
"11", XTALCAP[7:0] value must also be set to "0".  
XDRV[1:0]  
0
0
1
1
0
0
0
0
30  
Bits 7,6, 3, 2, 1, 0 are reserved and should be set to "0"  
XTAL load cap = 3.5pF+ (0.125 x XTALCAP[7:0]) , 3.5pF to 35.4pF; Each XTAL pin to GND;  
(For example, "00000001"=0.125pF, "00000010"=0.25pF, "00000100"=0.5pF); Default = "00000000";  
0x07  
0x08  
0x09  
0x0A  
0x0B  
0x0C  
0x0D  
0x0E  
0x0F  
0x10  
0x11  
0x12  
0x13  
0x14  
0x15  
0x16  
0x17  
0x18  
0x19  
0x1A  
0x1B  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
XTALCAP[7:0]  
IP0[2:0]_CONFIG0  
IP0[2:0]_CONFIG1  
IP0[2:0]_CONFIG2  
IP0[2:0]_CONFIG3  
RZ0[3:0]_CONFIG0  
RZ0[3:0]_CONFIG1  
RZ0[3:0]_CONFIG2  
RZ0[3:0]_CONFIG3  
CZ0[3:0]_CONFIG0  
CZ0[3:0]_CONFIG1  
CZ0[3:0]_CONFIG2  
CZ0[3:0]_CONFIG3  
ODIV0_CONFIG0  
ODIV0_CONFIG1  
ODIV0_CONFIG2  
ODIV0_CONFIG3  
PLL0 LOOP FILTER SETTING  
Loop Filter Values for PLL0 - For 4 Configurations (Default value is '0');  
CONFIG0 will be selected if GINx are disabled and operating in MFC mode  
ODIV0_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated with  
PLL0; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;  
Resistor = 0.3KΩ + RZ0[3:0] * 1KΩ, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);  
Zero capacitor = 6pF + CZ0[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);  
Pole capacitor = 1.3pF + CP0[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)  
Charge pump current = 5 * 2^IP0[2:0] μA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;  
CP0[3:0]_CONFIG0  
CP0[3:0]_CONFIG1  
CP0[3:0]_CONFIG2  
CP0[3:0]_CONFIG3  
D0[7:0]_CONFIG0  
D0[7:0]_CONFIG1  
D0[7:0]_CONFIG2  
D0[7:0]_CONFIG3  
N0[7:0]_CONFIG0  
N0[7:0]_CONFIG1  
N0[7:0]_CONFIG2  
N0[7:0]_CONFIG3  
PLL0 INPUT DIVIDER D0 SETTING  
PLL0 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');  
PLL0 MULTIPLIER SETTING  
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.  
N0[11:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');  
A0[3:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');  
SSC_OFFSET0[5:0] - Spread Spectrum Fractional Multiplier Offset Value. See Spread Spectrum Settings in register address range 0x60-  
0x67  
A0[3:0]_CONFIG0  
A0[3:0]_CONFIG1  
A0[3:0]_CONFIG2  
A0[3:0]_CONFIG3  
N0[11:8]_CONFIG0  
N0[11:8]_CONFIG1  
N0[11:8]_CONFIG2  
N0[11:8]_CONFIG3  
Total Multiplier Value M0 = 2 * N0[11:0] + A0 + 1 + SS_OFFSET0 * 1/64  
When A0[3:0] = 0 and spread spectrum disabled, M0= 2 * N0[11:0];  
When A0[3:0] > 0 and spread spectrum disabled, M0 = 2 * N0[11:0] + A0 + 1;  
(Note: A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);  
SP=Shutdown/OE Polarity for SHUTDOWN/OE signal pin, ("0"= Active High (Default), "1"= Active Low);  
OEx=Output Disable Function for OUTx, ("1"=OUTx disabled based on OE pin (Default for OUT2-6, Disable mode is defined by OEMx  
bits), "0"= Outputs enabled and no association with OE pin (Default));  
0x1C  
0x1D  
0x1E  
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00  
40  
00  
SP  
SH  
OE4  
OS4  
OE3  
OS3  
OE2  
OS2  
OE1  
OS1  
OSx=Output Power Suspend function for OUTx, ("1"=OUTx will be suspended on GIN3/SUSPEND pin (MFC="1"), "0"= Always Enabled  
(Default));  
PLLSx=Determines which PLLx to suspend when GIN3 is programmed to be used as SUSPEND, It suspends all the outputs associated  
with that PLL, ("1"= suspends based on SUSPEND pin, "0"= PLL enabled and no association with SUSPEND pin (Default)); It over-rides  
OSx bits;  
OKC  
SH=Determines the function of the SHUTDOWN/OE signal pin. ("1"=Global Shutdown; this over-rides OEx and OSx bits, "0"=Ouput  
Enable/Disable (Default))  
OKC=clock OK count, "0"=8 cycles, "1"=1024 cycles (Default) of Input Clocks for Revertive Switchover Mode:  
Address 0x1D, Bit 7; Address 0x1E, Bits [7:3] are reserved and should be set to "0"  
PLLS2  
PLLS1  
PLLS0  
27  
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
RAM(PROGRAMMINGREGISTER)TABLES  
BIT #  
(Default Settings)  
BIT #  
Default  
ADDR  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Register  
DESCRIPTION  
Hex Value  
Configuring Output OUT1  
INV1=Output Inversion for OUT1 ("0"= Non-Invert (Default), "1"=Invert);  
SLEW1=Slew Rate Settings for OUT1 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);  
OEM1= Output Enable Mode for OUT1 output, when used with OE1 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park Low,  
"11"=Park High);  
OEM1[1;0]  
SLEW1[1:0]  
0x1F  
0
0
0
0
0
0
0
0
00  
INV1  
Address 0x1F, Bits 3, 1, 0 are reserved and should be set to "0"  
IP1[2:0]_CONFIG0  
IP1[2:0]_CONFIG1  
IP1[2:0]_CONFIG2  
IP1[2:0]_CONFIG3  
RZ1[3:0]_CONFIG0  
RZ1[3:0]_CONFIG1  
RZ1[3:0]_CONFIG2  
RZ1[3:0]_CONFIG3  
CZ1[3:0]_CONFIG0  
CZ1[3:0]_CONFIG1  
CZ1[3:0]_CONFIG2  
CZ1[3:0]_CONFIG3  
0x20  
0x21  
0x22  
0x23  
0x24  
0x25  
0x26  
0x27  
0x28  
0x29  
0x2A  
0x2B  
0x2C  
0x2D  
0x2E  
0x2F  
0x30  
0x31  
0x32  
0x33  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
ODIV1_CONFIG0  
ODIV1_CONFIG1  
ODIV1_CONFIG2  
ODIV1_CONFIG3  
PLL1 LOOP FILTER SETTING  
Loop Filter Values for PLL1 - For 4 Configurations (Default value is '0');  
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.  
ODIV1_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated with  
PLL1; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;  
Resistor = 0.3KΩ + RZ1[3:0] * 1KΩ, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);  
Zero capacitor = 6pF + CZ1[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);  
Pole capacitor = 1.3pF + CP1[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)  
Charge pump current = 5 * 2^IP1[2:0] μA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;  
CP1[3:0]_CONFIG0  
CP1[3:0]_CONFIG1  
CP1[3:0]_CONFIG2  
CP1[3:0]_CONFIG3  
D1[7:0]_CONFIG0  
D1[7:0]_CONFIG1  
D1[7:0]_CONFIG2  
D1[7:0]_CONFIG3  
N1[7:0]_CONFIG0  
N1[7:0]_CONFIG1  
N1[7:0]_CONFIG2  
N1[7:0]_CONFIG3  
PLL1 INPUT DIVIDER D1 SETTING  
PLL1 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');  
PLL1 MULTIPLIER SETTING  
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.  
N1[11:0]_CONFIGx - Part of PLL1 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');  
A1[3:0]_CONFIGx - Part of PLL1 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');  
SSC_OFFSET1[5:0] - Spread Spectrum Fractional Multiplier Offset Value. See Spread Spectrum Settings in register address range 0x68-  
0x6F  
A1[3:0]_CONFIG0  
A1[3:0]_CONFIG1  
A1[3:0]_CONFIG2  
A1[3:0]_CONFIG3  
N1[11:8]_CONFIG0  
N1[11:8]_CONFIG1  
N1[11:8]_CONFIG2  
N1[11:8]_CONFIG3  
Total Multiplier Value M1 = 2 * N1[11:0] + A1 + 1 + SS_OFFSET1 * 1/64  
When A1[3:0] = 0 and spread spectrum disabled, M1= 2 * N1[11:0];  
When A1[3:0] > 0 and spread spectrum disabled, M1 = 2 * N1[11:0] + A1 + 1 ;  
(Note: A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);  
SRC2[1:0]  
SRC1[1:0]  
0x34  
0x35  
0
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
46  
55  
Bit [3:0] is reserved and should be set to "0".  
SRCx[1:0]=Input Source Selection for Output Dividers "Qx" blocks ("00"=Selected Input CLK, "01"=PLL0, "10"=PLL1, "11"=PLL2);  
Default on SRC1 is the selected input clock. Default on SRC2-6 is PLL0 which will be powered down.  
SRC4[1:0]  
SRC3[1:0]  
0x36  
0x37  
0x38  
0x39  
0x3A  
0x3B  
0x3C  
0x3D  
0x3E  
0x3F  
Read-Only  
IP2[2:0]_CONFIG0  
RZ2[3:0]_CONFIG0  
RZ2[3:0]_CONFIG1  
RZ2[3:0]_CONFIG2  
RZ2[3:0]_CONFIG3  
CZ2[3:0]_CONFIG0  
CZ2[3:0]_CONFIG1  
CZ2[3:0]_CONFIG2  
CZ2[3:0]_CONFIG3  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00  
00  
00  
00  
00  
00  
00  
00  
ODIV2_CONFIG0  
ODIV2_CONFIG1  
ODIV2_CONFIG2  
ODIV2_CONFIG3  
IP2[2:0]_CONFIG1  
IP2[2:0]_CONFIG2  
IP2[2:0]_CONFIG3  
PLL2 LOOP FILTER SETTING  
Loop Filter Values for PLL2 - For 4 Configurations (Default value is '0');  
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.  
ODIV2_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated with  
PLL2; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;  
Resistor = 0.3KΩ + RZ2[3:0] * 1KΩ, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);  
Zero capacitor = 6pF + CZ2[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);  
Pole capacitor = 1.3pF + CP2[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)  
Charge pump current = 5 * 2^IP2[2:0] μA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;  
CP2[3:0]_CONFIG0  
CP2[3:0]_CONFIG1  
CP2[3:0]_CONFIG2  
CP2[3:0]_CONFIG3  
28  
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
RAM(PROGRAMMINGREGISTER)TABLES  
BIT #  
(Default Settings)  
BIT #  
Default  
ADDR  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DESCRIPTION  
Register  
Hex Value  
D2[7:0]_CONFIG0  
D2[7:0]_CONFIG1  
D2[7:0]_CONFIG2  
D2[7:0]_CONFIG3  
N2[7:0]_CONFIG0  
N2[7:0]_CONFIG1  
N2[7:0]_CONFIG2  
N2[7:0]_CONFIG3  
0x40  
0x41  
0x42  
0x43  
0x44  
0x45  
0x46  
0x47  
0x48  
0x49  
0x4A  
0x4B  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
PLL2 INPUT DIVIDER D2 SETTING  
PLL2 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');  
PLL2 MULTIPLIER SETTING  
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.  
N2[11:0]_CONFIGx - Part of PLL2 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');  
Total Multiplier Value M2 = N2;  
N2[11:8]_CONFIG0  
N2[11:8]_CONFIG1  
N2[11:8]_CONFIG2  
N2[11:8]_CONFIG3  
Bits [7:4] in addresses 0x48, 0x49, 0x4A, and 0x4B are reserved and should be set to "0"  
Configuring Output OUT2  
INV2=Output Inversion for OUT2 ("0"= Non-Invert (Default), "1"=Invert);  
OEM2[1:0]  
SLEW2[1:0]  
0x4C  
0x4D  
0x4E  
0x4F  
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
00  
BB  
00  
00  
INV2  
SLEW2=Slew Rate Settings for OUT2 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);  
OEM2= Output Enable Mode for OUT2output, when used with OE2 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park Low,  
"11"=Park High);  
Q2[x:x]=Output Divider "Q2" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;  
PM2[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));  
(Note: To enable OUT2, PM2 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)  
Q2[1:0]_CONFIG1  
PM2[1:0]_CONFIG1  
Q2[1:0]_CONFIG0  
PM2[1:0]_CONFIG0  
Q2[9:2]_CONFIG0  
Q2[9:2]_CONFIG1  
Address 0x4C, Bits 3, 1, 0 are reserved and should be set to "0"  
0x50  
0x51  
0x52  
0x53  
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
00  
00  
00  
00  
Reserved  
Configuring Output OUT3  
INV3_1=Output Inversion for /OUT3 ("0"= Invert , "1"=Non-Invert (Default));  
INV3_0=Output Inversion for OUT3 ("0"= Invert , "1"=Non-Invert (Default));  
SLEW3=Slew Rate Settings for OUT3 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);  
OEM3= Output Enable Mode for OUT3 output, when used with OE3 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park Low,  
"11"=Park High);  
LVL3=Output IO Standard Selection, ("00"=LVTTL (Default), "01"=LVDS, "10"=LVPECL, "11"=Reserved);  
Q3[x:x]=Output Divider "Q3" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;  
PM3[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));  
(Note: To enable OUT3, PM3 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)  
OEM3[1:0]  
SLEW3[1:0]  
LVL3[1:0]  
0x54  
0x55  
0x56  
0x57  
0x58  
0x59  
0x5A  
0x5B  
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0C  
BB  
00  
00  
08  
BB  
00  
00  
INV3_1  
INV3_0  
Q3[1:0]_CONFIG1  
PM3[1:0]_CONFIG1  
Q3[1:0]_CONFIG0  
PM3[1:0]_CONFIG0  
Q3[9:2]_CONFIG0  
Q3[9:2]_CONFIG1  
When using LVPECL or LVDS outputs, SLEW3 must be set to "00".  
Configuring Output OUT4  
OEM4[1:0]  
SLEW4[1:0]  
INV4_0  
INV4_1=Output Inversion for /OUT4 ("0"= Invert, "1"=Non-Invert (Default));  
INV4_0=Output Inversion for OUT4 ("0"= Invert, "1"=Non-Invert (Default));  
SLEW4=Slew Rate Settings for OUT4 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);  
OEM4= Output Enable Mode for OUT4 output, when used with OE4 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park Low,  
"11"=Park High);  
Q4[1:0]_CONFIG1  
PM4[1:0]_CONFIG1  
Q4[1:0]_CONFIG0  
PM4[1:0]_CONFIG0  
Q4[x:x]=Output Divider "Q4" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;  
PM4[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));  
(Note: To enable OUT4, PM4 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)  
Q4[9:2]_CONFIG0  
Q4[9:2]_CONFIG1  
When using LVPECL or LVDS outputs, SLEW4 must be set to "00".  
0x5C  
0x5D  
0x5E  
0x5F  
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
00  
00  
00  
00  
Reserved  
29  
IDT5V9882T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
RAM(PROGRAMMINGREGISTER)TABLES  
BIT #  
(Default Settings)  
BIT #  
Default  
ADDR  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DESCRIPTION  
Register  
Hex Value  
TSSC0[3:0]  
X2_0  
NSSC0[3:0]  
0x60  
0x61  
0x62  
0x63  
0x64  
0x65  
0x66  
0x67  
0x68  
0x69  
0x6A  
0x6B  
0x6C  
0x6D  
0x6E  
0x6F  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
SS_OFFSET0[5:0]  
DITH0  
SD0[3:0][1]  
SD0[3:0][3]  
SD0[3:0][5]  
SD0[3:0][7]  
SD0[3:0][9]  
SD0[3:0][11]  
TSSC1[3:0]  
X2_1  
SD0[3:0][0]  
SPREAD SPRECTRUM SETTINGS FOR PLL0  
SD0[3:0][2]  
SD0[3:0][4]  
SD0[3:0][6]  
SD0[3:0][8]  
SS_OFFSET0=SS Fractional Offset/ First Sample (Unsigned);  
TSSC0=# of PFD Cycles Per SS Cycle Step, TSSC="0000" for SSC off (Default);  
NSSC0=# of SS Samples to Use from SS Memory (Default is "0");  
DITH0=LSB DITHER on Σ, ("1"=dither on, "0"=off (Default));  
X2_0=ΣΔ output x2, ("1"=x2, "0"=normal (Default));  
SD0=Delta-encoded samples (unsigned); Waveform start with SS_OFFSET0, then SS_OFFSET0+SD0[0], etc. (Default is "0");  
SD0[3:0][10]  
NSSC1[3:0]  
SS_OFFSET1[5:0]  
DITH1  
SD1[3:0][1]  
SD1[3:0][3]  
SD1[3:0][5]  
SD1[3:0][7]  
SD1[3:0][9]  
SD1[3:0][11]  
SD1[3:0][0]  
SD1[3:0][2]  
SD1[3:0][4]  
SD1[3:0][6]  
SD1[3:0][8]  
SD1[3:0][10]  
SPREAD SPRECTRUM SETTINGS FOR PLL1  
SS_OFFSET1=SS Fractional Offset/ First Sample (Unsigned);  
TSSC1=# of PFD Cycles Per SS Cycle Step, TSSC="0000" for SSC off (Default);  
NSSC1=# of SS Samples to Use from SS Memory (Default is "0");  
DITH1=LSB DITHER on ΣΔ, ("1"=dither on, "0"=off (Default));  
X2_1=ΣΔ output x2, ("1"=x2, "0"=off (Default));  
SD1=Delta-encoded samples (unsigned); Waveform start with SS_OFFSET1, then SS_OFFSET1+SD1[0], etc. (Default is "0");  
0x70  
0x71  
0x72  
0x73  
0x74  
0x75  
0x76  
0x77  
0x78  
0x79  
0x7A  
0x7B  
0x7C  
0x7D  
0x7E  
0x7F  
0x80  
Read-Only  
CRC error in EEPROM  
CERR = CRC error bit indicator ("1`" = CRC error)  
0x81  
CERR  
Read-Only  
Read-Only  
0x82  
0x83  
0x84  
0x85  
0x86  
0x87  
0x88  
30  
IDT5V9882T  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
ORDERINGINFORMATION  
IDT XXXXX  
Device Type  
XX  
X
Package Process  
Industrial (-40°C to +85°C)  
I
Thin Shrink Small Outline Package- Green  
PGG  
5V9882T 3.3V EEPROM Programmable Clock Generator  
CORPORATE HEADQUARTERS  
for SALES:  
for Tech Support:  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
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