IDT5V994JG [IDT]
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32;
| 型号： | IDT5V994JG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32 时钟驱动器 |
| 文件： | 总9页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V PROGRAMMABLE
IDT5V994
SKEW PLL CLOCK DRIVER
TURBOCLOCK™ PLUS
FEATURES:
DESCRIPTION
• Ref input is 5V tolerant
TheIDT5V994isahighfanout3.3VPLLbasedclockdriverintendedfor
highperformancecomputinganddata-communicationsapplications.Akey
featureoftheprogrammableskewistheabilityofoutputstoleadorlagthe
REFinputsignal. TheIDT5V994haseightprogrammableskewoutputsin
fourbanksof2.Skewiscontrolledby3-levelinputsignalsthatmaybehard-
wired to appropriate HIGH-MID-LOW levels.
• 4 pairs of programmable skew outputs
• Low skew: 200ps same pair, 250ps all outputs
• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
• Input frequency: 17.5MHz to 133MHz
• Output frequency: 17.5MHz to 133MHz
• 2x, 4x, 1/2, and 1/4 outputs (of VCO frequency)
• 3-level inputs for skew control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
WhenthesOEpinisheldlow,alltheoutputsaresynchronouslyenabled.
However, if sOE is held high, all the outputs except 3Q0 and 3Q1 are
synchronously disabled.
Furthermore, whenthePEisheldhigh, alltheoutputsaresynchronized
with the positive edge of the REF clock input. When PE is held low, all the
outputs are synchronized with the negative edge of REF. The IDT5V994
has LVTTL outputs with 12mA balanced drive outputs.
• Low Jitter: <200ps cycle-to-cycle
• Available in PLCC and TQFP packages
FUNCTIONALBLOCKDIAGRAM
sOE
1Q0
Skew
Select
1Q1
3
3
1F1:0
PE TEST
2Q0
2Q1
Skew
Select
3
3
3
3
REF
PLL
2F1:0
3F1:0
4F1:0
FB
3Q0
3Q1
Skew
Select
3
4Q0
4Q1
Skew
Select
3
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
AUGUST 2002
1
c
2002 Integrated Device Technology, Inc.
DSC 5828/4
IDT5V994
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKPLUS
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATIONS
32 31 30 29 28 27 26
25
4
3
2
1
32 31 30
2F0
3F1
4F0
5
6
29
28
27
26
25
24
23
22
21
3F1
4F0
1
2
3
4
5
6
7
8
sOE
1F1
24
23
22
21
20
19
18
17
sOE
1F1
4F1
7
4F1
1F0
1F0
PE
8
PE
VDDQ
1Q0
1Q1
GND
GND
VDDQ
1Q0
1Q1
GND
GND
VDDQ
4Q1
4Q0
GND
GND
9
VDDQ
4Q1
4Q0
GND
10
11
12
13
14 15 16 17 18 19 20
9
10 11 12 13 14 15
16
PLCC
TQFP
TOP VIEW
TOP VIEW
ABSOLUTEMAXIMUMRATINGS(1)
PROGRAMMABLESKEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit tU which is of the
order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF1:0 control pins. In order
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF1:0 control pins.
Symbol
Description
Max
V
Unit
VDDQ, VDD Supply Voltage to Ground–0.5 to +4.6
VI
DC Input Voltage
–0.5 to VDD+0.5
–0.5 to +5.5
0.8
V
V
REF Input Voltage
Maximum Power Dissipation, TA = 85°C
Storage Temperature Range
W
°C
TSTG
–65 to +150
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description
Typ.
Max.
Unit
CIN
InputCapacitance
5
7
pF
NOTE:
1. Capacitance applies to all inputs except TEST, FS, and nF[1:0].
2
IDT5V994
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKPLUS
PINDESCRIPTION
Pin Name
REF
Type
IN
Description
ReferenceClockInput
FeedbackInput
FB
IN
TEST(1)
IN
WhenMIDorHIGH, disablesPLL(exceptforconditionsofNote1). REFgoestoalloutputs. SkewSelections(SeeControlSummary
Table)remainineffect. SetLOWfornormaloperation.
sOE(1)
IN
IN
SynchronousOutputEnable. WhenHIGH, itstopsclockoutputs(except3Q0 and3Q1)inaLOWstate-3Q0 and3Q1maybeusedas
the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act as output disable
controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation.
PE
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference
clock.
nF[1:0]
nQ[1:0]
VDDQ
VDD
IN
3-levelinputsforselecting1of9skewtapsorfrequencyfunctions
Fourbanksoftwooutputswithprogrammableskew
Powersupplyforoutputbuffers
OUT
PWR
PWR
PWR
Powersupplyforphaselockedloopandotherinternalcircuitry
Ground
GND
NOTE:
1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in
effect unless nF[1:0] = LL.
EXTERNALFEEDBACK
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
By providing external feedback, the IDT5V994 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
PROGRAMMABLESKEWRANGEANDRESOLUTIONTABLE
Comments
TimingUnitCalculation(tU)
VCOFrequencyRange(FNOM)(1,2)
SkewAdjustmentRange(2)
MaxAdjustment:
1/(16 x FNOM)
70 to 133MHz
±5.36ns
±135°
ns
PhaseDegrees
% of Cycle Time
±37.5%
Example 1, FNOM = 80MHz
Example 2, FNOM = 100MHz
Example 3, FNOM = 133MHz
tU = 0.78ns
tU = 0.63ns
tU = 0.47ns
NOTES:
1. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs
will be FNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication
by using a divided output as the FB input. Using the nF[1:0] inputs allows a different method for frequency multiplication (see Control Summary Table for Feedback Signals).
2. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.
3
IDT5V994
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKPLUS
INDUSTRIALTEMPERATURERANGE
CONTROLSUMMARYTABLEFORFEEDBACKSIGNALS
nF1:0
LL(1)
LM
Skew (Pair #1, #2)
Skew (Pair #3)
Divide by 2
–6tU
Skew (Pair #4)
Divide by 2
–6tU
–4tU
–3tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
MM
M H
HL
Zero Skew
1tU
Zero Skew
2tU
Zero Skew
2tU
2tU
4tU
4tU
H M
H H
3tU
6tU
6tU
Inverted(2)
4tU
Divide by 4
NOTES:
1. LL disables outputs if TEST = MID and sOE = HIGH.
2. When pair #4 is set to HH (inverted), sOE disables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW.
RECOMMENDEDOPERATINGRANGE
Symbol
VDD/VDDQ
TA
Description
Min.
3
Typ.
3.3
Max.
3.6
Unit
V
Power Supply Voltage
AmbientOperatingTemperature
-40
+25
+85
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Conditions
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
Min.
Max.
Unit
V
VIH
Input HIGH Voltage
2
—
—
0.8
VIL
InputLOWVoltage
V
VIHH
VIMM
VILL
IIN
Input HIGH Voltage(1)
InputMIDVoltage(1)
InputLOWVoltage(1)
InputLeakageCurrent
(REF, FB Inputs Only)
VDD−0.6
VDD/2−0.3
—
—
V
3-Level Inputs Only
VDD/2+0.3
0.6
V
3-Level Inputs Only
V
VIN = VDD or GND
−5
+5
µA
VDD = Max.
VIN = VDD
HIGH Level
MID Level
LOW Level
—
−50
−200
−100
—
+200
+50
—
I3
3-LevelInputDCCurrent
(TEST, FS, nF[1:0], DS[1:0])
Input Pull-Up Current (PE)
InputPull-DownCurrent(sOE)
Output HIGH Voltage
VIN = VDD/2
µA
VIN = GND
IPU
IPD
VDD = Max., VIN = GND
VDD = Max., VIN = VDD
VDDQ = Min., IOH = −12mA
VDDQ = Min., IOL = 12mA
—
µA
µA
V
+100
—
VOH
VOL
2.4
OutputLOWVoltage
—
0.4
V
NOTE:
1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
4
IDT5V994
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKPLUS
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
TestConditions(1)
VDD = Max., TEST = MID, REF = LOW,
PE = LOW, sOE = LOW
Typ.
Max.
Unit
IDDQ
Quiescent Power Supply Current
8
25
mA
Alloutputsunloaded
∆IDD
Power Supply Current per Input HIGH
VDD = Max., VIN = 3V,
1
30
90
—
—
—
µA
IDDD
Dynamic Power Supply Current per Output
VDD/VDDQ = Max., CL = 0pF
55
31
34
39
µA/MHz
VDD/VDDQ = 3.3V , FREF = 83MHz, CL = 160pF(1)
VDD/VDDQ = 3.3V , FREF = 100MHz, CL = 160pF(1)
VDD/VDDQ = 3.3V , FREF = 133MHz, CL = 160pF(1)
ITOT
TotalPowerSupplyCurrent
mA
NOTE:
1. For eight outputs, each loaded with 20pF.
INPUTTIMINGREQUIREMENTS
Symbol
tR, tF
tPWC
Description(1)
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
Min.
—
Max.
Unit
ns/V
ns
10
—
2
DH
10
90
%
FREF
Referenceclockinputfrequency(2)
17.5
133
MHz
NOTES:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
2. The minimum reference clock input frequency is 70MHz if Q/2 or Q/4 are not used as feedback
5
IDT5V994
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKPLUS
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
Symbol
FNOM
tRPWH
tRPWL
tU
Parameter
Min.
Typ.
Max.
Unit
VCO Frequency Range
REF Pulse Width HIGH(1)
REF Pulse Width LOW(1)
SeeProgrammableSkewRangeandResolutionTable
2
2
—
—
—
ns
ns
—
ProgrammableSkewTimeUnit
SeeControlSummaryTable
tSKEWPR
tSKEW0
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tDEV
Zero Output Matched-Pair Skew (xQ0, xQ1)(2,3)
ZeroOutputSkew(AllOutputs)(4)
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)(5)
OutputSkew(Rise-Fall,Nominal-Inverted,Divided-Divided)(5)
OutputSkew(Rise-Rise,Fall-Fall,DifferentClassOutputs)(5)
OutputSkew(Rise-Fall,Nominal-Divided,Divided-Inverted)(2)
Device-to-Device Skew(2,6)
REF Input to FB Static Phase Offset)(7)
Output Duty Cycle Variation from 50%
Output HIGH Time Deviation from 50%(8)
OutputLOWTimeDeviationfrom50%(9)
OutputRiseTime
—
—
0.05
0.1
0.25
0.3
0.25
0.5
—
0.2
0.25
0.5
1.2
0.5
0.9
0.75
0.25
1.2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
—
—
—
—
—
t(φ)
−0.25
−1.2
—
0
tODCV
tPWH
0
—
tPWL
—
—
2.5
1.8
1.8
0.5
200
tORISE
tOFALL
tLOCK
tJR
0.15
0.15
—
1
OutputFallTime
PLLLockTime(10)
1
—
Cycle-to-CycleOutputJitter(peak-to-peak)
—
—
NOTES:
1. Refer to Input Timing Requirements table for more detail.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSK(0) is the skew between outputs when they are selected for 0tU.
5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-
by-4 mode).
6. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
7. tφ is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.
8. Measured at 2V.
9. Measured at 0.8V.
10. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tφ is within specified limits.
6
IDT5V994
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKPLUS
AC TEST LOADS AND WAVEFORMS
VDDQ
150Ω
Output
150Ω
20pF
tOFALL
tORISE
2.0V
0.8V
tPWH
tPWL
LVTTL Output Waveform
≤1ns
≤1ns
3.0V
2.0V
VTH = 1.5V
0.8V
0V
LVTTL Input Test Waveform
7
IDT5V994
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKPLUS
INDUSTRIALTEMPERATURERANGE
AC TIMING DIAGRAM
tRPWL
tREF
tRPWH
REF
FB
Q
t(φ)
tODCV
tODCV
tJR
tSKEWPR
tSKEW0, 1
tSKEWPR
tSKEW0, 1
OTHER Q
tSKEW2
tSKEW2
INVERTED Q
tSKEW3, 4
tSKEW3, 4
tSKEW3, 4
tSKEW2, 4
REF DIVIDED BY 2
tSKEW1, 3, 4
REF DIVIDED BY 4
NOTES:
PE:
The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge
of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated
with 75Ω to VDDQ/2.
tSKEWPR:
tSKEW0:
tDEV:
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
The skew between outputs when they are selected for 0tU
.
The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tODCV:
tPWH is measured at 2V.
tPWL is measured at 0.8V.
tORISE and tOFALL are measured between 0.8V and 2V.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
8
IDT5V994
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKPLUS
ORDERINGINFORMATION
X
XXXXX
XX
IDT
Package
Package
Device Type
I
-40°C to +85°C (Industrial)
32-pin PLCC
J
32-pin TQFP
32-pin TQFP - Green
PF
PFG
5V994
3.3V Programmable Skew PLL Clock
Driver TurboClock Plus
DATASHEETDOCUMENTHISTORY
1/21/02 pages 1, 2, 4
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975StenderWay
Santa Clara, CA 95054
800-345-7015 or 408-727-6116
fax: 408-492-8674
logichelp@idt.com
(408) 654-6459
www.idt.com
9
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