IDT5V9950PF [IDT]
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, TQFP-32;
| 型号： | IDT5V9950PF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, TQFP-32 驱动 逻辑集成电路 |
| 文件： | 总8页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION
NOTE
PROGRAMMING TURBOCLOCK II™
IDT5V995, IDT5V9950,
IDT5T995/A, AND IDT5T9950/A
AN-228
INTRODUCTION
PROGRAMMING THE OUTPUT SKEW
Asnewtechnologydemandshigh-performancedesign,thedistribution
The outputs ofTurboClockIIare organizedinfourbanks oftwooutputs
ofhigh-speedclockhas become a difficulttaskforthe systemdesigners. each(nQ1,nQ0).Eachoutputpairis programmedwiththe corresponding
TurboClock II™ provides the design engineers with the opportunities to Function/SkewSelect(nF1,nF0)inputs.Theinputs canbetiedHigh,Low,
overcome the manychallengingissues ofclockskew,andclockmultipli- or left unconnected to Mid level (an internal resistor network will bias the
cation and division. The family offers 3.3V and 2.5V products in 32-pin signallevelto0.5VCC).These 3-levelinputs allowa totalofnine different
TQFP and 44-pin TQFP packages:
outputselections.Inthedatasheet,theSkewSelectionTableforOutputPairs
(reproducedinthe ControlSummaryTable)shows the listofoutputs from
eachpairwhenanyzeroskewoutputisusedasfeedback.Notethatoutput
pair#1and#2share the same outputcharacteristics. Forthe IDT5V995
and IDT5T995/A, the FB input passes through a programmable divider
beforebeingfedtothePLLasthefeedbacksignal. Thedivisionratioofthis
FBdivideris controlledbyDS[1:0] inputs,whichcanbe tiedhigh,tiedlow,
orleftunconnectedfora midlevel.
– IDT5V995 (3.3V, LVTTL outputs in TQFP)
– IDT5V9950 (3.3V, LVTTL outputs in TQFP)
– IDT5T995 (2.5V, LVTTL outputs in TQFP)
– IDT5T9950 (2.5V, LVTTL outputs in TQFP)
– IDT5T995A (2.5V, LVTTL outputs in TQFP)
– IDT5T9950A (2.5V, LVTTL outputs in TQFP)
Figure 1shows the TurboClockIIblockdiagrams fordifferentproduct
variants.
FIGURE1:TURBOCLOCKBLOCKDIAGRAMS
sOE
sOE
IDT5V9950
IDT5T9950
IDT5V995/A
IDT5T995/A
1Q0
1Q0
1Q1
SKEW
SKEW
SELECT
SELECT
3
3
3
3
1Q1
1F0:1
1F0:1
2Q0
2Q1
2Q0
2Q1
SKEW
SELECT
SKEW
SELECT
3
3
3
3
REF
FB
REF
FB
PLL
3
PLL
3
/N
2F0:1
2F0:1
3
3
3Q0
3Q1
3Q0
3Q1
SKEW
SELECT
SKEW
SELECT
DS0:1
FS
FS
3
3
3
3
3F0:1
3F0:1
4Q0
4Q1
4Q0
4Q1
SKEW
SELECT
SKEW
SELECT
3
3
3
3
4F0:1
4F0:1
1
c /-
2001 Integrated Device Technology, Inc.
DSC-5950/4
APPLICATIONNOTEAN-228
PROGRAMMINGTURBOCLOCKIIIDT5V995,IDT5V9950,IDT5T995/A,ANDIDT5T9950/A
ThefirststepinprogrammingistodeterminetheVCOfrequency(FNOM)
The flexibility of TurboClock II is further enhanced by using a skewed
basedonthe REFinputfrequency,andthe designedoutputfrequencies. outputas feedback.Forinstance,iffeedbackis 3Qand3F1:0 =ML(–2tU),
ThePLLwillalways trytoadjusttheVCOtoalignthefrequencyandphase the 2Qoutputwillhave zeroskewwhen2F1:0=LH(–2tU)since the actual
ofREFwiththe outputofthe FBdivider. Forexample,whenanundivided outputskewat2Qiscalculatedfromtheprogrammed2Qoutputskew(–2tU)
outputis usedas feedback,andthe FBdivideris settounity,the VCOwill minus the feedbackskew(–2tU).If2F1:0 =LL,thenthe actualoutputskew
operate atthe same frequencyas REF. Ifa divide-by-fouroutputis used at2Qis –2tU[–4tU–(–2tU)].The OutputConfigurationtables showallthe
asfeedback,andtheFBdividerisalsosetto4,theVCOoperatesat16times possibleoutputconfigurations(skewadjustment,frequencymultiplication/
theREFfrequency. Notethatloopstabilityconsiderations imposerestric- division)withdifferentfeedbacks.Tables1through3holdtruefor1Qoutput
tions on the combinations of output and FB divider values which are configurations ifFBis 2Q.Thefirstcolumninthetables settheskewofthe
permitted (refer to the DIVIDE SELECTION table on page 3).
feedback.Eachoutputpairhasninepossibleoutputcombinationsforagiven
FB(listed immediately on the right-hand side of the FB skew) by setting
differentlevels toFunctionSelectpairs (nF1:0).
The secondstepis todecide the settingforFSandnF1:0 controlinputs
basedontheVCOfrequencyanddesiredoutputskew.Thedesiredoutput
skew will be a multiple of the Time Unit (tU) calculated from the PLL
Programmable SkewRange andResolutionTable.
CONTROLSUMMARYTABLEFORFEEDBACKSIGNALS
nF(1:0)
Skew (Pair #1, #2)
Skew (Pair #3)
Divide by 2
–6tU
Skew (Pair #4)
Divide by 2
–6tU
LL
–4tU
–3tU
LM
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
MM
MH
HL
ZeroSkew
1tU
ZeroSkew
2tU
ZeroSkew
2tU
2tU
4tU
4tU
HM
HH
3tU
6tU
6tU
4tU
Divide by 4
Inverted
DIVIDESELECTIONTABLE
DS(1:0)
FeedbackDivide-by-n
Permitted Divide-by-n Connected to FB
LL
2
3
1 or 2
1
LM
LH
4
1, 2, or 4
1 or 2
1, 2, or 4
1 or 2
1 or 2
1
ML
5
MM
MH
HL
1
6
8
HM
HH
10
12
1
PLLPROGRAMMABLESKEWRANGEANDRESOLUTIONTABLE
FS = LOW
1/(32 x FNOM)
24 to 50MHz
FS = MID
1/(16 x FNOM)
48 to 100MHz
FS = HIGH
1/(8 x FNOM)
96 to 200 MHz
TimeUnit(tU)
VCO Frequency (FNOM)
IDT5V995,IDT5V9950,
IDT5T995A,andIDT5T9950A
IDT5T995andIDT5T9950
24 to 40MHz
40 to 80MHz
80 to 160 MHz
2
PROGRAMMINGTURBOCLOCKIIIDT5V995,IDT5V9950,IDT5T995/A,ANDIDT5T9950/A
APPLICATIONNOTEAN-228
OBTAININGMAXIMUMVCOFREQUENCYOPERATION
FORIDT5T995ANDIDT5T9950
REF
REF
40 MHz
80 MHz
FB
FB
40 MHz
80 MHz
REF
REF
4Q0
4Q1
4Q0
4Q1
160 MHz
40 MHz
160 MHz
80 MHz
FS
FS
4F0
4F1
3F0
3F1
4F0
4F1
3F0
3F1
IDT5T995 3Q0
3Q0
3Q1
IDT5T995
IDT5T9950
3Q1
IDT5T9950
2Q0
2Q1
2Q0
2Q1
160 MHz
160 MHz
2F0
2F1
1F0
160 MHz
160 MHz
2F0
2F1
1F0
1Q0
1Q1
1Q0
1Q1
1F1
1F1
TEST
TEST
DS1
DS0
DS1
DS0
Figure 2. Wiring Diagram and Frequency Multiply by two with
3F[1:0] = LL.
Figure 3. Wiring Diagram and Frequency Multiply by four with
3F[1:0] = HH.
Figure2demonstratestheIDT5T995 andIDT5T9950configuredforgetting
Figure3shows theIDT5T995 andIDT5T9950configuredforgettingmax
maxoutputat160MHz. The3Q0outputisprogrammedtodividebytwoand outputat160MHz. The3Q0outputisprogrammedtodividebyfourandisfed
isfedbacktoFB. ThiscausesthePLLtoincreaseitsfrequencyuntil3Q0and backtoFB. ThiscausesthePLLtoincreaseitsfrequencyuntil3Q0and3Q1
3Q1 outputs are locked at 80MHz while 1Qx, 2Qx and 3Qx outputs run at outputsarelockedat40MHzwhile1Qx,2Qxand4Qxoutputsrunat160MHz.
160MHz. The 1Qx, 2Qxand4Qxoutputs are skewedbyprogrammingtheir The1Qx,2Qxand3Qxoutputsareskewedbyprogrammingtheirselectinputs
selectinputsaccordingly(RefertoTable4formoredetails.)NotethatFSpin accordingly(RefertoTable5formoredetails.)NotethatFSpinisconnected
isconnectedtoHighforfastestfrequencyoutputrange. AlsonotethattheDS[1:0] to High for fastest frequency output range. Also note that the DS[1:0] is not
isnotapplicablefortheIDT5T9950. DS[1:0]=MMisforadivide-by-1selection. applicable for the IDT5T9950. DS[1:0] = MM is for a divide-by-1 selection.
REF
13.33 MHz
REF
26.67 MHz
FB
13.33 MHz
FB
26.67 MHz
REF
FS
REF
FS
4Q0
4Q1
160 MHz
160 MHz
4Q0
4Q1
160 MHz
160 MHz
4F0
4F1
3F0
3F1
4F0
4F1
3F0
3F1
3Q0
3Q1
IDT5T995
3Q0
3Q1
IDT5T995
2Q0
2Q1
160 MHz
160 MHz
2F0
2F1
1F0
2Q0
2Q1
160 MHz
160 MHz
2F0
2F1
1F0
1Q0
1Q1
1Q0
1Q1
1F1
1F1
TEST
TEST
DS1
DS0
DS1
DS0
Figure 4. Wiring Diagram and Frequency Multiply by six with
4F[1:0] = MM and DS[1:0] = MH.
Figure 5. Wiring Diagram and Frequency Multiply by twelve with
1F[1:0] = MM and DS[1:0] = HH.
Figure 4 illustrates the IDT5T995 configured for getting max output at
Figure 5 illustrates the IDT5T995 configured for getting max output at
160MHz. TheFBinputisprogrammedtodividebysix. With26.67MHzinput 160MHz. The FB inputis programmedtodivide by twelve. With13.33MHz
toREF,thePLLwillincreasetheVCOfrequencyuntiltheoutputoftheFBdivider inputtoREF,thePLLwillincreasetheVCOfrequencyuntiltheoutputoftheFB
isalso26.67MHz. TheFBinputand4Q0outputwillthenbesixtimes26.67MHz divideris also13.33MHz. TheFBinputand4Q0outputwillthenbesixtimes
or160MHz. The1Qx,2Qxand3Qxoutputsareskewedbyprogrammingtheir 13.33MHz or 160MHz. The 2Qx, 3Qx and 4Qx outputs are skewed by
selectinputsaccordingly(RefertoTable8formoredetails.)NotethatFSpin programmingtheirselectinputsaccordingly(RefertoTable9formoredetails.)
isconnectedtoHighforfastestfrequencyoutputrange.
NotethatFSpinisconnectedtoHighforfastestfrequencyoutputrange.
3
APPLICATIONNOTEAN-228
PROGRAMMINGTURBOCLOCKIIIDT5V995,IDT5V9950,IDT5T995/A,ANDIDT5T9950/A
OBTAININGMAXIMUMVCOFREQUENCYOPERATION
FORIDT5V995,IDT5V9950,IDT5T995A,ANDIDT5T9950A
REF
REF
100 MHz
50 MHz
FB
FB
100 MHz
50 MHz
REF
REF
4Q0
4Q1
4Q0
4Q1
200 MHz
100 MHz
200 MHz
50 MHz
FS
FS
4F0
4F1
3F0
3F1
4F0
4F1
3F0
3F1
3Q0
IDT5V995 3Q1
IDT5V9950
3Q0
3Q1
IDT5V995
IDT5V9950
IDT5T995A
IDT5T9950A
IDT5T995A
IDT5T9950A
2Q0
2Q1
2Q0
200 MHz
200 MHz
200 MHz
200 MHz
2F0
2F1
1F0
1F1
2F0
2F1
1F0
1F1
2Q1
1Q0
1Q1
1Q0
1Q1
TEST
TEST
DS1
DS0
DS1
DS0
Figure 6. Wiring Diagram and Frequency Multiply by two with
3F[1:0] = LL.
Figure 7. Wiring Diagram and Frequency Multiply by four with
3F[1:0] = HH.
Figure7showstheIDT5V995,IDT5V9950,IDT5T995A,andIDT5T9950A
configuredforgettingmaxoutputat200MHz. The3Q0outputisprogrammed
to divide by four and is fed back to FB. This causes the PLL to increase its
frequencyuntil3Q0and3Q1outputsarelockedat50MHzwhile1Qx,2Qxand
4Qx outputs run at 200MHz. The 1Qx, 2Qx and 3Qx outputs are skewed by
programmingtheirselectinputsaccordingly(RefertoTable5formoredetails.)
NotethatFSpinisconnectedtoHighforfastestfrequencyoutputrange. Also
note that the DS[1:0] is not applicable for the IDT5V9950 and IDT5T9950A.
DS[1:0] = MM is for a divide-by-1 selection.
Figure 6 demonstrates the IDT5V995, IDT5V9950, IDT5T995A, and
IDT5T9950Aconfiguredforgettingmaxoutputat200MHz. The3Q0outputis
programmed to divide by two and is fed back to FB. This causes the PLL to
increaseitsfrequencyuntil3Q0and3Q1outputsarelockedat100MHzwhile
1Qx,2Qxand3Qxoutputsrunat200MHz.The1Qx,2Qxand4Qxoutputsare
skewedbyprogrammingtheirselectinputs accordingly(RefertoTable 4for
moredetails.)NotethatFSpinisconnectedtoHighforfastestfrequencyoutput
range. Also note that the DS[1:0] is not applicable for the IDT5V9950 and
IDT5T9950A. DS[1:0] = MM is for a divide-by-1 selection.
REF
16.67 MHz
REF
33.33 MHz
FB
FB
33.33 MHz
REF
16.67 MHz
REF
4Q0
4Q1
200 MHz
200 MHz
FS
4Q0
FS
200 MHz
200 MHz
4Q1
4F0
4F1
3F0
3F1
4F0
4F1
3F0
3F1
3Q0
3Q1
IDT5V995
3Q0
3Q1
IDT5V995
IDT5T995A
IDT5T995A
2Q0
2Q1
2Q0
2Q1
200 MHz
200 MHz
2F0
2F1
1F0
2F0
2F1
1F0
200 MHz
200 MHz
1Q0
1Q1
1Q0
1Q1
1F1
1F1
TEST
TEST
DS1
DS0
DS1
DS0
Figure 8. Wiring Diagram and Frequency Multiply by six with
4F[1:0] = MM and DS[1:0] = MH.
Figure 9. Wiring Diagram and Frequency Multiply by twelve with
1F[1:0] = MM and DS[1:0] = MH.
Figure8illustratestheIDT5V995andIDT5T995configuredforgettingmax
Figure9illustratestheIDT5V995andIDT5T995configuredforgettingmax
outputat200MHz. TheFBinputisprogrammedtodividebysix. With33.33MHz output at 200MHz. The FB input is programmed to divide by twelve. With
inputtoREF,thePLLwillincreasetheVCOfrequencyuntiltheoutputoftheFB 16.67MHzinputtoREF,thePLLwillincreasetheVCOfrequencyuntiltheoutput
divideris also33.33MHz. TheFBinputand4Q0outputwillthenbesixtimes oftheFBdividerisalso16.67MHz. TheFBinputand4Q0outputwillthenbe
33.33MHz or 200MHz. The 1Qx, 2Qx and 3Qx outputs are skewed by sixtimes 16.67MHzor200MHz.The2Qx,3Qxand4Qxoutputs areskewed
programmingtheirselectinputsaccordingly(RefertoTable8formoredetails.) by programming their select inputs accordingly (Refer to Table 9 for more
NotethatFSpinisconnectedtoHighforfastestfrequencyoutputrange.
details.)NotethatFSpinisconnectedtoHighforfastestfrequencyoutputrange.
4
PROGRAMMINGTURBOCLOCKIIIDT5V995,IDT5V9950,IDT5T995/A,ANDIDT5T9950/A
APPLICATIONNOTEAN-228
OBTAININGMINIMUMVCOFREQUENCYOPERATIONFORIDT5V995,
IDT5V9950,IDT5T995/A,ANDIDT5T9950/A
Theminimumoutputfrequencyof6MHzisachievedat3Qx,withminimum
VCO frequency (24MHz with FS = low) and the 3Qx output divider set to
4 (3F[1:0] = HH).
The VCO minimum frequency is 24MHz with FS = low for all product
variants. The corresponding input frequency will depend on the division
ratiosusedintheoutputandFBdividers. NotethatforFS=low,theminimum
inputfrequencyis2MHz,whichlimitsthemaximumvalueofcombinedoutput
and FB dividers to 12 for a VCO frequency of 24MHz.
OUTPUTCONFIGURATIONTABLES
TABLE 1. FB = 1Q. 2Q OUTPUT CONFIGURATIONS WITH DIFFERENT 2F(1:0)(1)
FB
1F(1:0)
LL
Outputat2F(1:0)
LL
LM
1tU
LH
2tU
ML
3tU
MM
4tU
MH
5tU
HL
6tU
HM
7tU
6tU
5tU
4tU
3tU
2tU
1tU
0tU
–1tU
HH
8tU
7tU
6tU
5tU
4tU
3tU
2tU
1tU
0tU
0tU
LM
LH
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
–7tU
–8tU
0tU
1tU
2tU
3tU
4tU
5tU
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
–7tU
0tU
1tU
2tU
3tU
4tU
ML
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
0tU
1tU
2tU
3tU
M M
M H
HL
–1tU
–2tU
–3tU
–4tU
–5tU
0tU
1tU
2tU
–1tU
–2tU
–3tU
–4tU
0tU
1tU
–1tU
–2tU
–3tU
0tU
H M
H H
–1tU
–2tU
NOTE:
1. DS[1:0] = MM for IDT5V995 and IDT5T995/A.
TABLE 2. FB = 1Q. 3Q OUTPUT CONFIGURATIONS WITH DIFFERENT 3F(1:0)(1)
FB
1F(1:0)
LL
Outputat3F(1:0)
LL
LM
–2tU
–3tU
–4tU
–5tU
–6tU
–7tU
–8tU
–9tU
–10tU
LH
0tU
ML
2tU
MM
4tU
MH
6tU
HL
8tU
7tU
6tU
5tU
4tU
3tU
2tU
1tU
0tU
HM
HH
f/2+4tU
f/2+3tU
f/2+2tU
f/2+1tU
f/2+0tU
f/2–1tU
f/2–2tU
f/2–3tU
f/2–4tU
10tU
9tU
8tU
7tU
6tU
5tU
4tU
3tU
2tU
f/4+4tU
f/4+3tU
f/4+2tU
f/4+1tU
f/4+0tU
f/4–1tU
f/4–2tU
f/4–3tU
f/4–4tU
LM
LH
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
–7tU
–8tU
1tU
3tU
5tU
0tU
2tU
4tU
ML
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
1tU
3tU
M M
M H
HL
0tU
2tU
–1tU
–2tU
–3tU
–4tU
1tU
0tU
H M
H H
–1tU
–2tU
NOTE:
1. DS[1:0] = MM for IDT5V995 and IDT5T995/A.
5
APPLICATIONNOTEAN-228
PROGRAMMINGTURBOCLOCKIIIDT5V995,IDT5V9950,IDT5T995/A,ANDIDT5T9950/A
TABLE 3. FB = 1Q. 4Q OUTPUT CONFIGURATIONS WITH DIFFERENT 4F(1:0)(1)
FB
1F(1:0)
LL
Outputat4F(1:0)
LL
LM
–2tU
–3tU
–4tU
–5tU
–6tU
–7tU
–8tU
–9tU
–10tU
LH
0tU
ML
2tU
MM
4tU
MH
6tU
HL
8tU
7tU
6tU
5tU
4tU
3tU
2tU
1tU
0tU
HM
10tU
9tU
8tU
7tU
6tU
5tU
4tU
3tU
2tU
HH
f/2+4tU
f/2+3tU
f/2+2tU
f/2+1tU
f/2+0tU
f/2–1tU
f/2–2tU
f/2–3tU
f/2–4tU
–f+4tU
–f+3tU
–f+2tU
–f+1tU
–f+0tU
–f–1tU
–f–2tU
–f–3tU
–f–4tU
LM
LH
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
–7tU
–8tU
1tU
3tU
5tU
0tU
2tU
4tU
ML
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
1tU
3tU
M M
M H
HL
0tU
2tU
–1tU
–2tU
–3tU
–4tU
1tU
0tU
H M
H H
–1tU
–2tU
NOTE:
1.DS[1:0] = MM for IDT5V995 and IDT5T995/A.
TABLE 4. FB = 3Q. 1Q/2Q OUTPUT CONFIGURATIONS WITH DIFFERENT 1F(1:0)/2F(1:0)(1)
FB
3F(1:0)
LL
Outputat1F(1:0)/2F(1:0)
LL
2*f–4tU
2tU
LM
2*f–3tU
3tU
LH
2*f–2tU
4tU
ML
2*f–1tU
5tU
MM
2*f+0tU
6tU
MH
2*f+1tU
7tU
HL
2*f+2tU
8tU
HM
2*f+3tU
9tU
HH
2*f+4tU
10tU
8tU
LM
LH
0tU
1tU
2tU
3tU
4tU
5tU
6tU
7tU
ML
–2tU
–1tU
–3tU
–5tU
–7tU
–9tU
4*f–3tU
0tU
1tU
2tU
3tU
4tU
5tU
6tU
M M
M H
HL
–4tU
–2tU
–4tU
–6tU
–8tU
4*f–2tU
–1tU
–3tU
–5tU
–7tU
4*f–1tU
0tU
1tU
2tU
3tU
4tU
–6tU
–2tU
–4tU
–6tU
4*f+0tU
–1tU
–3tU
–5tU
4*f+1tU
0tU
1tU
2tU
–8tU
–2tU
–4tU
4*f+2tU
–1tU
–3tU
4*f+3tU
0tU
H M
H H
–10tU
4*f–4tU
–2tU
4*f+4tU
NOTE:
1.DS[1:0] = MM for IDT5V995 and IDT5T995/A.
TABLE 5. FB = 3Q. 4Q OUTPUT CONFIGURATIONS WITH DIFFERENT 4F(1:0)(1)
FB
3F(1:0)
LL
Outputat4F(1:0)
LL
LM
2*f–6tU
0tU
LH
2*f–4tU
2tU
ML
2*f–2tU
4tU
MM
2*f+0tU
6tU
MH
2*f+2tU
8tU
HL
2*f+4tU
10tU
8tU
HM
2*f+6tU
12tU
10tU
8tU
HH
0tU
–2*f
LM
LH
f/2+6tU
f/2+4tU
f/2+2tU
f/2+0tU
f/2–2tU
f/2–4tU
f/2–6tU
2*f
–f+6tU
–f+4tU
–f+2tU
–f+0tU
–f–2tU
–f–4tU
–f–6tU
–4*f
–2tU
0tU
2tU
4tU
6tU
ML
–4tU
–2tU
0tU
2tU
4tU
6tU
M M
M H
HL
–6tU
–4tU
–2tU
–4tU
–6tU
–8tU
4*f–2tU
0tU
2tU
4tU
6tU
–8tU
–6tU
–2tU
–4tU
–6tU
4*f+0tU
0tU
2tU
4tU
–10tU
–12tU
4*f–6tU
–8tU
–2tU
–4tU
4*f+2tU
0tU
2tU
H M
H H
–10tU
4*f–4tU
–2tU
4*f+4tU
0tU
4*f+6tU
NOTE:
1.DS[1:0] = MM for IDT5V995 and IDT5T995/A.
6
PROGRAMMINGTURBOCLOCKIIIDT5V995,IDT5V9950,IDT5T995/A,ANDIDT5T9950/A
APPLICATIONNOTEAN-228
TABLE 6. FB = 4Q. 1Q/2Q OUTPUT CONFIGURATIONS WITH DIFFERENT 1F(1:0)/2F(1:0)(1)
FB
4F(1:0)
LL
Outputat1F(1:0)/2F(1:0)
LL
–2*f–4tU
2tU
LM
2*f–3tU
3tU
LH
2*f–2tU
4tU
ML
MM
2*f+0tU
6tU
MH
2*f+1tU
7tU
HL
2*f+2tU
8tU
HM
2*f+3tU
9tU
HH
2*f+4tU
10tU
8tU
2*f–1tU
5tU
LM
LH
0tU
1tU
2tU
3tU
4tU
5tU
6tU
7tU
ML
–2tU
–1tU
–3tU
–5tU
–7tU
–9tU
–f–3tU
0tU
1tU
2tU
3tU
4tU
5tU
6tU
M M
M H
HL
–4tU
–2tU
–4tU
–6tU
–8tU
–f–2tU
–1tU
–3tU
–5tU
–7tU
–f–1tU
0tU
1tU
2tU
3tU
4tU
–6tU
–2tU
–4tU
–6tU
–f+0tU
–1tU
–3tU
–5tU
–f+1tU
0tU
1tU
2tU
–8tU
–2tU
–4tU
–f+2tU
–1tU
–3tU
–f+3tU
0tU
H M
H H
–10tU
–f–4tU
–2tU
–f+4tU
NOTE:
1.DS[1:0] = MM for IDT5V995 and IDT5T995/A.
TABLE 7. FB = 4Q. 3Q OUTPUT CONFIGURATIONS WITH DIFFERENT 3F(1:0)(1)
FB
4F(1:0)
LL
Outputat3F(1:0)
LL
LM
2*f–6tU
0tU
LH
2*f–4tU
2tU
ML
2*f–2tU
4tU
MM
2*f+0tU
6tU
MH
2*f+2tU
8tU
HL
2*f+4tU
10tU
8tU
HM
2*f+6tU
12tU
10tU
8tU
HH
0tU
f/2+0tU
f/4+6tU
f/4+4tU
f/4+2tU
f/4+0tU
f/4–2tU
f/4–4tU
f/4–6tU
–f/4
LM
f/2+6tU
f/2+4tU
f/2+2tU
f/2+0tU
f/2–2tU
f/2–4tU
f/2–6tU
–f/2
LH
–2tU
0tU
2tU
4tU
6tU
ML
–4tU
–2tU
–4tU
–6tU
–8tU
–10tU
–f–4tU
0tU
2tU
4tU
6tU
M M
M H
HL
–6tU
–2tU
–4tU
–6tU
–8tU
–f–2tU
0tU
2tU
4tU
6tU
–8tU
–2tU
–4tU
–6tU
–f+0tU
0tU
2tU
4tU
–10tU
–12tU
–f–6tU
–2tU
–4tU
–f+2tU
0tU
2tU
H M
H H
–2tU
–f+4tU
0tU
–f+6tU
NOTE:
1.DS[1:0] = MM for IDT5V995 and IDT5T995/A.
TABLE 8. FB = 4Q; DS(1:0) = MH. 3Q OUTPUT CONFIGURATIONS WITH DIFFERENT 3F(1:0) AND DIVIDE-BY-6 ON FB (1)
FB
4F(1:0)
LL
Outputat3F(1:0)
MM
LL
LM
LH
ML
MH
HL
HM
HH
6*f+0tU
3*f+6tU
3*f+4tU
3*f+2tU
3*f+0tU
3*f–2tU
3*f–4tU
3*f–6tU
–3*f
12*f–6tU
–6*f+0tU
–6*f–2tU
–6*f–4tU
–6*f–6tU
–6*f–8tU
–6*f–10tU
–6*f–12tU
–6*f–6tU
12*f–4tU
–6*f+2tU
–6*f+0tU
–6*f–2tU
–6*f–4tU
–6*f–6tU
–6*f–8tU
–6*f–10tU
–6*f–4tU
12*f–2tU
–6*f+4tU
–6*f+2tU
–6*f+0tU
–6*f–2tU
–6*f–4tU
–6*f–6tU
–6*f–8tU
–6*f–2tU
12*f+0tU
–6*f+6tU
–6*f+4tU
–6*f+2tU
–6*f+0tU
–6*f–2tU
–6*f–4tU
–6*f–6tU
–6*f+0tU
12*f+2tU
–6*f+8tU
–6*f+6tU
–6*f+4tU
–6*f+2tU
–6*f+0tU
–6*f–2tU
–6*f–4tU
–6*f+2tU
12*f+4tU
–6*f+10tU
–6*f+8tU
–6*f+6tU
–6*f+4tU
–6*f+2tU
–6*f+0tU
–6*f–2tU
–6*f+4tU
12*f+6tU
–6*f+12tU
–6*f+10tU
–6*f+8tU
–6*f+6tU
–6*f+4tU
–6*f+2tU
–6*f+0tU
–6*f+6tU
3*f
LM
LH
3*f/2+6tU
3*f/2+4tU
3*f/2+2tU
3*f/2+0tU
3*f/2–2tU
3*f/2–4tU
3*f/2–6tU
–3*f/2
ML
M M
M H
HL
H M
H H
NOTE:
1.Not applicable to IDT5V9950 and IDT5T9950/A.
7
APPLICATIONNOTEAN-228
TABLE 9. FB = 1Q/2Q; DS(1:0) = HH. 3Q OUTPUT CONFIGURATIONS WITH DIFFERENT 3F(1:0) AND DIVIDE-BY-12 ON FB (1)
PROGRAMMINGTURBOCLOCKIIIDT5V995,IDT5V9950,IDT5T995/A,ANDIDT5T9950/A
FB
1F(1:0)/2F(1:0)
LL
Outputat3F(1:0)
MM
LL
LM
LH
ML
MH
HL
HM
HH
6*f+4tU
6*f+3tU
6*f+2tU
6*f+1tU
6*f+0tU
6*f–1tU
6*f–2tU
6*f–3tU
6*f–4tU
12*f–2tU
12*f–3tU
12*f–4tU
12*f–5tU
12*f–6tU
12*f–7tU
12*f–8tU
12*f–9tU
12*f–10tU
12*f+0tU
12*f–1tU
12*f–2tU
12*f–3tU
12*f–4tU
12*f–5tU
12*f–6tU
12*f–7tU
12*f–8tU
12*f+2tU
12*f+1tU
12*f+0tU
12*f–1tU
12*f–2tU
12*f–3tU
12*f–4tU
12*f–5tU
12*f–6tU
12*f+4tU
12*f+3tU
12*f+2tU
12*f+1tU
12*f+0tU
12*f–1tU
12*f–2tU
12*f–3tU
12*f–4tU
12*f+6tU
12*f+5tU
12*f+4tU
12*f+3tU
12*f+2tU
12*f+1tU
12*f+0tU
12*f–1tU
12*f–2tU
12*f+8tU
12*f+7tU
12*f+6tU
12*f+5tU
12*f+4tU
12*f+3tU
12*f+2tU
12*f+1tU
12*f+0tU
12*f+10tU
12*f+9tU
12*f+8tU
12*f+7tU
12*f+6tU
12*f+5tU
12*f+4tU
12*f+3tU
12*f+2tU
3*f+4tu
3*f+3tu
3*f+2tu
3*f+1tu
3*f+0tu
3*f-1tu
3*f-2tu
3*f-3tu
3*f-4tu
LM
LH
ML
M M
M H
HL
H M
H H
NOTE:
1.Not applicable to IDT5V9950 and IDT5T9950/A.
TABLE 10. FB = 4Q; DS(1:0) = LH. 1Q/2Q OUTPUT CONFIGURATIONS WITH DIFFERENT 1F(1:0)/2F(1:0) AND DIVIDE-BY-4 ON FB (1)
FB
4F(1:0)
LL
Outputat3F(1:0)
MM
LL
LM
LH
ML
MH
HL
HM
HH
8*f-4tU
4*f+2tU
4*f+0tU
4*f-2tU
4*f-4tU
4*f-6tU
4*f-8tU
4*f-10tU
4*f-4tU
8*f-3tU
4*f+3tU
4*f+1tU
4*f-1tU
4*f-3tU
4*f-5tU
4*f-7tU
4*f-9tU
4*f-3tU
8*f-2tU
4*f+4tU
4*f+2tU
4*f+0tU
4*f-2tU
4*f-4tU
4*f-6tU
4*f-8tU
4*f-2tU
8*f-1tU
4*f+5tU
4*f+3tU
4*f+1tU
4*f-1tU
4*f-3tU
4*f-5tU
4*f-7tU
4*f-1tU
8*f+0tU
4*f+6tU
4*f+4tU
4*f+2tU
4*f+0tU
4*f-2tU
8*f+1tU
4*f+7tU
4*f+5tU
4*f+3tU
4*f+1tU
4*f-1tU
4*f-3tU
4*f-5tU
4*f+1tU
8*f+2tU
4*f+8tU
4*f+6tU
4*f+4tU
4*f+2tU
4*f+0tU
4*f-2tU
4*f-4tU
4*f+2tU
8*f+3tU
4*f+9tU
4*f+7tU
4*f+5tU
4*f+3tU
4*f+1tU
4*f-1tU
4*f-3tU
4*f+3tU
8*f+4tU
4*f+10tU
4*f+8tU
4*f+6tU
4*f+4tU
4*f+2tU
4*f+0tU
4*f-2tU
LM
LH
ML
M M
M H
HL
4*f-4tU
H M
H H
4*f-6tU
4*f+0tU
4*f+4tU
NOTE:
1.Not applicable to IDT5V9950 and IDT5T9950/A.
CONCLUSION
Withits flexible,programmableskewcapability,TurboClockIIis ideally solutionsthaneverbefore. Thedesignerscanthenselectthesolutionthat
suitedforavarietyofapplications.WiththeaddedfeatureofanFBdivider best meets their requirements. In addition, IBIS and Hspice models are
forthe IDT5V995andIDT5T995/A,designers have manymore possible available atnocostforsystemsimulationpurposes.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
8
相关型号：
IDT5V9950PFI8
PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PQFP32, TQFP-32
IDT
IDT5V9955BFGI
PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PBGA96, GREEN, FBGA-52
IDT
IDT5V9955BFGI8
PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PBGA96, GREEN, FBGA-52
IDT
IDT5V9955BFI
PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PBGA96, FBGA-52
IDT
IDT5V9955BFI8
PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PBGA96, FBGA-52
IDT
©2020 ICPDF网 联系我们和版权申明