IDT5V9950PFG [IDT]
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, TQFP-32;
| 型号： | IDT5V9950PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, TQFP-32 驱动 逻辑集成电路 |
| 文件： | 总9页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK™ II JR.
IDT5V9950
ADVANCED
INFORMATION
DESCRIPTION:
FEATURES:
The IDT5V9950is a highfanout3.3VPLLbasedclockdriverintended
forhighperformancecomputinganddata-communicationsapplications.A
keyfeatureoftheprogrammableskewis theabilityofoutputs toleadorlag
the REF input signal. The IDT5V9950 has eight programmable skew
outputs infourbanks of2. Skewis controlledby3-levelinputsignals that
may be hard-wired to appropriate HIGH-MID-LOW levels.
•
•
•
•
REF is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 185ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
•
•
•
•
•
•
•
•
•
•
Synchronous output enable
Input frequency: 6MHz to 200MHz
Output frequency: 6MHz to 200MHz
2x, 4x, 1/2, and 1/4 outputs
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Available in 32-pin TQFP Package
WhenthesOEpinisheldlow,alltheoutputsaresynchronouslyenabled.
However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are
synchronouslydisabled.
Furthermore,whenPEisheldhigh,alltheoutputsaresynchronizedwith
thepositiveedgeoftheREFclockinput.WhenPEisheldlow,alltheoutputs
are synchronized with the negative edge of REF. The IDT5V9950 has
LVTTLoutputs with12mAbalanceddrive outputs.
sOE
FUNCTIONALBLOCKDIAGRAM
1Q0
Skew
Select
1Q1
3
3
1F1:0
PE TEST
3
2Q0
2Q1
Skew
Select
3
3
3
3
REF
PLL
2F1:0
FB
3Q0
3Q1
Skew
Select
3
3
FS
3F1:0
4Q0
4Q1
Skew
Select
3
4F1:0
INDUSTRIAL TEMPERATURE RANGE
MARCH 2001
1
c
2001 Integrated Device Technology, Inc.
DSC-5870/-
IDT5V9950
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.
ABSOLUTE MAXIMUM RATINGS (1)
PINCONFIGURATION
Symbol
Rating
Max.
Unit
VDDQ,VDD Supply Voltage to Ground
–0.5 to +4.6
V
VI
DC Input Voltage
REF Input Voltage
Maximum Power
Dissipation
–0.5 to VDD+0.5
–0.5 to +5.5
0.7
V
V
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
3F1
4F0
1
2
3
4
5
6
7
8
1F1
1F0
TA = 85°C
TA = 55°C
W
W
°C
1.1
TSTG
Storage Temperature Range
–65 to +150
4F1
PE
sOE
NOTE:
VDDQ
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
PR32
VDDQ
4Q1
1Q
0
1Q1
4Q0
GND
GND
GND
9
10 11 12 13 14 15 16
CAPACITANCE (T = 25 C, f = 1MHz, V = 0V)
°
A
IN
Parameter
Description
Typ.
Max.
Unit
CIN
Input Capacitance
5
7
pF
NOTE:
1. Capacitance applies to all inputs except TEST, FS, and nF[1:0].
TQFP
TOP VIEW
PIN DESCRIPTION
Pin Name
Type
Description
REF
IN
Reference Clock Input
Feedback Input
FB
IN
TEST (1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control
Summary Table) remain in effect. Set LOW for normal operation.
sOE (1)
IN
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and 2Q1
may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act
as output disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down).
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock (has internal pull-up).
PE
nF[1:0]
FS
IN
3-level inputs for selecting 1 of 9 skew taps or frequency functions
IN
Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)
nQ[1:0]
VDDQ
VDD
OUT
PWR
PWR
PWR
Four banks of two outputs with programmable skew
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
GND
NOTE:
1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew
selections remain in effect unless nF[1:0] = LL.
2
IDT5V9950
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.
PROGRAMMABLESKEW
Output skew with respect to the REF input is adjustable to compensate to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
for PCB trace delays, backplane propagation delays or to accommodate are used, they are intended for but not restricted to hard-wiring. Undriven
requirements for special timing relationships between clocked compo- 3-level inputs default to the MID level. Where programmable skew is
nents. Skew is selectable as a multiple of a time unit (tU) which ranges not a requirement, the control pins can be left open for the zero skew
from 625ps to 1.3ns (see Programmable Skew Range and Resolution default setting. The Control Summary Table shows how to select specific
Table). There are nine skew configurations available for each output skew taps by using the nF1:0 control pins.
pair. These configurations are chosen by the nF1:0 control pins. In order
EXTERNALFEEDBACK
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
By providing external feedback, the IDT5V9950 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FS = LOW
1/(32 x FNOM)
24 to 50MHz
FS = MID
1/(16 x FNOM)
48 to 100MHz
FS = HIGH
1/(8 xFNOM)
96 to 200 MHz
Comments
Timing Unit Calculation (tU)
VCO Frequency Range (FNOM) (1,2)
Skew Adjustment Range (3)
Max Adjustment:
±7.8125ns
±67.5º
±7.8125ns
±135º
±7.8125ns
±270º
ns
Phase Degrees
% of Cycle Time
±18.75%
tu = 1.25ns
tu = 0.833ns
tu = 0.625ns
—
±37.5%
—
±75%
Example 1, FNOM = 25MHz
Example 2, FNOM = 37.5MHz
Example 3, FNOM = 50MHz
Example 4, FNOM = 75MHz
Example 5, FNOM = 100MHz
Example 6, FNOM = 150MHz
Example 7, FNOM = 200MHz
NOTES:
—
—
—
tu = 1.25ns
tu = 0.833ns
tu = 0.625ns
—
—
—
—
tu = 1.25ns
tu = 0.833ns
tu = 0.625ns
—
—
—
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always
appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs
will be the same as VCO when the output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO
frequency when the part is configured for frequency multiplication by using a divided output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will
be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is
programmed for those outputs. ‘Max adjustment’ range applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest
FNOM value.
3
IDT5V9950
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
LL (1)
LM
Skew (Pair #1, #2)
Skew (Pair #3)
Divide by 2
–6tU
Skew (Pair #4)
Divide by 2
–6tU
–4tU
–3tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
MM
MH
HL
Zero Skew
1tU
Zero Skew
2tU
Zero Skew
2tU
2tU
4tU
4tU
HM
HH
3tU
6tU
6tU
Inverted (2)
4tU
Divide by 4
NOTES:
1. LL disables outputs if TEST = MID and sOE = HIGH.
2. When pair #4 is set to HH (inverted), sOE disables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW.
RECOMMENDED OPERATING RANGE
Symbol
Description
Power Supply Voltage
Ambient Operating Temperature
Min.
Typ.
Max.
Unit
VDD/VDDQ
3
3.3
3.6
V
TA
-40
—
+85
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Input HIGH Voltage
Conditions
Min.
Max.
Unit
VIH
Guaranteed Logic HIGH (REF, FB Inputs Only)
2
—
V
V
VIL
Input LOW Voltage
Input HIGH Voltage (1)
Input MID Voltage (1)
Input LOW Voltage (1)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
—
VDD−0.6
VDD/2−0.3
—
0.8
—
VIHH
VIMM
VILL
IIN
V
3-Level Inputs Only
VDD/2+0.3
0.6
V
3-Level Inputs Only
V
Input Leakage Current
(REF, FB Inputs Only)
VIN = VDD or GND
VDD = Max.
−5
+5
µA
VIN = VDD
HIGH Level
MID Level
LOW Level
—
−50
−200
−100
—
+200
+50
—
I3
3-Level Input DC Current
(TEST, FS, nF[1:0])
VIN = VDD/2
µA
VIN = GND
IPU
Input Pull-Up Current (PE)
Input Pull-Down Current (sOE)
Output HIGH Voltage
VDD = Max., VIN = GND
VDD = Max., VIN = VDD
VDDQ = Min., IOH = −12mA
VDDQ = Min., IOL = 12mA
—
µA
µA
V
IPD
+100
—
VOH
VOL
2.4
Output LOW Voltage
—
0.4
V
NOTE:
1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are
switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are
achieved.
4
IDT5V9950
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
VDD = Max., TEST = MID, REF = LOW,
PE = LOW, sOE = LOW
Typ. (2)
Max.
Unit
IDDQ
Quiescent Power Supply Current
20
30
mA
All outputs unloaded
∆IDD
Power Supply Current per Input HIGH
VDD = Max., VIN = 3V
1
30
290
230
200
—
µA
FS = L
190
150
130
56
IDDD
Dynamic Power Supply Current per Output
FS = M
µA/MHz
FS = H
FS = L , FVCO = 50MHz, CL = 0pF
FS = M , FVCO = 100MHz, CL = 0pF
FS = H, FVCO = 200MHz, CL = 0pF
ITOT
Total Power Supply Current
80
—
mA
125
—
NOTES:
1. Measurements are for divide-by-1 outputs and DS[1:0] = MM.
2. For nominal voltage and temperature.
INPUT TIMING REQUIREMENTS
Symbol
Description (1)
Min.
Max.
Unit
tR, tF
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
—
2
10
—
ns/V
tPWC
DH
ns
%
10
6
90
FS = LOW
FS = MID
FS = HIGH
50
FREF
Reference clock input frequency
12
24
100
200
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
5
IDT5V9950
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Min.
Typ.
Max.
Unit
FNOM
VCO Frequency Range
See Programmable Skew Range and Resolution Table
tRPWH
tRPWL
tU
REF Pulse Width HIGH (10)
REF Pulse Width LOW (10)
Programmable Skew Time Unit
2
2
—
—
—
—
ns
ns
See Control Summary Table
tSKEWPR
tSKEW0
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tDEV
Zero Output Matched-Pair Skew (xQ0, xQ1) (1,2)
Zero Output Skew (All Outputs) (3)
—
—
50
0.1
0.1
0.2
0.15
0.3
—
0
185
0.25
0.25
0.5
0.5
0.9
0.75
0.25
1
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs) (4)
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided) (4)
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs) (4)
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted) (1)
Device-to-Device Skew (1,5)
—
—
—
—
—
t(φ)
REF Input to FB Static Phase Offset (7)
Output Duty Cycle Variation from 50%
Output HIGH Time Deviation from 50% (8)
Output LOW Time Deviation from 50% (9)
Output Rise Time
−0.25
−1
tODCV
tPWH
0
—
—
—
0.7
0.7
—
—
1.5
2
tPWL
—
tORISE
tOFALL
tLOCK
tCCJH
0.15
0.15
—
1.5
1.5
0.5
100
Output Fall Time
PLL Lock Time (6)
Cycle-to-Cycle Output Jitter (peak-to-peak)
(divide by 1 output frequency, FS = H)
Cycle-to-Cycle Output Jitter (peak-to-peak)
(divide by 1 output frequency, FS = M)
Cycle-to-Cycle Output Jitter (peak-to-peak)
(divide by 1 output frequency, FS = L)
—
tCCJM
tCCJL
—
—
—
—
150
200
ps
NOTES:
1. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are
loaded with the specified load.
2. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
3. tSK(0) is the skew between outputs when they are selected for 0tU.
4. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only
in Divide-by-2 or Divide-by-4 mode). Test condition: nF0:1 = MM is set on unused outputs.
5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal
operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
7. tφ is measured with REF input rise and fall times (from 0.8V to 2V) of 0.5ns. Measured from 1.5V on REF to 1.5V on FB.
8. Measured at 2V.
9. Measured at 0.8V.
10. Refer to Input Timing Requirements table for more detail.
6
IDT5V9950
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.
AC TEST LOADS AND WAVEFORMS
VDDQ
150Ω
Output
150Ω
20pF
tOFALL
tORISE
2.0V
= 1.5V
0.8V
tPWH
VTH
tPWL
LVTTLOUTPUTWAVEFORM
≤1ns
≤1ns
3.0V
2.0V
VTH = 1.5V
0.8V
0V
LVTTL INPUT TEST WAVEFORM
7
IDT5V9950
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.
AC TIMING DIAGRAM
tRPWL
tREF
tRPWH
REF
FB
Q
t(φ)
tODCV
tODCV
tCCJH,M,L
tSKEWPR
tSKEW0, 1
tSKEWPR
tSKEW0, 1
OTHER Q
tSKEW2
tSKEW2
INVERTED Q
tSKEW3, 4
tSKEW3, 4
tSKEW3, 4
REF DIVIDED BY 2
tSKEW1, 3, 4
tSKEW2, 4
REF DIVIDED BY 4
NOTES:
PE:
The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs
change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are
loaded with 20pF and terminated with 75Ω to VDDQ/2.
tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSKEW0: The skew between outputs when they are selected for 0tU
.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tODCV:
tPWH is measured at 2V.
tPWL is measured at 0.8V.
tORISE and tOFALL are measured between 0.8V and 2V.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal
operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
8
IDT5V9950
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.
ORDERINGINFORMATION
IDT
XXXXX
XX
Package
Device Type
Thin Quad Flat Pack (PR32)
PF
5V9950
3.3V Programmable Skew PLL Clock
Driver TurboClock II Jr.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Turboclock is a registered trademark of Integrated Device Technology, Inc.
9
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