IDT49FCT805CTPYG8 [IDT]
Low Skew Clock Driver, FCT Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, GREEN, SSOP-20;
| 型号： | IDT49FCT805CTPYG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, FCT Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, GREEN, SSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS
BUFFER/CLOCK DRIVER
IDT49FCT805BT/CT
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew < 500ps (max.)
• Very low duty cycle distortion < 600ps (max.)
• Low CMOS power levels
This buffer/clock driver is built using advanced dual metal CMOS
technology. TheFCT805Tisanon-invertingclockdriverconsistingoftwo
banksofdrivers. EachbankdrivesfiveoutputbuffersfromastandardTTL
compatibleinput. Thisparthasextremelylowoutputskew,pulseskew,and
packageskew. Thedevicehasa “heart-beat”monitorfordiagnosticsand
PLLdriving. Themonitoroutputisidenticaltoallotheroutputsandcomplies
withtheoutputspecificationsinthisdocument.
• TTL compatible inputs and outputs
• TTL level output voltage swings
• High drive: -32mA IOH, +48mA IOL
• Two independent output banks with 3-state control
• 1:5 fanout per bank
The FCT805T is designed for fast, clean edge rates to provide accurate
clock distribution in high speed systems.
• "Heartbeat" monitor output
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• Available in the following packages:
– Commercial: QSOP, SOIC, SSOP
– Military: CERDIP, LCC
NOTE: EOL for non-green parts to occur on 5/13/10 per
PDNU-09-01
FUNCTIONALBLOCKDIAGRAM
OEA
INA
5
OA1-OA5
5
INB
OB1-OB5
OEB
MON
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEPT. 2009
1
c
2000 Integrated Device Technology, Inc.
DSC-4771/3
IDT49FCT805BT/CT
FAST CMOSBUFFER/CLOCKDRIVER
MILITARYANDCOMMERCIALTEMPERATURERANGES
PINCONFIGURATION
INDEX
1
2
20
19
18
17
16
VCC
OA1
VCC
OB1
OB2
OB3
19
20
2
3
3
OA2
OA3
GND
OA4
OB2
OB3
GND
OB4
OB5
18
17
16
15
14
OA3
4
5
6
7
8
1
4
5
6
GND
OA4
GND
OB4
15
14
13
12
OA5
(1)
GND
7
OA5
GND(1)
OEA
OB5
8
MON
9
10 11 12 13
9
OEB
INB
10
INA
11
QSOP/ SOIC/ SSOP/ CERDIP
TOP VIEW
LCC
TOP VIEW
NOTE:
1. Pin 8 is internally connected to GND. To insure compatibility with all products, pin
8 should be connected to GND at the board level.
ABSOLUTEMAXIMUMRATINGS(1)
PINDESCRIPTION
Pin Names
Description
Symbol
VTERM
TSTG
Description
Max
Unit
V
OEA, OEB
INA, INB
OAx, OBx
MON
3-StateOutputEnableInputs(ActiveLOW)
ClockInputs
TerminalVoltagewithRespecttoGND
StorageTemperature
–0.5 to +7
–65to+150
–60to+120
°C
mA
ClockOutputs
IOUT
NOTE:
DCOutputCurrent
MonitorOutput
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
FUNCTION TABLE(1)
Inputs
Outputs
OEA, OEB
INA, INB
OAx, OBx
MON
L
L
L
H
L
L
H
Z
Z
L
H
L
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Conditions Typ.
Max. Unit
H
H
InputCapacitance
OutputCapacitance
VIN = 0V
4.5
5.5
6
8
pF
pF
H
H
COUT
VOUT = 0V
NOTE:
NOTE:
1. H = HIGH
L = LOW
1. This parameter is measured at characterization but not tested.
Z = High-Impedance
2
IDT49FCT805BT/CT
MILITARYANDCOMMERCIALTEMPERATURERANGES
FAST CMOSBUFFER/CLOCKDRIVER
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Commercial: TA = 0°C to +70°C, Military: TA = -55°C to +125°C, VCC = 5V ± 10%
Symbol
VIH
VIL
Parameter
TestConditions(1)
Min.
2
Typ.(2)
—
Max.
—
0.8
1
Unit
V
Input HIGH Level
Guaranteed Logic HIGH Level
GuaranteedLogicLOWLevel
InputLOWLevel
—
—
V
IIH
Input HIGH Current(5)
InputLOWCurrent(5)
HighImpedanceOutputCurrent
(3-StateOutputPins)
Input HIGH Current
ClampDiodeVoltage
ShortCircuitCurrent
VCC = Max.
VCC = Max.
VCC = Max.
VI = 2.7V
—
—
µA
µA
µA
IIL
VI = 0.5V
VO = 2.7V
VO = 0.5V
—
—
1
IOZH
IOZL
II
—
—
1
—
—
1
VCC = Max., VI = VCC (Max.)
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
—
—
1
µA
V
VIK
IOS
—
–0.7
–120
3.3
–1.2
–255
—
–60
2.4
mA
V
VCC = Min.
IOH = –12mA MIL
VOH
VOL
Output HIGH Voltage
VIN = VIH or VIL
IOH = –15mA COM'L
IOH = –24mA MIL
IOH = –32mA COM'L(4)
IOL = 32mA MIL
2
3
—
V
V
OutputLOWVoltage
VCC = Min.
—
0.3
0.55
VIN = VIH or VIL
IOL = 48mA COM'L
IOFF
VH
Input/OutputPowerOffLeakage(5)
InputHysteresisforallinputs
VCC = 0V, VIN or VO ≤4.5V
—
—
—
—
—
150
5
1
—
µA
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
500
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition should not exceed one second.
5. The test limit for this parameter is ±5µA at TA = -55°C.
3
IDT49FCT805BT/CT
FAST CMOSBUFFER/CLOCKDRIVER
MILITARYANDCOMMERCIALTEMPERATURERANGES
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
VCC = Max.
VIN = 3.4V(3)
—
1
2
mA
TTL Inputs HIGH
ICCD
Dynamic Power Supply Current(4)
VCC = Max.
VIN = VCC
—
60
100
µA/MHz
OutputsOpen
VIN = GND
OEA = OEB = GND
50% Duty Cycle
VCC = Max.
IC
TotalPowerSupplyCurrent(6)
VIN = VCC
—
—
—
—
1.5
1.8
33
3
OutputsOpen
VIN = GND
fO = 25MHz
50% Duty Cycle
OEA = OEB = VCC
Mon.OutputToggling
VCC = Max.
VIN = 3.4V
VIN = GND
4
VIN = VCC
55.5(5)
57.5(5)
mA
OutputsOpen
VIN = GND
fO = 50MHz
50% Duty Cycle
OEA = OEB = GND
ElevenOutputsToggling
VIN = 3.4V
VIN = GND
33.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO = Output Frequency
NO = Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
4
IDT49FCT805BT/CT
MILITARYANDCOMMERCIALTEMPERATURERANGES
FAST CMOSBUFFER/CLOCKDRIVER
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE-MILITARY(1,2)
FCT805BT
FCT805CT
(4)
(4)
Symbol Parameter
Conditions(3)
CL = 50pF
Min.
Max.
Min.
Max.
Unit
tPLH
tPHL
tR
PropagationDelay
1.5
5.7
1.5
5.2
ns
INA to OAx, INB to OBx
RL = 500Ω
OutputRiseTime
—
—
—
2
—
—
—
2
ns
ns
ns
tF
OutputFallTime
1.5
0.9
1.5
0.7
tSK(O)
Outputskew:skewbetweenoutputsofallbanksof
samepackage(inputstiedtogether)
Pulseskew:skewbetweenoppositetransitions
ofsameoutput(|tPHL-–tPLH|)
tSK(P)
—
—
0.9
1.5
—
—
0.8
1.2
ns
ns
tSK(PP)
Part-to-partskew:skewbetweenoutputsofdifferent
packagesatsamepowersupplyvoltage,
temperature,packagetypeandspeedgrade
OutputEnableTime
tPZL
tPZH
tPLZ
tPHZ
1.5
1.5
6.5
6.5
1.5
1.5
6
6
ns
ns
OEA to OAx, OEB to OBx
OutputDisableTime
OEA to OAx, OEB to OBx
NOTES:
1. tPLH, tPHL, and tSK(pp) are production tested. All other parameters are guaranteed but not production tested.
2. Propagation delay range indicated by Min. and Max. limit is dues to Vcc, operating temperature, and process parameters. These propagation delay limits do not imply
skew.
3. See Test Circuits and Waveforms.
4. Minimum limits are guaranteed but not tested on Propagation Delays.
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE-COMMERCIAL(1,2)
FCT805BT
FCT805CT
(4)
(4)
Symbol Parameter
Conditions(3)
CL = 50pF
Min.
Max.
Min.
Max.
Unit
tPLH
tPHL
tR
PropagationDelay
1.5
5
1.5
4.5
ns
INA to OAx, INB to OBx
RL = 500Ω
OutputRiseTime
—
—
—
1.5
1.5
0.7
—
—
—
1.5
1.5
0.5
ns
ns
ns
tF
OutputFallTime
tSK(O)
Outputskew:skewbetweenoutputsofallbanksof
samepackage(inputstiedtogether)
Pulseskew:skewbetweenoppositetransitions
ofsameoutput(|tPHL-–tPLH|)
tSK(P)
—
—
0.7
1.2
—
—
0.6
1
ns
ns
tSK(PP)
Part-to-partskew:skewbetweenoutputsofdifferent
packagesatsamepowersupplyvoltage,
temperature,packagetypeandspeedgrade
OutputEnableTime
tPZL
tPZH
tPLZ
tPHZ
1.5
1.5
6
6
1.5
1.5
5
5
ns
ns
OEA to OAx, OEB to OBx
OutputDisableTime
OEA to OAx, OEB to OBx
NOTES:
1. tPLH, tPHL, and tSK(pp) are production tested. All other parameters are guaranteed but not production tested.
2. Propagation delay range indicated by Min. and Max. limit is dues to Vcc, operating temperature, and process parameters. These propagation delay limits do not imply
skew.
3. See Test Circuits and Waveforms.
4. Minimum limits are guaranteed but not tested on Propagation Delays.
5
IDT49FCT805BT/CT
FAST CMOSBUFFER/CLOCKDRIVER
MILITARYANDCOMMERCIALTEMPERATURERANGES
TESTCIRCUITSANDWAVEFORMS
SWITCHPOSITION
VCC
7V
Test
Switch
Disable LOW
Enable LOW
Closed
500
VIN
VOUT
Pulse
Generator
Disable HIGH
Enable HIGH
GND
D.U.T.
50pF
CL
500
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
3V
1.5V
0V
1.5V
0V
INPUT
INPUT
tPLH1
tPLH1
tPHL
tPLH
VOH
1.5V
VOH
1.5V
VOL
2.0V
0.8V
OUTPUT 1
OUTPUT 2
VOL
VOH
tSK(o)
tSK(o)
OUTPUT
1.5V
VOL
tR
tF
Package Delay
tPHL2
tPLH2
tSK(o) = tPLH2 - tPLH1 or tPHL2 - tPHL1
3V
1.5V
0V
INPUT
Output Skew
tPLH
tPHL
VOH
1.5V
VOL
3V
OUTPUT
1.5V
0V
tSK(p) = tPHL - tPLH
INPUT
tPLH1
tPHL1
Pulse Skew - tSK(P)
VOH
1.5V
PACKAGE 1
OUTPUT
VOL
VOH
DISABLE
tPLZ
ENABLE
tSK(pp)
tSK(pp)
3V
CONTROL
1.5V
0V
PACKAGE 2
OUTPUT
1.5V
VOL
INPUT
tPZL
3.5V
1.5V
OUTPUT
NORMALLY
LOW
tPHL2
tPLH2
3.5V
VOL
SWITCH
CLOSED
0.3V
0.3V
tSK(pp) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHZ
tPZH
OUTPUT
NORMALLY
HIGH
Part-to-Part Skew - tSK(PP)
SWITCH
OPEN
VOH
0V
1.5V
0V
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤1.0MHz; tF ≤2.5ns; tR ≤2.5ns
6
IDT49FCT805BT/CT
MILITARYANDCOMMERCIALTEMPERATURERANGES
FAST CMOSBUFFER/CLOCKDRIVER
ORDERINGINFORMATION
XXXX
XX
X
IDT49FCT
Package
Process
Device Type
Blank
B
Commercial (0°C to +70°C)
MIL-STD-883, Class B (– 55°C to +125°C)
Commercial Options
Small Outline IC
SOIC - Green
SO
SOG
Q
Quarter-size Small Outline Package
QG
QSOP - Green
Shrink Small Outline Package
SSOP - Green
PY
PYG
Military Options
CERDIP
Leadless Chip Carrier
D
L
Fast CMOS Buffer/Clock Driver
805BT
805CT
NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
clockhelp@idt.com
www.idt.com
7
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