IDT49FCT805CTPYI [IDT]
Low Skew Clock Driver, FCT Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, SSOP-20;
| 型号： | IDT49FCT805CTPYI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, FCT Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, SSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS
BUFFER CLOCK/DRIVER
IDT49FCT805BT/CT
DESCRIPTION:
FEATURES:
This buffer/clock driver is built using advanced dual metal CMOS
technology. The FCT805T is a non-inverting clock driver consisting of two
banksofdrivers. EachbankdrivesfiveoutputbuffersfromastandardTTL
compatibleinput. Thisparthasextremelylowoutputskew,pulseskew,and
package skew. The device has a “heart-beat” monitor for diagnostics and
PLLdriving. Themonitoroutputisidenticaltoallotheroutputsandcomplies
withtheoutputspecificationsinthisdocument.
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0.5 MICRON CMOS Technology
Guaranteed low skew < 500ps (max.)
Very low duty cycle distortion < 600ps (max.)
Low CMOS power levels
TTL compatible inputs and outputs
TTL level output voltage swings
High drive: -32mA IOH, +48mA IOL
Two independent output banks with 3-state control
1:5 fanout per bank
The FCT805T is designed for fast, clean edge rates to provide accurate
clock distribution in high speed systems.
“Heartbeat” monitor output
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
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Available in the following packages:
·
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Commercial: SOIC, SSOP, QSOP
Military: CERDIP, LCC, CERPACK
FUNCTIONALBLOCKDIAGRAM
OEA
INA
5
OA1-OA5
5
INB
OB1-OB5
OEB
MON
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 2000
1
c
1999 Integrated Device Technology, Inc.
DSC-4771
IDT49FCT805BT/CT
FASTCMOSBUFFER/CLOCKDRIVER
MILITARYANDCOMMERCIALTEMPERATURERANGES
PINCONFIGURATION
INDEX
1
2
20
19
18
17
16
VCC
OA1
VCC
OB1
OB2
OB3
19
2
3
20
3
OA2
OB2
OB3
GND
OB4
OB5
18
17
16
15
14
OA3
4
5
6
7
8
1
4
5
6
OA3
SO20-2
SO20-7
SO20-8
E20-1
GND
OA4
GND
GND
OB4
L20-2
OA4
15
14
13
12
D20-1
OA5
7
OA5
OB5
GND(1)
GND(1)
OEA
INA
8
MON
9
10 11 12 13
9
OEB
INB
10
11
SOIC/ SSOP/ QSOP/ CERPACK/ CERDIP
TOP VIEW
LCC
TOP VIEW
NOTE:
1. Pin 8 is internally connected to GND. To insure compatibility with all
products, pin 8 should be connected to GND at board level.
ABSOLUTE MAXIMUM RATINGS(1)
PIN DESCRIPTION
Symbol
Rating
Max.
Unit
Pin Names
Description
VTERM
Terminal Voltage with Respect to GND
–0.5 to +7
V
OEA, OEB
INA, INB
OAx, OBx
MON
3-State Output Enable Inputs (Active LOW)
Clock Inputs
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–65 to +120
°C
Clock Outputs
mA
Monitor Output
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability. No
terminal voltage may exceed Vcc by +0.5V unless otherwise noted.
(1)
FUNCTION TABLE
Inputs
Outputs
OEA, OEB
INA, INB
OAx, OBx
MON
L
L
L
H
L
L
H
Z
Z
L
H
L
H
H
CAPACITANCE (TA = +25OC, f = 1.0MHz)
H
H
Parameter(1)
Conditions
Typ.
Max. Unit
NOTE:
Symbol
1. H = HIGH Voltage Level
L = LOW Voltage Level
Z = High-Impedance
CIN
Input Capacitance
VIN = 0V
4.5
6
8
pF
pF
COUT
Output Capacitance
VOUT = 0V
5.5
NOTE:
1. This parameter is measured at characterization but not tested.
2
IDT49FCT805BT/CT
FASTCMOSBUFFER/CLOCKDRIVER
MILITARYANDCOMMERCIALTEMPERATURERANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = -55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
Typ.(2)
Max.
Unit
VIH
2
—
—
V
VIL
II H
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
—
—
0.8
±1
V
Input HIGH Current(5)
Input LOW Current(5)
High Impedance Output Current
(3-State Output Pins)
Input HIGH Current
VI = 2.7V
VI = 0.5V
VO = 2.7V
VO = 0.5V
µA
µA
µA
II L
VCC = Max.
—
—
±1
IOZH
IOZL
II
VCC = Max.
—
—
±1
—
—
±1
VCC = Max., VI = VCC (Max.)
VCC = Min., IIN = –18mA
VCC = Max.(3), VO = GND
—
—
±1
µA
V
VIK
IOS
VOH
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
—
–0.7
–120
3.3
–1.2
–225
—
–60
2.4
mA
V
VCC = Min.
VIN = VIH or VIL
IOH = –12mA MIL
IOH = –15mA COM’L
IOH = –24mA MIL
IOH = –32mA COM’L (4)
IOL = 32mA MIL
2
3
—
V
V
VOL
Output LOW Voltage
VCC = Min.
—
0.3
0.55
VIN = VIH or VIL
IOH = 48mA COM’L
IOFF
VH
Input/Output Power Off Leakage(5)
Input Hysteresis for all inputs
VCC = 0V, VIN or VO £ 4.5V
—
—
—
—
150
5
±1
—
µA
mV
µA
—
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
500
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. Duration of the condition should not exceed one second.
5. The test limit for thie parameter is ±5µA at TA = -55°C.
3
IDT49FCT805BT/CT
FASTCMOSBUFFER/CLOCKDRIVER
MILITARYANDCOMMERCIALTEMPERATURERANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
VCC = Max.
VIN = 3.4V(3)
—
0.5
2
mA
DICC
ICCD
Dynamic Power Supply Current(4)
VCC = Max.
VIN = VCC
—
60
100
µA/
Outputs Open
OEA = OEB = GND
50% Duty Cycle
VIN = GND
MHz/bit
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
fo = 25MHz
VIN = VCC
VIN = GND
—
—
1.5
1.8
3
4
mA
50% Duty Cycle
OEA = OEB =VCC
VIN = 3.4V
VIN = GND
Mon. Output Toggling
VCC = Max.
Outputs Open
fo = 50MHz
VIN = VCC
VIN = GND
—
—
33
55.5(5)
57.5(5)
50% Duty Cycle
OEA = OEB = GND
Eleven Outputs Toggling
VIN = 3.4V
VIN = GND
33.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + DICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH, and ICCZ)
DICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO = Output Frequency
NO = Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
4
IDT49FCT805BT/CT
FASTCMOSBUFFER/CLOCKDRIVER
MILITARYANDCOMMERCIALTEMPERATURERANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1, 2)
(MILITARY)
FCT805BT
FCT805CT
(4)
(4)
Min.
Max.
Min.
Max.
Symbol
tPLH
tPHL
Parameter
Condition(3)
CL = 50pF
Unit
Propagation Delay
INA to OAx, INB to OBx
Output Rise Time
1.5
5.7
1.5
5.2
ns
RL = 500W
tR
—
—
2
—
—
2
ns
ns
tF
Output Fall Time
1.5
1.5
tSK(o)
Output skew: skew between outputs of all banks of same package (inputs
tied together)
—
—
—
0.9
0.9
1.5
—
—
—
0.7
0.8
1.2
ns
ns
ns
tSK(p)
Pulse skew: skew between opposite transitions of same output (|tPHL–tPLH|)
tSK(pp) Part-to-part skew: skew between outputs of different packages at same
power supply voltage, temperature, package type and speed grade
tPZL
tPZH
tPLZ
tPHZ
Output Enable Time
OEA to OAx, OEB to OBx
Output Disable Time
1.5
1.5
6.5
6.5
1.5
1.5
6
6
ns
ns
OEA to OAx, OEB to OBx
NOTES:
1. tPLH, tPHL, and tSK(pp) are production tested. All other parameters are guaranteed but not production tested.
2. Propagation delay range indicated by Min. and Max. limit is dues to Vcc, operating temperature, and process parameters. These propagation
delay limits do not imply skew.
3. See Test Circuits and Waveforms.
4. Minimum limits are guaranteed but not tested on Propagation Delays.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1, 2)
(COMMERCIAL)
FCT805BT
FCT805CT
(4)
(4)
Min.
Max.
Min.
Max.
Symbol
tPLH
tPHL
Parameter
Condition(3)
CL = 50pF
Unit
Propagation Delay
INA to OAx, INB to OBx
Output Rise Time
1.5
5
1.5
4.5
ns
RL = 500W
tR
—
—
1.5
1.5
—
—
1.5
1.5
ns
ns
tF
Output Fall Time
tSK(o)
Output skew: skew between outputs of all banks of same package (inputs
tied together)
—
—
—
0.7
0.7
1.2
—
—
—
0.5
0.6
1
ns
ns
ns
tSK(p)
Pulse skew: skew between opposite transitions of same output (|tPHL–tPLH|)
tSK(pp) Part-to-part skew: skew between outputs of different packages at same
power supply voltage, temperature, package type and speed grade
tPZL
tPZH
tPLZ
tPHZ
Output Enable Time
OEA to OAx, OEB to OBx
Output Disable Time
1.5
1.5
6
6
1.5
1.5
5
5
ns
ns
OEA to OAx, OEB to OBx
NOTES:
1. tPLH, tPHL, and tSK(pp) are production tested. All other parameters are guaranteed but not production tested.
2. Propagation delay range indicated by Min. and Max. limit is dues to Vcc, operating temperature, and process parameters. These propagation
delay limits do not imply skew.
3. See Test Circuits and Waveforms.
4. Minimum limits are guaranteed but not tested on Propagation Delays.
5
IDT49FCT805BT/CT
FASTCMOSBUFFER/CLOCKDRIVER
MILITARYANDCOMMERCIALTEMPERATURERANGES
TESTCIRCUITSANDWAVEFORMS
ENABLE AND DISABLE TIMES
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
VCC
7V
500W
TEST
SWITCH
VIN
VOUT
Pulse
Generator
Disable LOW
Enable LOW
Closed
D.U.T.
50pF
CL
500W
RT
Disable HIGH
Enable HIGH
Open
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
PACKAGEDELAY
OUTPUTSKEW
3V
3V
1.5V
0V
1.5V
0V
INPUT
INPUT
tPLH1
tPLH1
tPHL
tPLH
VOH
1.5V
VOH
1.5V
VOL
2.0V
0.8V
OUTPUT 1
OUTPUT 2
VOL
VOH
tSK(o)
tSK(o)
OUTPUT
1.5V
VOL
tR
tF
tPHL2
tSK(o) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPLH2
PULSE SKEW - tSK(p)
3V
1.5V
0V
INPUT
tPLH
tPHL
PART-TO-PART SKEW - tSK(pp)
VOH
1.5V
VOL
3V
OUTPUT
1.5V
0V
tSK(p) = tPHL - tPLH
INPUT
tPLH1
tPHL1
VOH
1.5V
ENABLEANDDISABLETIMES
PACKAGE 1
OUTPUT
VOL
VOH
DISABLE
ENABLE
tSK(pp)
tSK(pp)
3V
CONTROL
INPUT
1.5V
0V
PACKAGE 2
OUTPUT
1.5V
VOL
tPZL
tPLZ
3.5V
1.5V
OUTPUT
NORMALLY
LOW
tPHL2
tSK(pp) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPLH2
3.5V
VOL
SWITCH
CLOSED
0.3V
tPHZ
tPZH
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
0.3V
VOH
0V
1.5V
0V
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate £ 1.0MHz; tF £ 2.5ns; tR £ 2.5ns
6
IDT49FCT805BT/CT
FASTCMOSBUFFER/CLOCKDRIVER
MILITARYANDCOMMERCIALTEMPERATURERANGES
ORDERINGINFORMATION
XXXX
XX
X
IDT49FCT
Package
Process
Device Type
Blank
B
Commercial (0°C to +70°C)
MIL-STD-883, Class B (– 55°C to +125°C)
Commercial Options
Small Outline IC (SO20-2)
Quarter-size Small Outline Package (SO20-8)
Shrink Small Outline Package (SO20-7)
SO
Q
PY
Military Options
D
E
L
CERDIP (D20-1)
CERPACK (E20-1)
Leadless Chip Carrier (L20-2)
Fast CMOS Buffer/Clock Driver
805BT
805CT
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www.idt.com*
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
7
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