ICS91857YLLFT [IDT]
PLL Based Clock Driver, 91857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 4.40 MM, 0.40 MM PITCH, ROHS COMPLIANT, MO-153, TVSOP-48;
| 型号： | ICS91857YLLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 91857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 4.40 MM, 0.40 MM PITCH, ROHS COMPLIANT, MO-153, TVSOP-48 驱动 光电二极管 逻辑集成电路 电视 |
| 文件： | 总14页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS91857
Integrated
Circuit
Systems, Inc.
Value SSTL_2 Clock Driver (60MHz - 220MHz)
RecommendedApplication:
Zero delay board fan-out memory modules
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ProductDescription/Features:
•
•
•
•
Meets PC3200 specification for DDRI-400 support
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization
GND
GND
CLKC2
CLKT2
VDD
CLKC7
CLKT7
VDD
•
•
PD#forpowermanagement
Spread Spectrum tolerant inputs
VDD
PD#
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
•
Auto PD when input signal removed
SwitchingCharacteristics:
•
•
CYCLE - CYCLE jitter (>100MHz):<75ps
OUTPUT - OUTPUT skew: <100ps
48-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
Functionality
Block Diagram
INPUTS
OUTPUTS
PLL State
AVDD PD# CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
FB_OUTT
GND
GND
H
H
L
H
L
L
H
L
L
H
L
Bypassed/off
Bypassed/off
FB_OUTC
CLKT0
CLKC0
H
H
H
2.5V
(nom)
L
L
L
H
L
H
L
Z
Z
L
Z
Z
H
L
Z
Z
L
Z
Z
H
L
off
off
on
on
off
CLKT1
CLKC1
2.5V
(nom)
Control
CLKT2
CLKC2
2.5V
(nom)
H
H
X
H
L
PD#
Logic
2.5V
(nom)
CLKT3
CLKC3
H
H
Z
H
Z
2.5V
(nom)
<20MHz)(1)
Z
Z
CLKT4
CLKC4
FB_INT
FB_INC
CLKT5
CLKC5
PLL
CLK_INC
CLK_INT
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
0494C—08/15/05
ICS91857
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Power supply 2.5V up to DDR 333.
4, 11, 12, 15, 21,
28, 34, 38, 45,
VDD
GND
PWR
Power supply 2.6V for DDR-I at 400MHz.
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
PWR Ground
Analog power supply, 2.5V up to DDR 333.
Power supply 2.6V for DDR-I at 400MHz.
PWR Analog ground.
16
AVDD
PWR
17
AGND
27, 29, 39, 44, 46,
22, 20, 10, 5, 3
CLKT(9:0)
OUT
OUT
"True" Clock of differential pair outputs.
26, 30, 40, 43, 47,
23, 19, 9, 6, 2
CLKC(9:0)
"Complementary" clocks of differential pair outputs.
14
13
CLK_INC
CLK_INT
IN
IN
"Complementary" reference clock input
"True" reference clock input
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
33
FB_OUTC
OUT
"True" Feedback output, dedicated for external feedback. It switches at
the same frequency as the CLK. This output must be wired to FB_INT.
32
36
FB_OUTT
FB_INT
OUT
IN
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
35
37
FB_INC
PD#
IN
IN
Power Down. LVCMOS input
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
ICS91857 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten differential
pairofclockoutputs(CLKT[0:9], CLKC[0:9])andonedifferentialpairfeedbackclockoutput(FB_OUT, FB_OUTC).The
clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT, FB_INC) the 2.5-
VLVCMOSinput(PD#)andtheAnalogPowerinput(AVDD).Wheninput(PD#)islowwhilepowerisapplied, thereceivers
are disabled, the PLL is turned off and the differential clock outputs areTri-Stated.When AVDD is grounded, the PLL
is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will
enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input
buffers, will detect the low frequency condition and perform the same low power features as when the (PD#) input
is low. When the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on,
the inputs and outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT,
FB_INC) and the input clock pair (CLK_INC, CLK_INT).
The PLL in the ICS91857 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]). The
ICS91857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS91857 ischaracterizedforoperationfrom0°Cto70°CandwillmeetJEDECStandard82-1and82-1AforRegistered
DDRClockDriver.
0494C—08/15/05
2
ICS91857
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Ambient Operating Temperature . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratings are stress specifications only and functional operation of the device at these or any other conditions above
those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Electrical Characteristics for DDR200/266/333 - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5V 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
VI = VDD or GND
VI = VDD or GND
MIN
5
TYP
MAX
5
UNITS
µA
Input High Current
IIH
IIL
Input Low Current
Operating Supply
Current
µA
IDD2.5 CL = 0pf @ 200MHz
IDDPD CL = 0pf
260
mA
mA
mA
100
Output High Current
Output Low Current
IOH
IOL
VDD = 2.3V, VOUT = 1V
VDD = 2.3V, VOUT = 1.2V
-18
26
-32
35
mA
High Impedance
Output Current
Input Clamp Voltage
IOZ
VIK
VDD=2.7V, Vout=VDD or GND
VDDQ = 2.3V Iin = -18mA
10
mA
-1.2
V
V
V
DD = min to max,
VDDQ - 0.1
1.7
High-level output
voltage
IOH = -1 mA
VOH
VDDQ = 2.3V,
IOH = -12 mA
VDD = min to max
IOL=1 mA
V
V
V
0.1
0.6
Low-level output voltage
VOL
VDDQ = 2.3V
IOH=12 mA
Input Capacitance1
Output Capacitance1
CIN
COUT
VI = GND or VDD
3
3
pF
pF
VOUT = GND or VDD
1Guaranteed by design at 170MHz, not 100% tested in production.
0494C—08/15/05
3
ICS91857
Electrical Characteristics for DDRI-400 - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.6V 0.1V
PARAMETER
SYMBOL
CONDITIONS
VI = VDD or GND
VI = VDD or GND
MIN
5
TYP
MAX
5
UNITS
µA
Input High Current
IIH
IIL
Input Low Current
Operating Supply
Current
µA
IDD2.5 CL = 0pf @ 200MHz
IDDPD CL = 0pf
260
mA
mA
mA
100
Output High Current
Output Low Current
IOH
IOL
VDD = 2.3V, VOUT = 1V
VDD = 2.3V, VOUT = 1.2V
-18
26
-32
35
mA
High Impedance
Output Current
Input Clamp Voltage
IOZ
VIK
VDD=2.7V, Vout=VDD or GND
VDDQ = 2.3V Iin = -18mA
10
mA
-1.2
V
V
V
DD = min to max,
OH = -1 mA
DDQ = 2.3V,
OH = -12 mA
DD = min to max
OL=1 mA
DDQ = 2.3V
OH=12 mA
V
DDQ - 0.1
1.7
High-level output
voltage
I
VOH
V
V
V
V
I
V
0.1
0.6
I
Low-level output voltage
VOL
V
I
Input Capacitance1
Output Capacitance1
CIN
COUT
VI = GND or VDD
3
3
pF
pF
VOUT = GND or VDD
1Guaranteed by design at 220MHz, not 100% tested in production.
0494C—08/15/05
4
ICS91857
Recommended Operating Condition for DDR200/266/333
(see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5V 0.2V (unless otherwise stated)
PARAMETER
Supply Voltage
SYMBOL
DDQ, AVDD
CONDITIONS
MIN
2.3
TYP
MAX
2.7
UNITS
V
V
V
V
V
V
CLKT, CLKC, FB_INC
VDDQ/2 - 0.18
0.7
Low level input voltage
High level input voltage
VIL
PD#
-0.3
DDQ/2 + 0.18
1.7
CLKT, CLKC, FB_INC
PD#
V
VIH
V
DDQ + 0.6
VDDQ
DC input signal voltage
(note 2)
-0.3
V
Differential input signal
voltage (note 3)
DC - CLKT, FB_INT
AC - CLKT, FB_INT
0.36
0.7
V
V
DDQ + 0.6
DDQ + 0.6
V
V
VID
VOX
VIX
IOH
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
High level output
current
VDDQ/2 - 0.15
VDDQ/2 - 0.2
VDDQ/2 + 0.15
VDDQ/2 + 0.2
0.12
V
V
mA
Low level output current
IOL
SR
TA
12
4
mA
V/ns
°C
Input slew rate
Operating free-air
temperature
1
0
70
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VCC and is the
voltage at which the differential signal must be crossing.
0494C—08/15/05
5
ICS91857
Recommended Operating Condition for DDRI-400
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.6V 0.1V
(see note1)
PARAMETER
Supply Voltage
SYMBOL
DDQ, AVDD
CONDITIONS
MIN
2.5
TYP
2.6
MAX
2.7
UNITS
V
V
V
V
V
V
CLKT, CLKC, FB_INC
VDDQ/2 - 0.18
0.7
Low level input voltage
High level input voltage
VIL
PD#
-0.3
VDDQ/2 + 0.18
CLKT, CLKC, FB_INC
PD#
VIH
1.7
V
DDQ + 0.3
VDDQ
DC input signal voltage
(note 2)
-0.3
V
Differential input signal
voltage (note 3)
DC - CLKT, FB_INT
AC - CLKT, FB_INT
0.36
0.7
V
V
DDQ + 0.6
DDQ + 0.6
V
V
VID
VOX
VIX
IOH
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
High level output
current
VDDQ/2 - 0.15
VDDQ/2 - 0.2
VDDQ/2 + 0.15
VDDQ/2 + 0.2
12
V
V
mA
Low level output current
IOL
SR
TA
-12
4
mA
V/ns
°C
Input slew rate
Operating free-air
temperature
1
0
70
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VCC and is the
voltage at which the differential signal must be crossing.
0494C—08/15/05
6
ICS91857
Timing Requirements for DDR200/266/333
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5V 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
freqop
MIN
60
MAX UNITS
Max clock frequency
170
170
60
MHz
2.5V 0.2V @ 25°C
Application Frequency
Range
Input clock duty cycle
freqApp
dtin
95
40
MHz
%
2.5V 0.2V @ 25°C
CLK stabilization
TSTAB
100
µs
Timing Requirements for DDRI-400
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.6V 0.1V
CONDITIONS
PARAMETER
SYMBOL
freqop
MIN
60
MAX UNITS
Max clock frequency
230
220
60
MHz
MHz
%
2.6V 0.1V
Application Frequency
Range
Input clock duty cycle
freqApp
dtin
95
40
2.6V 0.1V
CLK stabilization
TSTAB
100
µs
Switching Characteristics for DDR200/266/333
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX UNITS
Low-to high level
1
CLK_IN to any output
3.5
3.5
ns
ns
tPLH
propagation delay time
High-to low level propagation
delay time
1
CLK_IN to any output
tPLL
Output enable time
Output disable time
tEN
tdis
PD# to any output
PD# to any output
100 - 200 MHz
3
3
ns
ns
ps
Period jitter
Tjit (per)
t(jit_hper)
t(sir_I)
-75
-75
1
75
75
4
Half-period jitter
100 - 200 MHz
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter1
Static Phase Offset
Output to Output Skew
Pulse skew
V/ns
V/ns
ps
t(sl_o)
1
2
Tcyc-Tcyc
100 - 200 MHz
-75
-50
75
50
100
100
3
0
ps
t(spo)
Tskew
ps
Tskewp
ps
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. Switching characteristics guaranteed for application frequency range.
3. Static phase offset shifted by design.
0494C—08/15/05
7
ICS91857
Switching Characteristics for DDRI-400
PARAMETER
SYMBOL
CONDITION
MIN
TYP
3.5
MAX UNITS
ns
Low-to high level
1
CLK_IN to any output
tPLH
propagation delay time
High-to low level propagation
delay time
1
CLK_IN to any output
3.5
ns
tPLL
Output enable time
Output disable time
tEN
tdis
PD# to any output
PD# to any output
100 - 200 MHz
3
3
ns
ns
Period jitter
Tjit (per)
t(jit_hper)
t(sir_I)
-50
-75
1
50
75
4
ps
Half-period jitter
100 - 200 MHz
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter1
Static Phase Offset
Output to Output Skew
Pulse skew
V/ns
V/ns
ps
t(sl_o)
1
2
Tcyc-Tcyc
100 - 200 MHz
-75
-50
75
50
75
100
3
0
ps
t(spo)
Tskew
ps
Tskewp
ps
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. Switching characteristics guaranteed for application frequency range.
3. Static phase offset shifted by design.
0494C—08/15/05
8
ICS91857
Parameter Measurement Information
V
DD
V
(CLKC)
R = 60Ω
V
/2
R = 60Ω
DD
V
(CLKC)
ICS91857
GND
Figure 1. IBIS Model Output Load
VDD/2
C = 14 pF
ICS91857
-VDD/2
SCOPE
R = 10Ω Z = 50Ω
Z = 60Ω
Z = 60Ω
R = 50Ω
(TT)
V
R = 10Ω
Z = 50Ω
R = 50Ω
C = 14 pF
-VDD/2
V
(TT)
-VDD/2
NOTE: V
(TT) = GND
Figure 2. Output Load Test Circuit
YX, FBOUTC
YX, FBOUTT
t
t
c(n+1)
c(n)
t
= t
t
jit(cc) c(n) c(n+1)
Figure 3. Cycle-to-Cycle Jitter
0494C—08/15/05
9
ICS91857
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t
t
(
) n
(
) n+1
å 1n = N
N
(N is a large number of samples)
t
(
) n
t
=
)
(
Figure 4. Static Phase Offset
YX
#
YX
YX, FB_OUTC
YX, FB_OUTT
t(SK_O)
Figure 5. Output Skew
YX, FB_OUTC
YX, FB_OUTT
YX, FB_OUTC
YX, FB_OUTT
1
fO
1
fO
t(jit_per) =
tC(n) -
Figure 6. Period Jitter
0494C—08/15/05
10
ICS91857
Parameter Measurement Information
YX, FB_OUTC
YX, FB_OUTT
t
t
(hper_n+1)
(hper_n)
1
f
o
t(jit_Hper) t(jit_Hper_n)
1
2xfO
=
-
Figure 7. Half-Period Jitter
80%
80%
V , V
ID OD
20%
20%
Clock Inputs
and Outputs
t
t
slrf(i) slrf(o)
slrr(i)
Figure 8. Input and Output Slew Rates
0494C—08/15/05
11
ICS91857
c
In Millimeters
In Inches
N
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
E1
e
6.00
0.50 BASIC
6.20
.236
.244
a
D
0.020 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
A1
VARIATIONS
- C -
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
MAX
12.60
MIN
.488
MAX
.496
b
48
12.40
aaa
C
Reference Doc.: JEDEC Publication 95, M O-153
10 - 0 0 3 9
6.10 mm. Body, 0.50 mm. pitch TSSOP
(20 mil)
(240 mil)
Ordering Information
ICS91857yGLFT
Example:
ICS XXXX y G - PPP - LF - T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Pattern Number
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0494C—08/15/05
12
ICS91857
c
In Millimeters
In Inches
N
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.13
0.09
MAX
1.20
0.15
1.05
0.23
0.20
MIN
--
.002
.032
.005
.0035
MAX
.047
.006
.041
.009
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
22
E1
e
L
4.30
0.40 BASIC
0.45
4.50
.169
0.016 BASIC
.018
.177
α
D
0.75
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.08
0°
--
8°
.003
A
A2
VARIATIONS
A1
D mm.
D (inch)
- CC --
N
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
e
SEATING
PLANE
48
b
Reference Doc.: JEDEC Publication 95, M O-153
aaa
C
10 - 0 0 3 7
4.40 mm. Body, 0.40 mm. pitch TSSOP (TVSOP)
(16 mil)
(173 mil)
Ordering Information
ICS91857yLLFT
Example:
ICS XXXX y L - PPP - LF -T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Pattern Number
Package Type
L =TSSOP (TVSOP)
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0494C—08/15/05
13
ICS91857
Revision History
Rev.
Issue Date Description
Page #
C
8/15/2005 Added LF Ordering Information.
12-13
0494C—08/15/05
14
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Processor Specific Clock Generator, 533.3MHz, PDSO24, 0.150 INCH, GREEN, SSOP-24
IDT
ICS9212AF-13LFT-IN0
Processor Specific Clock Generator, 533.3MHz, PDSO24, 0.150 INCH, GREEN, SSOP-24
IDT
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