ICS9211YF-02 [IDT]
Processor Specific Clock Generator, 400MHz, PDSO24, 0.150 INCH, SSOP-24;
| 型号： | ICS9211YF-02 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 400MHz, PDSO24, 0.150 INCH, SSOP-24 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总6页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9211-02
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Direct Rambus™ Clock Generator
General Description
Features
•
•
Compatible with all Direct Rambus™ based IC s
The ICS9211-02 is a High-speed clock generator providing
400 MHz differential clock source for direct Rambus
memory system. It includes DDLL (Distributed Delay locked
loop) and phase detection mechanism to synchronize the
direct Rambus channel clock to an external system clock.
ICS 9211-02 provides a solution for a broad range of Direct
Rambus memory applications. The device works in
conjunction with the ICS9250-09.
Up to 400 MHz differential clock source for direct
Rambus™ memory system
•
•
•
Cycle to cycle jitter is less than 60ps
3.3 + 5% supply
Synchronization flexibility: Supports Systems that
need clock domains of Rambus channel to synchronize
with system or processor clock, or systems that do not
require synchronization of the Rambus clock to
another system clock
The ICS9211-02 power management support system turns
“off” the Rambus
channel clock to minimize power
consumption for mobile and other power –sensitive
applications. In “clock off” mode the device remains “on”
while the output is disabled, allowing fast transitions between
clock-off and clock –on states. In “power down” mode it
completely powers down for minimum power dissipation.
•
•
Excellent power management support
REFCLK input is from the ICS9250-09.
The ICS9211-02 meets the requirements for input frequency
tracking when the input frequency clock is using Spread
Spectrum clocking and also the optimum bandwidth is
maintained while attenuating the jitter of the reference signal.
Block Diagram
Pin Configuration
24-Pin 150 Mil SSOP
9211-02RevA04/23/99
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
ICS9211-02
Preliminary Product Preview
Pin Descriptions
Pin #
Name
VDDREF
REFCLK
VDD1
GND1
GND3
Type
REFV
IN
PWR
PWR
PWR
Description
Reference voltage for refclk, to be connected to CK133
Reference clock, to be connected to CK133
3.3 V power supply used for PLL
1
2
3
4
5
Ground for PLL
Ground for control inputs
Phase controller input, used to drive a phase aligner
that adjusts the phase of the busclk.
Ground for phase aligner
3.3 V power supply used for phase aligner
Reference voltage for phase detector inputs connected
to the controller
6,7
PCLK/M, SYNCLK/N
IN
8
9
GND2
VDD2
PWR
PWR
10
11
12
VDDPD
BUSCLK_ STOP#
PD#
REFV
IN
Active low output enable/disable
3.3V CMOS active low power down, the device is
powered down when the "(PD#) =0"
3.3V CMOS PLL Multiplier select, logic for selecting the
multiply ratio for the PLL from the input REFCLK
3.3V supply for clock out puts
IN
14,15
MULTI (0:1)
IN
16
17
VDD_OUT
GND_OUT
PWR
PWR
Ground for clock outputs
Out put clock connected to the Rambus channel. This
output is the complement of BUSCLK
NOT USED
Out put clock connected to the Rambus channel. This
output is the true component of BUSCLK
Ground for clock outputs
18
19
20
BUSCLKC
N/C
OUT
N/C
BUSCLKT
OUT
21
22
GND_OUT
VDD_OUT
PWR
PWR
3.3V supply for clock out puts
3.3V CMOS Mode control, used in selecting bypass,
test, normal, and output test (OE)
13,23,24
FS(0:2)
IN
2
ICS9211-02
Preliminary Product Preview
PLL DIVIDER SELECTION AND PLL VALUES ( PLLCLK = REFCLK*A/B)
Multo
Mult1
A
9
6
16
8
B
2
1
3
1
PLLCLK for REFCLK=50MHz
PLLCLK for REFCLK=66.6MHz
0
0
1
1
0
1
0
1
225
300
267
400
300
400
356
Reserved
BYPASS AND TEST MODE SELECTION
Mode
FS0
FS1
FS2
Bypclk (int.)
BusClk
BusClkB
Normal
0
0
0
Gnd
PAclk
PAclkB
Bypass
1
0
0
PLLclk
PLLclk
PLLclkB
Test
1
1
0
Refclk
Refclk
RefclkB
Vendor Test A
Vendor Test B
Reserved
0
0
1
-
-
-
-
-
-
1
0
1
-
-
-
-
1
1
1
Output Test (OE)
0
1
X
Hi-Z
Hi-Z
POWER MANAGEMENT MODES
State
PwrDnB
StopB
NORMAL
Clk Off
Powerdown
1
1
0
1
0
X
3
ICS9211-02
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics-input/supply/Outputs
Parameters
Symbol
Min
Max
Unit
Supply Voltage
VDD
3.15
3.45
V
Refclk Input cycle time
tCYCLE,IN
tJ,IN
10
-
40
250
60%
33
ns
ps
Input cycle-to-cycle Jitter
Input Duty cycle over 10k cycles
Input frequency of modulation
40%
30
DCIN
tCYCLE
KHz
Fm,in
Modulation index
PM,IN
tCYCLE,PD
Terr,init
0.25
30
0.5
100
0.5
%
ns
Phase detector input cycle time at PDclk/M & Synclk/N
Initial phase error at phase detector inputs
-0.5
tCYCLE,PD
Phase detector input duty cycle over 10k cycles
Input rise & fall times ( measured at 20%-80% of input voltage) for
PDCLK/M & SYNCLK/N,&REfCLK
DCIN,PD
25%
75%
tCYCLE,PD
T ,T
IR IF
-
1
ns
Input capacitance at PDCLK/M,Synclk/N,&REFCLK
CIN,PD
-
7
pF
pF
Input Capacitance matching at PCLK/M & SYNCLK/N
Input capacitance at CMOS pins
C
IN,PD
-
-
0.5
10
0.3
-
∆
CIN,CMOS
VIL
pF
Input (CMOS) signal low voltage
-
Vdd
Vdd
Input (CMOS) signal high voltage
0.7
VIH
REFCLK input low voltage
-
0.3
Vddi,R
VIL,R
REFCLK input high voltage
VIH,R
VIL,PD
VIH,PD
0.7
-
-
Vddi,R
Input signal low voltage for PD inputs and STOP
0.3
Vddi,PD
Input signal high voltage for PD inputs and STOP
Input supply referance for REFCLK
0.7
1.3
1.3
-
Vddi,PD
3.3
3.3
V
V
VDD,IR
Input supply referance vfor PD inputs
VDDI,PD
Phase detector phase error for distributed loop measured at
PDCLK/M & SYNCLK/N(rising
tERR,PD
-100
100
ps
Cycle cycle time
tCYCLE
2.5
3.75
60
ns
ps
ps
Cycle-to-cycle jitter at Busclk/BUSCLKB
Total jitter over 2,3, or 4clock cycles
tJ
-
-
tJ
100
Phase aligner, phase step size (BSCLK/BUSCLKB)
PLL out put phase error when tracking SSC
tSTEP
1
-
ps
ps
tERR,SSC
-100
100
Out put crossing-point voltage
Output voltage swing
VX
1.3
0.4
1.8
0.6
V
V
VCOS
Output high voltage
VH
DC
-
40%
-
2
V
tCYCLE
ps
Out put duty cycle over 10k cycle
60%
50
Output cycle -to-cycle duty cycle error
Output rise & fall times ( measured at 20%-80% of output voltage)
tDC,ERR
300
500
psd
t
CR,tCF
Difference between rise and fall times on a single device(20%-80%)
tCR,CF
-
100
ps
4
ICS9211-02
Preliminary Product Preview
General Layout Precautions:
1) Use a ground plane on the top layer of
the PCB in all areas not used by traces.
2) Make all power traces and vias as wide as
possible to lower inductance.
Capacitor Values:
C3 : 100pF ceramic
All unmarked capacitors are 0.01µF ceramic
Connections to VDD:
5
ICS9211-02
Preliminary Product Preview
COMMON
DIMENSIONS
VARIATIONS
D
S
SYMBOL
MIN. NOM. MAX.
MIN. NOM. MAX. MIN. NOM. MAX.
N
A
A1
A2
B
.061
.004
.055
.008
.0075
.064
.006
.058
.010
.008
.068
.0098
.061
.012
.0098
AA
AB
AC
AD
.189
.337
.337
.386
.194
.342
.342
.391
.196
.344
.344
.393
.0020 .0045 .0076
.0500 .0525 .0550
.0250 .0275 .0300
.0250 .0280 .0300
16
20
24
28
C
D
E
e
H
L
SEE VARIATIONS
.150
.155
.025 BSC
.236
.157
.230
.010
.244
.016
150 mil SSOP Package
.013
N
S
SEE VARIATIONS
SEE VARIATIONS
0°
0.85
5°
0.93
8°
.100
Diminisions are in inches
X
Ordering Information
ICS9211yF-02
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
6
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