ICS9211AFLF-T [IDT]
Processor Specific Clock Generator, 150MHz, PDSO48, 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48;
| 型号： | ICS9211AFLF-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 150MHz, PDSO48, 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总19页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS94211
Integrated
Circuit
Systems, Inc.
Programmable System Frequency Generator for PII/III™
Recommended Application:
440BX/VIA Apollo Pro133/ ALI 1631 style chipset.
Output Features:
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDREF
*PCI_STOP/REF0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDLAPIC
IOAPIC
REF1/FS2*
GND
•
2 - CPUs @2.5V
X1
X2
VDDPCI
•
•
•
•
•
•
1 - IOAPIC @ 2.5V
13 - SDRAM @ 3.3V
6 - PCI @3.3V,
1 - 48MHz, @3.3V
1 - 24MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
CPUCLK0
CPUCLK1
VDDLCPU
RESET#
SDRAM0
GND
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
GND
SDRAM5
SDRAM6
VDDSDR
SDRAM7
SDRAM8
VDD48
*MODE/PCICLK_F
**FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
Features:
BUFFER_IN
GND
•
•
•
Programmable ouput frequency.
Programmable ouput rise/fall time.
Programmable PCICLK, PCICLK_F,
SDRAM skew.
SDRAM12_F
SDRAM11
VDDSDR
SDRAM10
SDRAM9
GND
•
•
Real time system reset output
Spread spectrum for EMI control typically by 7dB to
8dB,
SDATA
SCLK
48MHz/FS0*
24MHz/FS1*
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
FS pins for frequency select
48-Pin 300mil SSOP
•
*
Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND
•
•
Key Specifications:
Functionality
•
•
•
•
CPU – CPU: <175ps
SDRAM - SDRAM: <500ps
PCI – PCI: <500ps
CPU
(MHz)
80.00
75.00
83.31
66.82
103.00
112.01
68.01
100.23
120.00
114.99
109.99
105.00
140.00
150.00
124.00
132.99
PCICLK
(MHz)
40.00
37.50
41.65
33.41
34.33
37.34
34.01
33.41
40.00
38.33
36.66
35.00
35.00
37.50
31.00
33.25
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Block Diagram
PLL2
48MHz
24MHz
/2
X1
X2
XTAL
OSC
IOAPIC
BUFFER IN
REF(1:0)
2
13
2
SDRAM (12:0)
CPUCLK (1:0)
PLL1
Spread
Spectrum
PCI
CLOCK
DIVDER
STOP
PCICLK (4:0)
PCICLK_F
RESET#
5
Control
Logic
4
FS(3:0)
MODE
PCI_STOP#
SDATA
Config.
Reg.
SCLK
0441F—08/24/05
ICS94211
General Description
The ICS94211 is a single chip clock solution for desktop designs using the BX/Apollo Pro133/ALI 1631 style chipset.
It provides all necessary clock signals for such a system.
The ICS94211 belongs to ICS new generation of programmable system clock generators. It employs serial
programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable from over clocking.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
OUT 14.318 Mhz reference clock.
REF0
2
Halts PCICLK(0:4) clocks at logic 0 level, when input low (In mobile
mode, MODE=0)
PCI_STOP#1
IN
3, 9, 16, 22,
33, 39, 45
GND
X1
PWR Ground
Crystal input, has internal load cap (36pF) and feedback
4
IN
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
5
X2
OUT
6, 14
VDDPCI
PCICLK_F
PWR Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V
Free running PCI clock not affected by PCI_STOP# for power
management.
OUT
7
Pin 7 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched
Input.
MODE1, 2
FS3
IN
IN
Frequency select pin. Latched Input. Internal Pull-down to GND
8
PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew
(CPU early)
PCICLK0
OUT
PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew
(CPU early)
13, 12, 11, 10
PCICLK (4:1)
BUFFER IN
OUT
IN
15
Input to Fanout Buffers for SDRAM outputs.
17, 18, 20, 21, 28,
29, 31, 32, 34, 35, SDRAM (12:0)
37, 38, 40
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset)
OUT
19, 30, 36
VDDSDR
SDATA
SCLK
PWR Supply for SDRAM (0:12) and CPU PLL Core, nominal 3.3V.
23
24
I/O
IN
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
24MHz output clock
24MHz
FS11, 2
48MHz
FS01, 2
VDD48
OUT
IN
25
26
Frequency select pin. Latched Input.
48MHz output clock
OUT
IN
Frequency select pin. Latched Input
27
41
PWR Power for 24 & 48MHz output buffers and fixed PLL core.
Real time system reset signal for frequency ratio change or
OUT
RESET
watchdog timmer timeout. This signal is active low.
42
43
44
VDDLCPU
CPUCLK1
CPUCLK0
REF1
PWR Supply for CPU clocks, 2.5V nominal
OUT
OUT
OUT
IN
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Free running CPU clock. Not affected by the CPU_STOP#
14.318 MHz reference clock.
46
FS21, 2
Frequency select pin. Latched Input
47
48
IOAPIC
OUT
IOAPIC clock output. 14.318 MHz Powered by VDDL.
VDDLAPIC
PWR Power pin for the IOAPIC outputs. 2.5V.
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0441F—08/24/05
2
ICS94211
General I2C serial interface information for the ICS94211
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending Byte 0 through Byte 20
(see Note)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• ICS clock sends Byte 0 through byte 8 (default)
• ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
How to Read:
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
Start Bit
Start Bit
Address D2(H)
Address D3(H)
ACK
ACK
Dummy Command Code
Byte Count
ACK
ACK
Dummy Byte Count
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
ACK
ACK
ACK
ACK
ACK
ACK
If 7H has been written to B6
ACK
Byte 7
Byte 18
Byte 19
Byte 20
ACK
ACK
ACK
If 12H has been written to B6
ACK
Byte18
Byte 19
Byte 20
If 13H has been written to B6
ACK
If 14H has been written to B6
Stop Bit
ACK
Stop Bit
*See notes on the following page.
0441F—08/24/05
3
ICS94211
Brief I2C registers description for ICS94211
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Functionality &
Frequency Select
Register
See individual
byte
description
See individual
byte
0
Active / inactive output control
registers/latch inputs read back.
Output Control Registers
1-6
7
description
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
See individual
byte
description
Vendor ID & Revision ID
Registers
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00H to
this byte.
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
Byte Count
Read Back Register
8
9
08H
10H
Watchdog Timer
Count Register
Watchdog enable, watchdog status
10 Bit [6:0] and programmable 'safe' frequency'
can be configured in this register.
Watchdog Control
Registers
000,0000
This bit select whether the output
VCO Control Selection
Bit
frequency is control by
hardware/byte 0 configurations or
10 Bit [7]
0
byte 11&12 programming.
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
Depended on
hardware/byte
0 configuration
VCO Frequency Control
Registers
11-12
Depended on
hardware/byte
0 configuration
Spread Spectrum
Control Registers
These registers control the spread
percentage amount.
13-14
Increment or decrement the group
skew amount as compared to the
initial skew.
See individual
byte
description
See individual
byte
Group Skews Control
Registers
15-16
17-20
Output Rise/Fall Time
Select Registers
These registers will control the
output rise and fall time.
description
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
4.
5.
6.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
7.
0441F—08/24/05
4
ICS94211
Byte 0: Functionality and frequency select register (Default=0)
Bit
Description
PWD
Bit7 Bit6 Bit5 Bit4
FS3 FS2 FS1 FS0
VCO/REF VCO CPUCLK PCICLK
Bit2
Divider
MHz
MHz
MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
447/40
440/42
512/44
392/42
446/31
485/31
513/54
518/37
352/21
514/32
507/33
484/33
352/18
440/21
433/25
483/26
396/21
345/19
440/25
478/29
486/30
491/37
440/35
463/39
371/16
447/20
433/20
310/15
469/23
362/18
476/24
347/18
160.01
150.00
166.61
133.64
206.00
224.01
136.02
200.45
240.00
229.99
219.98
210.00
280.00
300.00
247.99
265.99
270.00
259.99
252.00
236.00
231.95
190.01
180.00
169.98
332.00
320.01
309.99
80.00
75.00
83.31
40.00
37.50
41.65
33.41
34.33
37.34
34.01
33.41
40.00
38.33
36.66
35.00
35.00
37.50
31.00
33.25
33.75
32.50
31.50
39.33
38.66
31.67
30.00
28.34
41.50
40.00
38.75
36.99
36.50
35.99
35.50
34.50
66.82
103.00
112.01
68.01
100.23
120.00
114.99
109.99
105.00
140.00
150.00
124.00
132.99
135.00
129.99
126.00
118.00
115.98
95.00
Bit
(2,7:4)
Note 1
90.00
85.01
166.00
160.01
154.99
295.91 147.95
291.97
287.95
283.98
276.02
145.98
143.98
141.99
138.01
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
Bit 3
Bit 1
Bit 0
0
1
0
0- Normal
1- Spread spectrum enable 0.35% Center Spread
0- Running
1- Tristate all outputs
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0441F—08/24/05
5
ICS94211
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
X
1
1
1
1
1
1
1
Latched FS2#
(Reserved)
(Reserved)
(Reserved)
SDRAM0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
(Reserved)
PCICLK_F
(Reserved)
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
7
-
-
-
13
12
11
10
8
40
-
(Reserved)
CPUCLK1
CPUCLK0
43
44
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PIN# PWD
DESCRIPTION
(Reserved)
BIT PIN# PWD
DESCRIPTION
(Reserved)
-
-
1
X
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
Latched FS0#
48MHz
(Reserved)
(Reserved)
(Reserved)
Latched FS1#
(Reserved)
Latched FS3#
(Reserved)
26
25
-
1
1
24 MHz
1
1
(Reserved)
X
1
17, 21,
20, 18
28, 32,
31, 29,
34, 38,
37, 35
Bit 2
Bit 1
Bit 0
1
1
1
SDRAM (9:12)
SDRAM (5:8)
SDRAM (1:4)
X
1
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved (Note)
BIT PIN# PWD
DESCRIPTION
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
(Reserved)
(Reserved)
IOAPIC
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
-
47
-
(Reserved)
(Reserved)
REF1
-
46
2
REF0
Notes:
Note: This is an unused register writing to this register
will not affect device performance or functinality.
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
0441F—08/24/05
6
ICS94211
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
X
X
X
X
X
Vendor ID
Vendor ID
Vendor ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Byte 9: VCO Control Selection Bit &
Watchdog Timer Control Register
Byte 10: Watchdog Timer Count Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0=Hw/B0 freq / 1=B14&15 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
The decimal representation of these
8 bits correspond to 290ms or 1ms
the watchdog timer will wait before
it goes to alarm mode and reset the
frequency to the safe setting. Default
at power up is 16X 290ms = 4.6
seconds.
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
Byte 12: VCO Frequency Control Register
Byte 11: VCO Frequency Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
Note: The decimal representation of these 9 bits (Byte
12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO
divider value. For example if VCO divider value of 36
is desired, user need to program 36 - 8 = 28, namely, 0,
00011100 into byte 12 bit & byte 11 bit 7.
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
Notes:
1. PWD = Power on Default
0441F—08/24/05
7
ICS94211
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Spread Spectrum Bit7
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK_F Skew Control
SDRAM [8:11] Skew Control
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCICLK [0:4} Skew Control
SDRAM_F Skew Control
SDRAM [0:7} Skew Control
Byte 17:Output Rise/FallTime Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPUCLK_F: Slew Rate Control
PCI {0:4]: Slew Rate Control
CPUCLK1: Slew Rate Control
SDRAM [0:11] Slew Rate Control
SDRAM_F: Slew Rate Control
PCI_F Slew Rate Control
48MHz: Slew Rate Control
24MHz: Slew Rate Control
Notes:
1. PWD = Power on Default
2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting.
Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first
pass.
0441F—08/24/05
8
ICS94211
Byte 19: Reserved Register
Byte 20: Reserved Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Byte 19 and 20 are reserved registers, these
are unused registers writing to these registers
will not affect device performance or
functinality.
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 xVCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
To program theVCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy
programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware power up frequency.
2.Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew
rate.
7.The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be
changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew
relation programmedintobytes13-16couldbeunstable. Step3&7assurethecorrectspreadandskewrelationship.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and maxVCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or
too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4.ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program theVCO
frequency.
5.Spread percent needs to be calculated based onVCO frequency, spread modulation frequency and spreadamount
desired. See Application note for software support.
0441F—08/24/05
9
ICS94211
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
TYP
MAX
VDD + 0.3
0.8
UNITS
V
2
VSS - 0.3
-5
VIL
V
IIH
VIN = VDD
5
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = max cap loads;
CPU=66-133 MHz, SDRAM=100 MHz
CPU=133 MHz, SDRAM=133 MHz
-5
Input Low Current
mA
mA
IIL2
-200
124
350
Operating Supply
Current
IDD3.3OP
135
18
500
70
IDD2.5OP CL = max cap loads;
Powerdown Current
Input Frequency
Pin Inductance
IDD3.3PD CL = 0 pF; Input address to VDD or GND
mA
MHz
nH
pF
600
Fi
VDD = 3.3 V
14.318
Lpin
7
5
CIN
Logic Inputs
Input Capacitance1
COUT
CINX
Ttrans
Ts
Output pin capacitance
6
pF
X1 & X2 pins
27
45
3
pF
Transition time1
Settling time1
Clk Stabilization1
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
From VDD = 3.3 V to 1% target frequency
ms
ms
ms
ns
3
TSTAB
3
tPZH,tPZL Output enable delay (all outputs)
1
1
10
10
4
Delay1
Skew1
t
PHZ,tPLZ Output disable delay (all outputs)
ns
VT = 1.5V; VTL=1.25V
tcpu-pci
2.45
ns
1Guaranteed by design, not 100% tested in production.
0441F—08/24/05
10
ICS94211
Electrical Characteristics - CPU
TA = 0 - 70°C;VDD = 3.3V; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
RDSP2B
RDSN2B
VOH2B
CONDITIONS
MIN
13.5
13.5
2
TYP
15
MAX UNITS
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
45
45
Ω
Ω
V
V
16.5
2.48
0.04
-60
-7
VOL2B
0.4
-27
V
V
OH@MIN = 1 V
OH@MAX = 2.375V
Output High Current
IOH2B
IOL2B
mA
mA
-27
27
VOL@MIN = 1.2 V
OL@MAX =0.3V
63
Output Low Current
V
20
30
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr2B
tf2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
1.2
0.9
46.9
12.7
150
ns
ns
%
dt2B
tsk2B
VT = 1.25 V
175
250
ps
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
VT = 1.25 V, CPU 66, SDRAM 100
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70°C; VDD = 3.3 V +/-5%, CL = 40 pF for PCI0-1, CL = 10 - 30 pF for other PCIs (unless otherwise sta
PARAMETER
SYMBOL
RDSP1
RDSN1
VOH1
CONDITIONS
MIN
12
TYP
MAX UNITS
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
55
55
Ω
Ω
V
V
12
2.4
VOL1
0.55
-33
V
OH@MIN = 1 V
VOH@MAX = 3.135V
Output High Current
IOH1
IOL1
mA
mA
-33
30
V
V
OL@MIN = 1.95 V
OL@MAX =0.4V
Output Low Current
38
2
Rise Time1
Fall Time1
Duty Cycle1
VOL = 0.4 V, VOH = 2.4 V,
1.5
tr1
tf1
0.5
0.5
45
ns
ns
VOL = 2.4 V, VOH = 0.4 V, PCI0-3
VT = 1.5 V
1.5
52.5
49
2
dt1
55
%
ps
ps
Skew1
tsk1
VT = 1.5 V
500
500
Jitter, cycle-to-cycle1
tjcyc-cyc1 VT = 1.5 V
200
1Guaranteed by design, not 100% tested in production.
0441F—08/24/05
11
ICS94211
Electrical Characteristics - IOAPIC
TA = 0 - 70°C; VDD = 3.3V; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
RDSP4B
RDSN4B
VOH4B
CONDITIONS
MIN
9
TYP
MAX UNITS
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -5.5 mA
IOL = 9 mA
3
Ω
Ω
V
V
9
30
2
VOL4B
0.4
-21
VOH@MIN = 1.4 V
VOH@MAX = 2.5V
Output High Current
IOH4B
IOL4B
mA
mA
-36
36
V
OL@MIN = 1.0 V
Output Low Current
VOL@MAX =0.2V
31
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
tr4B
tf4B
dt4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
0.7
1.1
ns
ns
%
53.7
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70°C; VDD = 3.3 V +/-5%, CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
RDSP3
RDSN3
VOH3
CONDITIONS
MIN
10
TYP
MAX UNITS
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
24
24
Ω
Ω
V
V
10
2.4
VOL3
0.4
-46
V
V
V
V
OH@MIN = 2 V
Output High Current
IOH3
IOL3
mA
mA
OH@MAX = 3.135V
OL@MIN = 1 V
-54
54
Output Low Current
OL@MAX =0.4V
53
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr3
tf3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
0.4
0.4
45
0.8
0.8
ns
ns
%
dt3
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
51.7
166
3.1
tsk3
Tprop
250
5
ps
ns
Propagation Delay
1Guaranteed by design, not 100% tested in production.
0441F—08/24/05
12
ICS94211
Electrical Characteristics - REF, 24_48MHz, 48MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
RDSP5
RDSN5
VOH5
CONDITIONS
VO = VDD*(0.5)
MIN
20
TYP
MAX UNITS
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
60
60
Ω
Ω
V
V
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
20
2.4
VOL5
0.4
-23
V
V
OH @ MIN = 1.0 V
Output High Current
IOH5
IOL5
mA
mA
OH @ MAX = 3.135 V
-29
29
VOL @ MIN = 1.95 V
OL @ MAX = 0.4 V
Output Low Current
V
27
4
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
2
2
ns
ns
%
4
dt5
53
55
VT = 1.5 V, Fixed clocks
VT = 1.5 V, Ref clocks
200
500
Jitter, cycle-to-cycle1
tjcyc-cyc5
ps
1032 1250
1Guaranteed by design, not 100% tested in production.
0441F—08/24/05
0441C—10/09/03
13
ICS94211
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) on the ICS94211
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of Power-
On reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0441F—08/24/05
14
ICS94211
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94211. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS94211 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94211 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94211.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
0441F—08/24/05
15
ICS94211
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
c
SYMBOL
N
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
L
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
0.635 BASIC
0.025 BASIC
a
h x 45°
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
D
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
A1
D mm.
D (inch)
- C -
N
MIN
15.75
MAX
16.00
MIN
.620
MAX
.630
e
SEATING
PLANE
b
48
Reference Doc.: JEDEC Publication 95, M O-118
.10 (.004) C
10-0034
Ordering Information
ICS94211yFLF-T
Example:
ICS XXXX y F LF -T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0441F—08/24/05
16
ICS94211
Revision History
Rev.
Issue Date Description
Page #
F
8/24/2005 Added LF Ordering Information.
16
0441F—08/24/05
17
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94211 (Desktop Chipsets)
Description
440BX/VIA Apollo Pro133/ ALI 1631 style chipset.
Market Group
PC CLOCK
Additional Info
The ICS94211 is a single chip clock solution for desktop designs using the BX/Apollo Pro133/ALI 1631 style chipset. It provides all necessary
clock signals for such a system. The ICS94211 belongs to ICS new generation of programmable system clock generators. It employs serial
programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output
to output skew, changing spread spectrum amount, changing group divider ratio and dis/ enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking. •
Programmable ouput frequency. • Programmable ouput rise/fall time. • Programmable PCICLK, PCICLK_F, SDRAM skew. • Real time system
reset output • Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage. • Watchdog timer technology to
reset system if over-clocking causes malfunction. • Uses external 14.318MHz crystal. • FS pins for frequency select
Related Orderable Parts
Attributes
94211AF
94211AFLF
94211AFLFT
94211AFT
3.3 V (PV48)
3.3 V (PVG48)
3.3 V (PVG48)
3.3 V (PV48)
SSOP 48
NA
Voltage
Package
Speed
SSOP 48
NA
SSOP 48
NA
SSOP 48
NA
C
C
C
C
Temperature
Active
Yes
90
Active
Yes
90
Active
No
Active
No
Status
Sample
1000
1000
1000
Minimum Order Quantity
Factory Order Increment
30
30
1000
Related Documents
Type
Title
94211 Datasheet
Size
Revision Date
Datasheet
165 KB
11/08/2006
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