ICS889872AKT [IDT]
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION; 差分至LVDS缓冲器/分频器W /内部端接
| 型号： | ICS889872AKT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION |
| 文件： | 总14页 (文件大小：1088K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER
W/INTERNAL TERMINATION
ICS889872
General Description
Features
The ICS889872 is a high speed Differential-to-
• Three LVDS outputs
S
IC
LVDS Buffer/Divider w/Internal Termination and is a
member of the HiPerClockS™family of high
performance clock solutions from IDT. The
• Frequency divide select options: ÷4, ÷6: >2GHz,
HiPerClockS™
÷8, ÷16: >1.6GHz
• IN, nIN input can accept the following differential input levels:
ICS889872 has a selectable ÷2, ÷4, ÷8, ÷16 output
LVPECL, LVDS, CML
dividers. The clock input has internal termination resistors,
allowing it to interface with several differential signal types while
minimizing the number of required external components. The
device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
• Output frequency: >2GHz
• Cycle-to-cycle jitter: 1ps (typical)
• Total jitter: 10ps (typical)
• Output skew: 7ps (typical), QA/nQA outputs
• Part-to-part skew: 250ps (typical)
• Propagation Delay: 750ps (typical), QA/nQA outputs
• Full 2.5V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
Enable
16 15 14 13
nRESET/
FF
1
2
3
QB0
nQB0
QB1
12
11
10
IN
nDISABLE
VT
VREF_AC
nIN
Enable
MUX
QA
nQB1
4
9
5
6
7
8
nQA
QB0
IN
50Ω
nQB0
÷2, ÷4,
÷8, ÷16
VT
50Ω
ICS889872
nIN
QB1
16-Lead VFQFN
3mm x 3mm x 0.95mm package body
VREF_AC
S1
nQB1
K Package
Top View
Decoder
S0
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
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Table 1. Pin Descriptions
Number
Name
Type
Description
Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be
terminated with 100W across the pin (QB0/nQB0).
LVDS interface levels.
1, 2
QB0, nQB0
Output
Output
Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be
terminated with 100W across the pin (QB1nQB1).
LVDS interface levels.
3, 4
QB1, nQB1
5, 6
QA, nQA
VDD
Output
Power
Differential undivided output pair. LVDS interface levels.
Power supply pins.
7, 14
Output reset and enable/disable pin. When LOW, resets the divider select,
and align Bank A and Bank B edges. In addition, when LOW, Bank A and
Bank B will be disabled. Input threshold is VDD/2V.
nRESET/
nDISABLE
8
Input
Pullup
Includes a 37kΩ pullup resistor. LVTTL / LVCMOS interface levels.
9
nIN
VREF_AC
VT
Input
Output
Input
Inverting differential LVPECL clock input. RT = 50Ω termination to VT.
Reference voltage for AC-coupled applications. Equal to VDD – 1.4V
(approx.). Maximum sink/source current is 0.5mA.
10
11
12
13
Termination input. Leave pin floating.
Non-inverting LVPECL differential clock input.
RT = 50Ω termination to VT.
IN
Input
GND
Power
Power supply ground.
Select pins. Logic HIGH if left unconnected (÷16 mode). S0 = LSB.
Input threshold is VDD/2. 37kW pullup resistor.
LVCMOS/LVTTL interface levels.
15, 16
S1, S0
Input
Pullup
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
RPULLUP
Input Pullup Resistor
37
kΩ
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DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
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Function Tables
Table 3A. Control Input Function Table
Input
Outputs
nRESET
QA, QBx
Disabled; LOW
Enabled
nQA, nQBx
Disabled; HIGH
Enabled
0
1
NOTE: After nRESET switches, the clock outputs are disabled or
enabled following a falling input clock edge as shown in Figure 1.
Figure 1. nRESET Timing Diagram
V
/2
DD
nRESET
t
RR
IN
nIN
V
Swing
IN
t
PD
nQBx
QBx
V
Swing
OUT
QA
nQA
Table 3B. Truth Table
Inputs
Outputs
nRESET/nDISABLE
S1
0
S0
0
Bank A
Bank B
1
1
1
1
0
Input Clock
Input Clock
Input Clock
Input Clock
Input Clock ÷2
Input Clock ÷4
Input Clock ÷8
Input Clock ÷16
0
1
1
0
1
1
X
X
QA = LOW, nQA = HIGH; NOTE 1
QBx = LOW, nQBx = HIGH; NOTE 2
NOTE 1: On the next negative transition of the input signal.
NOTE 2: Asynchronous reset/disable function.Absolute Maximum Ratings
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DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Input Current, IN, nIN
50mA
VT Current, IVT
100mA
Input Sink/Source, IREF_AC
0.5mA
Operating Temperature Range, TA
Package Thermal Impedance, θJA, (Junction-to-Ambient)
Storage Temperature, TSTG
-40°C to +85°C
51.5°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
VDD Positive Supply Voltage
IDD Power Supply Current
Test Conditions
Minimum
Typical
2.5
Maximum
Units
V
2.375
2.625
80
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol
VIH
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
2
0
VDD + 0.3
V
V
VIL
0.8
5
IIH
VDD = VIN = 2.625V
µA
µA
IIL
VDD = 2.625V, VIN = 0V
-150
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Table 4C. Differential DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol
RIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
Differential Input Voltage Swing
Input Current
(IN, nIN)
(IN, nIN)
(IN, nIN)
100
Ω
V
VIH
1.2
0
VDD
VDD – 0.15
2.8
VIL
V
VIN
0.15
0.3
V
VDIFF_IN
IIN
V
(IN, nIN)
45
mA
V
VREF_AC
Bias Voltage
VDD – 1.35
Table 4D. LVDS DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol
VOUT
VOH
Parameter
Test Conditions
Minimum
Typical
350
Maximum
Units
mV
V
Output Voltage Swing
Output High Voltage
1.475
VOL
Output Low Voltage
0.925
V
VCCM
∆VOCM
Output Common Mode Voltage
Change in Common Mode Voltage
1.35
V
50
mV
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Parameter
Symbol
Test Conditions
÷2, ÷4
Minimum
Typical
>2
Maximum
Units
GHz
GHz
ps
Output Frequency
Input Frequency
fMAX
÷8, ÷16
>1.6
750
750
7
Input Swing: <400mV
Input Swing: ≥400mV
Propagation Delay;
NOTE 1, 2
tPD
IN-to-Q
ps
QB0-to-QB1
QA-to-QB
ps
Output Skew;
NOTE 2, 3, 4
tsk(o)
60
ps
tsk(pp)
tjit(cc)
tjit(j)
Part-to-Part Skew; NOTE 2, 4, 5
Cycle-to-Cycle Jitter; NOTE 2, 6
Total Jitter; NOTE 2
250
1
ps
ps
10
ps
tRR
Reset Recovery Time; NOTE 2
Output Rise/Fall Time; NOTE 2
600
ps
tR / tF
150
ps
All parameters characterized at ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Specs are design targets.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 6: The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
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Parameter Measurement Information
V
DD
,
SCOPE
nIN
Qx
V
DD
2.5V 5%
POWER SUPPLY
VIN
VIH
Cross Points
VIL
+
Float GND –
LVDS
IN
nQx
GND
LVDS Output Load AC Test Circuit
Differential Input Level
nQx
Qx
Part 1
nQx
Qx
nQy
Part 1
Qy
Qy
Qy
tsk(o)
tsk(pp)
Part-to-Part Skew
Output Skew
nQA,
nQB[0:1]
nIN
IN
QA,
QB[0:1]
➤
➤
nQA,
nQB[0:1]
tcycle n
tcycle n+1
➤
➤
tjit(cc) = tcycle n – tcycle n+1
QA,
QB[0:1]
1000 Cycles
tPD
Cycle-to-Cycle Jitter
Propagation Delay
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DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
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Parameter Measurement Information, continued
80%
80%
tR
VDIFF_IN, VDIFF_OUT
VOD
1600mV
(typical)
VIN, VOUT
Clock
Outputs
20%
20%
800mV
(typical)
tF
Single-Ended & Differential Input Voltage Swing
Output Rise/Fall Time
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
VDD
R1
1K
Single Ended Clock Input
R2/R1 = 0.609.
IN
V_REF
nIN
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
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Differential Input with Built-in 50Ω Termination Interface
The IN /nIN with built-in 50Ω terminations accepts LVDS, LVPECL,
LVHSTL, CML, SSTL and other differential signals. Both signals
must meet the VPP and VCMR input requirements. Figures 3A to 3E
show interface examples for the HiPerClockS IN/nIN input with
built-in 50Ω terminations driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm
the driver termination requirements.
2.5V
2.5V
2.5V
3.3V or 2.5V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
IN
IN
VT
nIN
VT
nIN
Receiver
With
Receiver
With
LVPECL
LVDS
R1
18
Built-In
50Ω
Built-In
50Ω
Figure 3A. HiPerClockS IN/nIN Input with Built-In 50Ω
Figure 3B. HiPerClockS IN/nIN Input with Built-In 50Ω
Driven by an LVDS Driver
Driven by an LVPECL Driver
2.5V
2.5V
2.5V
3.3V
3.3V LVPECL
C1
C2
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
IN
IN
50Ω
50Ω
VT
VT
nIN
nIN
Receiver
With
REF_AC
CML - Built-in 50Ω Pull-up
R5
100 - 200Ω
R5
100 - 200Ω
Receiver with
Built-In 50Ω
Built-In
50Ω
Figure 3C. HiPerClockS IN/nIN Input with Built-In 50Ω
Driven by a CML Driver with Built-In 50Ω
Pullup
Figure 3D. HiPerClockS IN/nIN Input with Built-In 50Ω
Driven by an SSTL Driver
2.5V
3.3V
3.3V CML with
Built-In Pullup
Zo = 50Ω
Zo = 50Ω
C1
C2
IN
50Ω
50Ω
VT
nIN
REF_AC
Receiver with
Built-In 50Ω
Figure 3E. HiPerClockS IN/nIN Input with Built-In 50Ω
Driven by a 3.3V CML Driver with
Built-In Pullup
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Recommendations for Unused Input Pins
Inputs:
OUTputs:
LVCMOS Select Pins
LVDS Outputs
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
EPAD Thermal Release Path
The EPAD provides heat transfer from the device to the P.C. board.
The exposed metal pad on the PCB is connected to the ground
plane through thermal vias. To guarantee the device’s electrical
and thermal performance, EPAD must be soldered to the exposed
metal pad on the PCB, as shown in Figure 4. For further
information, please refer to the Application Note on Surface Mount
Assembly of Amkor’s Thermally /Electrically Enhance Leadframe
Base Package, Amkor Technology.
SOLDER
SOLDER
PIN
PIN
EPAD
PIN PAD
GROUND PLANE
EXPOSED METAL PAD
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Board for Exposed Pad Thermal Release Path Example
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2.5V LVDS Driver Termination
Figure 5 shows a typical termination for LVDS driver in
characteristic impedance of 100Ω differential (50Ω single)
transmission line environment. For buffer with multiple LDVS driver,
it is recommended to terminate the unused outputs.
2.5V
50Ω
2.5V
LVDS Driver
+
–
R1
100Ω
50Ω
100Ω Differential Transmission Line
Figure 5. Typical LVDS Driver Termination
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS889872.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS889872 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
•
Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 80mA = 210mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.210W * 51.5°C/W = 95.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 16 Lead VFQFN, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
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Reliability Information
Table 7. θJA vs. Air Flow Table for a 16 Lead VFQFN
θJA by Velocity
Linear Feet per Minute
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
Transistor Count
The transistor count for ICS889872 is: 323
Pin compatible with SY89872U
Package Outline and Package Dimensions
Package Outline - K Suffix for 16 Lead VFQFN
(Ref.)
Seating Plane
N & N
(N -1)x e
(Ref.)
Even
A1
IndexArea
L
A3
E2
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
Singulation
1
2
(N -1)x e
OR
(Ref.)
E2
2
TopView
D
b
(Ref.)e
N & N
Odd
Thermal
Base
A
D2
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
Table 8. Package Dimensions
JEDEC Variation: VEED-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
0.80
0
1.00
0.05
A1
A3
0.25 Ref.
b
ND & NE
D & E
D2 & E2
e
0.18
0.30
4
3.00 Basic
1.00
0.30
1.80
0.50 Basic
L
0.50
Reference Document: JEDEC Publication 95, MO-220
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Ordering Information
Table 9. Ordering Information
Part/Order Number
ICS889872AK
ICS889872AKT
ICS889872AKLF
ICS889872AKLFT
Marking
872A
872A
TBD
Package
16 Lead VFQFN
16 Lead VFQFN
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
“Lead-Free” 16 Lead VFQFN
“Lead-Free” 16 Lead VFQFN
TBD
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
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Europe
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England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
www.IDT.com
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