ICS889874AK [ICSI]
DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER; 差分至LVPECL缓冲器/除法器型号: | ICS889874AK |
厂家: | INTEGRATED CIRCUIT SOLUTION INC |
描述: | DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER |
文件: | 总14页 (文件大小:162K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
GENERAL DESCRIPTION
FEATURES
The ICS889874 is a high speed 1:2 Differential- • 2 LVPECL outputs
ICS
to-LVPECL Buffer/Divider and is a member of
• Frequency divide select options: ÷ 1, ÷ 2, ÷4, ÷8, ÷16
HiPerClockS™
the HiPerClockS™family of high performance
clock solutions from ICS. The ICS889874 has
a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output divider,
• IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
which allows the device to be used as either a 1:2 fanout
buffer or frequency divider. The clock input has internal
termination resistors, allowing it to interface with several
differential signal types while minimizing the number of
required external components. The device is packaged in
a small, 3mm x 3mm VFQFN package, making it ideal for
use on space-constrained boards.
• Output frequency: > 2.5GHz
• Output skew: 5ps (typical)
• Part-to-part skew: TBD
• Additive jitter, RMS: <0.03ps (design target)
• Supply voltage range:(LVPECL), 2.375V to 3.465V
Supply voltage range: (ECL), -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
• Pin compatible with SY89874U
BLOCK DIAGRAM
PIN ASSIGNMENT
S2
16 15 14 13
Q0
IN
VT
1
2
3
4
12
nQ0
11
nRESET
Enable
Q1
VREF_AC
10
9
FF
nQ1
nIN
Q0
5
6
7
8
Enable
MUX
0
nQ0
1
Q1
IN
00 ÷2
01 ÷4
10 ÷8
nQ1
VT
ICS889874
16-LeadVFQFN
11 ÷16
nIN
S0
S1
3mm x 3mm x 0.95 package body
K Package
Decoder
Top View
VREF_AC
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
889874AK
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REV. A MAY 19, 2004
1
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
S2, S1, S0
nc
Type
Description
Output
Output
Input
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Select pins. LVCMOS/LVTTL interface levels.
No connect.
3, 4
5, 15, 16
6
Pullup
Pullup
Unused
Power
7, 14
VCC
Positive supply pins.
Synchronizing enable/disable pin. When LOW, resets the divider. When
HIGH, unconnected. Input threshold is VCC/2V. Includes a 37kΩ pull-up
resistor. LVTTL / LVCMOS interface levels.
8
nRESET
Input
9
nIN
VREF_AC
VT
Input
Output
Input
Inverting differential LVPECL clock input.
Reference voltage for AC-coupled applications.
Termination input.
10
11
12
13
IN
Input
Non-inverting LVPECL differential clock input.
Negative supply pin.
VEE
Power
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
RPULLUP
Input Pullup Resistor
37
KΩ
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REV. A MAY 19, 2004
2
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nRESET
Selected Source
IN, nIN
Q0, Q1
Disabled; LOW
Enabled
nQ0, nQ1
0
1
Disabled; HIGH
Enabled
IN, nIN
NOTE: After nRESET switches, the clock outputs are disabled or enabled following a
falling input clock edge as shown in Figure 1.
V
/2
CC
nRESET
t
RR
IN
V
IN
nIN
t
PD
nQ
Q
V
Swing
OUT
FIGURE 1. nRESET TIMING DIAGRAM (WHEN S2 = 1)
TABLE 3B. TRUTH TABLE
Inputs
Outputs
nRESET
S2
0
S1
X
0
S0
1
1
1
1
1
X
0
1
0
1
Reference Clock (pass through)
Reference Clock ÷2
1
1
0
Reference Clock ÷4
1
1
Reference Clock ÷8
1
1
Reference Clock ÷16
Q = LOW, nQ = HIGH
Clock Disable; (NOTE 1)
Q = LOW, nQ = HIGH
Clock Disable; (NOTE 1)
0
0
1
0
X
X
X
X
NOTE 1: Reset/Disable function is asserted on the next clock input
(IN/nIN) high-to-low transition.
889874AK
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REV. A MAY 19, 2004
3
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
-0.5V to +4.0V
Inputs, VI
-0.5V toVCC + 0.5 V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Input Current IN, nIN
VT Current, IVT
50mA
100mA
0.5mA
VREF_AC Sink/Source, IVREF_AC
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature, TSTG -65°C to 150°C
PackageThermal Impedance, θJA 51.5°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 10ꢀ OR 2.5V 5ꢀ; TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.63
V
50
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V 10ꢀ OR 2.5V 5ꢀ; TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
0
VCC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
Input Low Current
VCC = VIN = 3.63V
-125
20
µA
µA
IIL
VCC = 3.63V, VIN = 0V
-300
TABLE 4C. DC CHARACTERISTICS, VCC = 3.3V 10ꢀ OR 2.5V 5ꢀ; TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
RIN
Differential Input Resistance (IN, nIN)
100
Ω
VIH
Input High Voltage
Input Low Voltage
Input Voltage Swing
(IN, nIN)
(IN, nIN)
1.2
0
VCC
VCC - 0.15
2.8
V
V
VIL
VIN
0.15
0.3
V
VDIFF_IN
IIN
Differential Input Voltage Swing
V
Input Current
Bias Voltage
(IN, nIN)
45
mA
V
VREF_AC
VCC - 1.35
889874AK
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REV. A MAY 19, 2004
4
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 10ꢀ OR 2.5V 5ꢀ; TA = -40°C TO 85°C
Symbol Parameter Conditions Minimum
Typical
VCC - 1.005
VCC - 1.78
Maximum Units
VOH
VOL
Output High Voltage; NOTE 1
mV
mV
Output Low Voltage; NOTE 1
Output Voltage Swing
VOUT
800
mV
V
VDIFF_OUT Differential Output Voltage Swing
1.60
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 10ꢀ OR 2.5V 5ꢀ; TA = -40°C TO 85°C
Symbol Parameter
Maximum Output Frequency
Condition
Minimum Typical Maximum Units
Output Swing ≥ 450mV
÷ 2, ÷4, ÷8, ÷16
2
2
GHz
GHz
ps
fMAX
Maximum Input Frequency
Input Swing: < 400mV
Input Swing: ≥ 400mV
725
725
5
Propagation Delay, (Differential);
NOTE 1
tPD
ps
tsk(o)
Output Skew; NOTE 2, 4
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
TBD
ps
Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tjit
<0.03
ps
tRR
tR/tF
tS
Reset Recovery Time
TBD
180
ps
ps
ps
ps
Output Rise/Fall Time
20ꢀ to 80ꢀ
Clock Enable Setup Time EN to IN, nIN
TBD
TBD
tH
Clock Enable Hold Time
EN to IN, nIN
All parameters characterized at ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
889874AK
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REV. A MAY 19, 2004
5
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nIN
LVPECL
VIN
VIH
Cross Points
IN
nQx
VEE
VIL
VEE
-0.375V to -1.63V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nIN
IN
80ꢀ
tF
80ꢀ
VSWING
20ꢀ
Clock
20ꢀ
nQ0, nQ1
Outputs
tR
Q0, Q1
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nIN
IN
VIN, VOUT
VDIFF_IN, VDIFF_OUT
800mV
(typical)
1600mV
(typical)
tHOLD
nRESET
tSET-UP
SETUP & HOLD TIME
SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING
889874AK
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REV. A MAY 19, 2004
6
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
APPLICATION INFORMATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Z
o = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
889874AK
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REV. A MAY 19, 2004
7
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V ground level. The R3 in Figure 3B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 3C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
R3
+
-
250
250
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A MAY 19, 2004
8
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
2.5V LVPECL INPUT WITH BUILT-IN 50Ω TERMINATIONS INTERFACE
The IN /nIN with built-in 50Ω terminations accepts LVDS,
LVPECL, LVHSTL, CML, SSTL and other differential signals.
Both VSWING and VOH must meet the VPP and VCMR input
requirements.Figures 4A to 4D show interface examples for the
by the most common driver types. The input interfaces sug-
gested here are examples only.If the driver is from another ven-
dor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termi-
HiPerClockS IN/nIN input with built-in 50Ω terminations driven nation requirements.
2.5V
2.5V
3.3V or 2.5V
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
nIN
VT
nIN
Receiver
With
Receiver
With
Built-In
50 Ohm
2.5V LVPECL
LVDS
R1
18
Built-In
50 Ohm
FIGURE 4A. HIPERCLOCKS IN/nIN INPUT WITH
FIGURE 4B. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER
BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER
2.5V
2.5V
2.5V
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
VT
Zo = 50 Ohm
Zo = 50 Ohm
nIN
nIN
Receiver
Receiver
With
With
CML - Built-in 50 Ohm Pull-up
CML - Open Collector
Built-In
Built-In
50 Ohm
50 Ohm
FIGURE 4C. HIPERCLOCKS IN/nIN INPUT WITH
FIGURE 4D. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN OPEN COLLECTOR
CML DRIVER
BUILT-IN 50Ω DRIVEN BY A CML DRIVER
WITH BUILT-IN 50Ω PULLUP
2.5V
2.5V
Zo = 50 Ohm
R1
25
25
IN
VT
Zo = 50 Ohm
nIN
R2
Receiver With Built-In 50Ω
SSTL
FIGURE 4E. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN SSTL DRIVER
889874AK
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REV. A MAY 19, 2004
9
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
3.3V LVPECL INPUT WITH BUILT-IN 50Ω TERMINATIONS INTERFACE
The IN /nIN with built-in 50Ω terminations accepts LVDS,
LVPECL, LVHSTL, CML, SSTL and other differential signals.
Both VSWING and VOH must meet the VPP and VCMR input require-
ments. Figures 5A to 5E show interface examples for the
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another ven-
dor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termi-
HiPerClockS IN/nIN input with built-in 50Ω terminations driven nation requirements.
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
nIN
VT
nIN
Receiver
With
Receiver
With
Built-In
50 Ohm
LVPECL
LVDS
R1
50
Built-In
50 Ohm
FIGURE 5A. HIPERCLOCKS IN/nIN INPUT WITH
FIGURE 5B. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER
BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
VT
Zo = 50 Ohm
Zo = 50 Ohm
nIN
nIN
Receiver
Receiver
With
With
CML- Open Collector
CML- Built-in 50 Ohm Pull-Up
Built-In
Built-In
50 Ohm
50 Ohm
FIGURE 5D. HIPERCLOCKS IN/nIN INPUT WITH
F
IGURE 5C. H
IP
ER
CLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY A CML DRIVER
WITH BUILT-IN 50Ω PULLUP
B
WITH
UILT
-
IN 50Ω DRIVEN BY A CML DRIVER
O
PEN
COLLECTOR
3.3V
3.3V
R1
25
Zo = 50 Ohm
Zo = 50 Ohm
IN
VT
nIN
Receiver
With
SSTL
R2
25
Built-In
50 Ohm
FIGURE 5E. HIPER
CLOCKS IN/nIN INPUT WITH
BUILT
-
IN 50Ω DRIVEN BY AN SSTL DRIVER
889874AK
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REV. A MAY 19, 2004
10
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
3.3V DIFFERENTIAL
To prevent oscillation and to reduce noise, it is recommended to
have pullup and pulldown connect to true and compliment of the
unused input as shown in Figure 6.
I
NPUT WITH
B
UILT-I
N
50Ω TERMINATION
U
NUSED
INPUT
H
ANDLING
3.3V
3.3V
R1
1K
IN
VT
nIN
Receiver
with
R2
1K
Built-In
50 Ohm
FIGURE 6. UNUSED INPUT HANDLING
2.5V DIFFERENTIAL
To prevent oscillation and to reduce noise, it is recommended to
have pullup and pulldown connect to true and compliment of the
unused input as shown in Figure 7.
I
NPUT WITH
B
UILT-I
N
50Ω TERMINATION
U
NUSED
INPUT
H
ANDLING
2.5V
2.5V
R1
680
IN
VT
nIN
Receiver
with
R2
680
Built-In
50 Ohm
FIGURE 7. UNUSED INPUT HANDLING
889874AK
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REV. A MAY 19, 2004
11
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
θJA 0 Air Flow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
TRANSISTOR COUNT
The transistor count for ICS889874 is: 326
889874AK
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REV. A MAY 19, 2004
12
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
16
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
4
4
3.0
D2
E
0.25
1.25
3.0
E2
L
0.25
0.30
1.25
0.50
Reference Document: JEDEC Publication 95, MO-220
889874AK
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REV. A MAY 19, 2004
13
PRELIMINARY
ICS889874
1:2
TO-LVPECL BUFFER/DIVIDER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL
-
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS889874AK
Marking
Package
Count
120 per tube
3500
Temperature
-40°C to 85°C
-40°C to 85°C
874A
874A
16 Lead VFQFN
ICS889874AKT
16 Lead VFQFN on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
889874AK
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REV. A MAY 19, 2004
14
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IDT
ICS8M3001AJT
Low Skew Clock Driver, 1 True Output(s), 0 Inverted Output(s), CDSO6, 5 X 7 MM, 1.50 MM, CERAMIC, HERMETIC-6
IDT
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