ICS889875AKLFT [IDT]
Low Skew Clock Driver, 889875 Series, 2 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-16;
| 型号： | ICS889875AKLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 889875 Series, 2 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-16 驱动 逻辑集成电路 |
| 文件： | 总16页 (文件大小：657K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER
W/INTERNAL TERMINATION
ICS889875
General Description
Features
The ICS889875 is a high speed Differential-to-
• Two LVDS outputs
S
IC
LVDS Buffer/Divider w/Internal Termination and is a
member of the HiPerClockS™ family of high
performance clock solutions from IDT. The
ICS889875 has a selectable ÷1, ÷2, ÷4, ÷8, ÷16
• Frequency divide select options: ÷1, ÷2, ÷4, ÷8, ÷16
HiPerClockS™
• IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
• Output frequency: >2GHz
output dividers. The clock input has internal termination resistors,
allowing it to interface with several differential signal types while
minimizing the number of required external components. The
device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
• Cycle-to-cycle jitter: 1ps RMS (maximum)
• Total jitter: 10ps (typical)
• Output skew: 15ps (maximum)
• Part-to-part skew: 280ps (maximum)
• Propagation Delay: 1140ps (maximum)
• Full 2.5V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
Pullup
S2
16 15 14 13
1
2
3
Q0
nQ0
Q1
12
11
10
IN
nRESET/
nDISABLE
VT
Enable
FF
Pullup
VREF_AC
nIN
nQ1
4
9
5
6
7
8
Enable
MUX
VREF_AC
Q0
nQ0
MUX
ICS889875
IN
VT
Q1
50Ω
50Ω
÷2, ÷4,
÷8, ÷16
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
nQ1
nIN
K Package
Top View
Pullup
Pullup
S1
S0
Decoder
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Table 1. Pin Descriptions
Number
Name
Type
Description
Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused outputs must be
terminated with 100Ω across the differential pair.
LVDS interface levels.
1, 2
Q0, nQ0
Output
Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused outputs must be
terminated with 100Ω across the differential pair.
LVDS interface levels.
3, 4
Q1, nQ1
Output
Input
Select pins. Internal 37kΩ pullup resistor. Logic HIGH if left disconnected.
Input threshold is VDD/2. LVCMOS/LVTTL interface levels.
5, 15, 16
S2, S1, S0
Pullup
6
nc
Unused
Power
No connect.
7, 14
VDD
Power supply pins.
Synchronizing enable/disable pin. When LOW, resets the divider (divided by
1, 2, 4, 8 or 16 mode). When HIGH, disconnected. The reset and disable
function occurs on the next high-to-low clock input transition.
Input threshold is VDD/2V. Includes a 37kΩ pull-up resistor.
LVTTL / LVCMOS interface levels.
nRESET/
nDISABLE
8
Input
Pullup
9
nIN
VREF_AC
VT
Input
Output
Input
Inverting differential LVPECL clock input. RT = 50Ω termination to VT.
Reference voltage for AC-coupled applications. Equal to VDD – 1.4V
(approx.). Maximum sink/source current is 0.5mA.
10
11
12
13
Termination center-tap input.
Non-inverting LVPECL differential clock input.
RT = 50Ω termination to VT.
IN
Input
GND
Power
Power supply ground.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
RPULLUP
Input Pullup Resistor
37
kΩ
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Function Tables
Table 3A. Control Input Function Table
Input
Outputs
nRESET
Q0, Q1
Disabled; LOW
Enabled
nQ0, nQ1
Disabled; HIGH
Enabled
0
1
NOTE: After nRESET switches, the clock outputs are disabled or
enabled following a falling input clock edge as shown in Figure 1.
Figure 1. nRESET Timing Diagram
V
/2
DD
nRESET
t
RR
nIN
IN
V
Swing
IN
t
PD
nQx
Qx
V
Swing
OUT
Table 3B. Truth Table
Inputs
Outputs
Q0/nQ0, Q1/nQ1
nRESET/nDISABLE
S2
0
S1
X
0
S0
X
0
1
Reference Clock (pass through)
Reference Clock ÷2
1
1
1
1
0
1
Reference Clock ÷4
1
1
1
0
Reference Clock ÷8
1
1
1
1
Reference Clock ÷16
0 (NOTE 1)
X
X
X
Qx = LOW, nQx = HIGH; Clock disabled
NOTE 1: Reset/disable function is asserted on the next clock input (IN/nIN) high-to-low transition.
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Input Current, IN, nIN
50mA
VT Current, IVT
100mA
Input Sink/Source, IREF_AC
0.5mA
Operating Temperature Range, TA
Package Thermal Impedance, θJA, (Junction-to-Ambient)
Storage Temperature, TSTG
-40°C to +85°C
88.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
VDD Positive Supply Voltage
IDD Power Supply Current
Test Conditions
Minimum
Typical
Maximum
2.625
82
Units
V
2.375
2.5
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol
VIH
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
2
0
VDD + 0.3
VIL
0.8
5
V
IIH
VDD = VIN = 2.625V
µA
µA
IIL
VDD = 2.625V, VIN = 0V
-150
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Table 4C. Differential DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol
RIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Ω
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
Differential Input Voltage Swing
Input Current
(IN, nIN)
(IN, nIN)
(IN, nIN)
100
VIH
1.2
0
VDD + 0.05
VDD – 0.15
2.8
V
VIL
V
VIN
0.15
0.3
V
VDIFF_IN
IIN
V
(IN, nIN)
45
mA
V
VREF_AC
Bias Voltage
VDD – 1.35
Table 4D. LVDS DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
350
Maximum
Units
400
VOUT
Output Voltage Swing
250
mV
VOH
Output High Voltage
1.475
V
V
VOL
Output Low Voltage
0.925
VCCM
∆VOCM
Output Common Mode Voltage
Change in Common Mode Voltage
1.35
V
50
mV
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Parameter
Symbol
Test Conditions
÷1, ÷2, ÷4
Minimum
Typical
>2
Maximum
Units
GHz
GHz
fMAX
Maximum Input Frequency
÷8, ÷16
>1.5
Propagation Delay;
NOTE 1
tPD
IN-to-Q
690
1140
ps
tsk(o)
tsk(pp)
tjit(cc)
tjit(j)
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Cycle-to-Cycle Jitter, RMS; NOTE 5
Total Jitter
15
280
1
ps
ps
ps
ps
ps
ps
10
tRR
Reset Recovery Time
Output Rise/Fall Time
600
70
tR / tF
260
All parameters characterized at fMAX unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
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Parameter Measurement Information
V
DD
SCOPE
nIN
IN
Qx
V
DD
2.5V 5%
POWER SUPPLY
VPP
VCMR
Cross Points
+
Float GND –
LVDS
nQx
GND
LVDS Output Load AC Test Circuit
Differential Input Level
Part 1
nQx
nQx
Qx
Qx
Part 2
nQy
nQy
Qy
Qy
tsk(o)
tsk(pp)
Part-to-Part Skew
Output Skew
nQ0,nQ1
Q0,Q1
nIN
IN
➤
➤
tcycle n
tcycle n+1
➤
➤
nQ0,nQ1
tjit(cc) = tcycle n – tcycle n+1
|
|
1000 Cycles
Q0,Q1
tPD
Cycle-to-Cycle Jitter, RMS
Propagation Delay
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Parameter Measurement Information, continued
nQ0,nQ1
80%
tF
80%
tR
VDIFF_IN, VDIFF_OUT
VOD
VOS
700mV
(typical)
VIN, VOUT
20%
20%
350mV
(typical)
Q0,Q1
Single-Ended & Differential Input Voltage Swing
Output Rise/Fall Time
VDD
VDD
out
➤
out
out
➤
DC Input
LVDS
LVDS
V
OD/∆ VOD
DC Input
100
out
➤
VOS/∆ VOS
➤
Differential Output Voltage Setup
Offset Voltage Setup
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Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
VDD
R1
1K
Single Ended Clock Input
R2/R1 = 0.609.
IN
V_REF
nIN
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
Recommendations for Unused Input Pins
Inputs:
OUTputs:
LVCMOS Select Pins
LVDS Outputs
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
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2.5V LVPECL Input with Built-In 50Ω Termination Interface
The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL,
CML, SSTL and other differential signals. Both signals must meet
the VPP and VCMR input requirements. Figures 3A to 3E show
interface examples for the HiPerClockS IN /nIN with built-in 50Ω
termination input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm
the driver termination requirements.
2.5V
2.5V
2.5V
3.3V or 2.5V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
IN
IN
VT
nIN
VT
nIN
Receiver
With
Receiver
With
LVPECL
LVDS
R1
18
Built-In
50Ω
Built-In
50Ω
Figure 3A. HiPerClockS IN/nIN Input with Built-In 50Ω
Figure 3B. HiPerClockS IN/nIN Input with Built-In 50Ω
Driven by an LVDS Driver
Driven by an LVPECL Driver
2.5V
2.5V
2.5V
2.5V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
IN
IN
VT
nIN
VT
nIN
Receiver
With
Receiver
With
CML - Built-in 50Ω Pull-up
CML
Built-In
50Ω
Built-In
50Ω
Figure 3C. HiPerClockS IN/nIN Input with Built-In 50Ω
Figure 3D. HiPerClockS IN/nIN Input with Built-In 50Ω
Driven by a CML Driver with Built-In 50Ω
Pullup
Driven by a CML Driver
2.5V
2.5V
Zo = 50Ω
Zo = 50Ω
R1
R2
25
25
IN
VT
nIN
Receiver
With
SSTL
Built-In
50Ω
Figure 3E. HiPerClockS IN/nIN Input with Built-In 50Ω
Driven by an SSTL Driver
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VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal and
electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as many
vias connected to ground as possible. It is also recommended that
the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz
copper via barrel plating. This is desirable to avoid any solder
wicking inside the via during the soldering process which may
result in voids in solder between the exposed pad/slug and the
thermal land. Precautions should be taken to eliminate any solder
voids between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only. For
further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadfame Base Package, Amkor Technology.
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias. The
vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
2.5V LVDS Driver Termination
Figure 5 shows a typical termination for LVDS driver in
characteristic impedance of 100Ω differential (50Ω single)
transmission line environment. For buffer with multiple LDVS driver,
it is recommended to terminate the unused outputs.
2.5V
50Ω
2.5V
LVDS Driver
+
–
R1
100Ω
50Ω
100Ω Differential Transmission Line
Figure 5. Typical LVDS Driver Termination
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Schematic Example
Figure 6 shows a schematic example of the ICS889875. This
schematic provides examples of input and output handling. The
ICS889875 input has built-in 50Ω termination resistors. The input
can directly accept various types of differential signals without AC
coupling. For AC coupling termination, the ICS889875 also
provides the VREF_AC pin for proper offset bias. This example
shows the ICS889875 input driven by a 2.5V LVPECL driver. The
ICS889875 outputs are LVDS drivers. In this example, we assume
the traces are long transmission lines and the receivers of the
LVDS drivers have high input impedance without built-in
termination.
2.5V
2.5V
C2
Zo = 50
0.1u
-
R3
Zo = 50
100
+
2.5V
LVPECL
Zo = 50
Q0
9
10
11
12
4
3
2
1
100 Ohm Differential
nIN
nQ1
Q1
nQ0
nQ1
Q1
VREF_AC
VT
IN
nQ0
Q0
Zo = 50
2.5V
100 Ohm Differential
Zo = 50
R1
150
R2
U1
150
-
ICS889875
2.5V
R4
100
Zo = 50
+
C1
0.1u
100 Ohm Differential
Figure 6. ICS889875 Schematic Example
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS889875.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS889875 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
•
Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 82mA = 215.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.215W * 88.5°C/W = 104°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 16 Lead VFQFN, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
88.5°C/W
77.3°C/W
69.4°C/W
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Reliability Information
Table 7. θJA vs. Air Flow Table for a 16 Lead VFQFN
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
88.5°C/W
77.3°C/W
69.4°C/W
Transistor Count
The transistor count for ICS889875 is: 328
Pin compatible with SY89875U
Package Outline and Package Dimensions
Package Outline - K Suffix for 16 Lead VFQFN
(Ref.)
Seating Plane
ND& NE
Even
(ND-1)x e
(R ef.)
A1
Index Area
L
A3
E2
e
2
N
N
(Typ.)
If ND & NE
are Even
Anvil
1
Singulation
2
(NE -1)x e
OR
(Re f.)
E2
2
Top View
D
b
e
Thermal
Base
A
(Ref.)
ND &NE
Odd
D2
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
Table 8. Package Dimensions
JEDEC Variation: VEED-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
0.80
0
1.00
0.05
A1
A3
0.25 Ref.
b
ND & NE
D & E
D2 & E2
e
0.18
0.30
4
3.00 Basic
1.00
0.30
1.80
0.50 Basic
L
0.50
Reference Document: JEDEC Publication 95, MO-220
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Ordering Information
Table 9. Ordering Information
Part/Order Number
889875AK
889875AKT
889875AKLF
889875AKLFT
Marking
875A
875A
75AL
75AL
Package
16 Lead VFQFN
16 Lead VFQFN
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
“Lead-Free” 16 Lead VFQFN
“Lead-Free” 16 Lead VFQFN
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
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DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
Revision History Sheet
Rev
Table
Page
Description of Change
Date
7/1/08
7/3/08
T4C
5
Differential DC Characteristics Table - corrected typo for VIH max. from VDD – 0.05V
to VDD + 0.05V.
B
B
T1
2
Pin Description Table - deleted “Leave pin floating.” from VT pin description.
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
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ICS889875AK REV. B OCTOBER 27, 2008
ICS889875
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
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United States
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www.IDT.com/go/contactIDT
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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Printed in USA
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