ICS853S012AKI [IDT]
Low Skew Clock Driver, 853S Series, 1 True Output(s), 0 Inverted Output(s), 5 MM X 5 MM, 0.75 MM HEIGHT, MO-220VHHD-2, VFQFN-32;
| 型号： | ICS853S012AKI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 853S Series, 1 True Output(s), 0 Inverted Output(s), 5 MM X 5 MM, 0.75 MM HEIGHT, MO-220VHHD-2, VFQFN-32 |
| 文件： | 总17页 (文件大小：2291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
12:1, DIFFERENTIAL-TO-3.3V, 2.5V
LVPECL CLOCK/DATA MULTIPLEXER
ICS853S012I
GENERAL DESCRIPTION
FEATURES
The ICS853S012I is an 12:1 Differential-to-3.3V
• High speed 12:1 differential multiplexer
ICS
HiPerClockS™
or 2.5V LVPECL Clock/Data Multiplexer which can
operate up to 3.2GHz and is a member of the
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS853S012I has 12 dif-
• One differential 3.3V or 2.5V LVPECL output
• Twelve selectable differential clock or data inputs
• CLKx, nCLKx pairs can accept the following differential input
levels: LVPECL, LVDS, CML, SSTL
ferential selectable clock inputs. The CLK, nCLK input pairs
can accept LVPECL, LVDS, CML or SSTL levels. The fully dif-
ferential architecture and low propagation delay make it ideal
for use in clock distribution circuits. The select pins have inter-
nal pulldown resistors.
• Maximum output frequency: 3.2GHz (typical)
• Translates any single ended input signal to LVPECL levels with
resistor bias on nCLKx input
• Additive phase jitter, RMS: 0.13ps (typical)
• Part-to-part skew: TBD
• Propagation delay: 685ps (typical)
• Full 3.3V or 2.5V operating supply modes
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Pulldown
CLK0
Pullup/Pulldown
nCLK0
Pulldown
Pullup/Pulldown
CLK1
nCLK1
32 31 30 29 28 27 26 25
CLK2
24
23
22
21
20
19
18
17
CLK9
nCLK9
SEL0
1
2
3
4
5
6
7
8
Pulldown
Pullup/Pulldown
CLK2
nCLK2
nCLK2
VCC
Q
ICS853S012I
32-Lead VFQFN
5mm x 5mm x 0.75mm
package body
SEL1
SEL2
SEL3
Q
nQ
nQ
VEE
K Package
Top View
CLK3
CLK8
nCLK3
nCLK8
9
10 11 12 13 14 15 16
Pulldown
Pullup/Pulldown
CLK11
nCLK11
SEL[3:0]
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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12:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK/DATA MULTIPLEXER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
1
CLK2
Input
Input
Non-inverting differential clock input.
Inverting differential clock input.
VCC/2 default when left floating.
2
3
nCLK2
VCC
Pullup/Pulldown
Power
Output
Positive supply pin.
4, 5
Q, nQ
Differential output pair. LVPECL interface levels.
6
7
8
VEE
Power
Input
Input
Negative supply pin.
CLK3
nCLK3
Pulldown
Non-inverting differential clock input.
Inverting differential clock input.
VCC/2 default when left floating.
Pullup/Pulldown
Inverting differential clock input.
VCC/2 default when left floating.
9
nCLK4
CLK4
nCLK5
CLK5
CLK6
Input
Input
Input
Input
Input
Pullup/Pulldown
Pulldown
10
11
12
13
Non-inverting differential clock input.
Inverting differential clock input.
VCC/2 default when left floating.
Pullup/Pulldown
Pulldown
Non-inverting differential clock input.
Non-inverting differential clock input.
Pulldown
Inverting differential clock input.
VCC/2 default when left floating.
14
15
16
nCLK6
CLK7
Input
Input
Input
Pullup/Pulldown
Pulldown
Non-inverting differential clock input.
Inverting differential clock input.
VCC/2 default when left floating.
nCLK7
Pullup/Pulldown
Inverting differential clock input.
VCC/2 default when left floating.
17
18
nCLK8
CLK8
Input
Pullup/Pulldown
Input
Input
Pulldown
Pulldown
Non-inverting differential clock input.
19, 20
21, 22
SEL3, SEL2,
SEL1, SEL0
Clock select input pins. LVCMOS/LVTTL interface levels.
Inverting differential clock input.
VCC/2 default when left floating.
23
24
25
26
27
nCLK9
CLK9
Input
Input
Input
Input
Input
Pullup/Pulldown
Pulldown
Non-inverting differential clock input.
Inverting differential clock input.
VCC/2 default when left floating.
nCLK10
CLK10
nCLK11
Pullup/Pulldown
Pulldown
Non-inverting differential clock input.
Inverting differential clock input.
VCC/2 default when left floating.
Pullup/Pulldown
28
29
CLK11
CLK0
Input
Input
Pulldown
Pulldown
Non-inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
VCC/2 default when left floating.
30
31
32
nCLK0
CLK1
Input
Input
Input
Pullup/Pulldown
Pulldown
Non-inverting differential clock input.
Inverting differential clock input.
VCC/2 default when left floating.
nCLK1
Pullup/Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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12:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK/DATA MULTIPLEXER
PRELIMINARY
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
RPULLDOWN Pulldown Resistor
50
50
kΩ
kΩ
RVCC/2
Pullup/Pulldown Resistor
TABLE 3. CONTROL INPUT FUNCTION TABLE
Control Inputs
Outputs
Q nQ
SEL3
SEL2
SEL1
SEL0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
L
nCLK0
nCLK1
nCLK2
nCLK3
nCLK4
nCLK5
nCLK6
nCLK7
nCLK8
nCLK9
nCLK10
nCLK11
H
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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12:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK/DATA MULTIPLEXER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Func-
tional operation of product at these conditions or any con-
ditions beyond those listed in the DC Characteristics
or AC Characteristics is not implied. Exposure to abso-
lute maximum rating conditions for extended periods may
affect product reliability.
Supply Voltage, V
4.6V
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
For 32 Lead VFQFN
JA
34.8°C/W (0 lfpm)
-65°C to 150°C
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.135
3.465
V
70
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
2.5
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
2.625
V
65
mA
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ OR 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
VCC = VIN = 3.465V,
VCC = VIN = 2.625V
CC = 3.465V, VIN = 0V,
IIH
IIL
Input High Current SEL0:SEL3
150
µA
µA
V
Input Low Current SEL0:SEL3
-150
VCC = 2.625V, VIN = 0V
TABLE 4D. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ OR 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VCC = VIN = 3.465V or
2.625V
Minimum
Typical
Maximum Units
CLK0:CLK11
nCLK0:nCLK11
150
µA
µA
VCC = 3.465V or 2.625V,
VIN = 0V
CLK0:CLK11
-10
IIL
Input Low Current
VCC = 3.465V or 2.625V,
VIN = 0V
nCLK0:nCLK11
-150
µA
VPP
Peak-to-Peak Input Voltage
0.15
1.2
1.5
VCC
V
V
Common Mode Input Voltage;
NOTE 1, 2
VCMR
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V.
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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12:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK/DATA MULTIPLEXER
PRELIMINARY
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ OR 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VCC - 1.125
VCC - 1.895
0.6
Typical
Maximum Units
VOH
Output High Voltage Voltage; NOTE 1
VCC - 0.935
VCC - 1.670
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
3.2
GHz
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
155.52MHz,
12kHz - 20MHz
tjit
0.13
ps
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Input Skew
685
TBD
35
ps
ps
ps
ps
tsk(pp)
tsk(i)
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
135
155.52MHz,
Input Peak-to-Peak = 800mV
MUX_ISOLATION Mux Isolation
60
dB
All parameters measured up to 1.3GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
3.2
GHz
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
155.52MHz,
12kHz - 20MHz
tjit
0.14
ps
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Input Skew
690
TBD
55
ps
ps
ps
ps
tsk(pp)
tsk(i)
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
125
155.52MHz,
Input Peak-to-Peak = 800mV
MUX_ISOLATION Mux Isolation
60
dB
All parameters measured up to 1.3GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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12:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK/DATA MULTIPLEXER
PRELIMINARY
ADDITIVE PHASE JITTER
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications.Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
Additive Phase Jitter @ 155.52MHz
(12kHz to 20MHz) = 0.13ps typical
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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12:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK/DATA MULTIPLEXER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
2V
SCOPE
SCOPE
VCC
VCC
Qx
Qx
LVPECL
LVPECL
nQx
nQx
VEE
VEE
-0.5V 0.125V
-1.3V 0.165V
OUTPUT LOAD 3.3V AC TEST CIRCUIT
OUTPUT LOAD 2.5V AC TEST CIRCUIT
VCC
nQx
PART 1
Qx
nCLK0:11
nQy
PART 2
Qy
VPP
VCMR
Cross Points
CLK0:11
VEE
tsk(pp)
PART-TO-PART SKEW
DIFFERENTIAL INPUT LEVEL
nCLK0:11
CLK0:11
nQ
nCLK0
CLK0
nLK1
Q
tPD
CLK1
PROPAGATION DELAY
nQ
Q
tPD2
80ꢀ
tF
80ꢀ
tPD1
VOD
tsk(i)
Clock
20ꢀ
20ꢀ
Outputs
tsk(i) = |tPD1 - tPD2
|
tR
INPUT SKEW
OUTPUT RISE/FALL TIME
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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12:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK/DATA MULTIPLEXER
PRELIMINARY
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
generated by the bias resistors R1, R2 and C1. This bias CcCircuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
CC
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK/nCLK INPUT:
LVPECL OUTPUT
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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12:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK/DATA MULTIPLEXER
PRELIMINARY
DIFFERENTIAL CLOCK INPUT INTERFACE
driver types. The input interfaces suggested here are examples
only. If the driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the driver
component to confirm the driver termination requirements.
The CLK /nCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and VCMR
input requirements. Figures 2A to 2F show interface examples
for the HiPerClockS CLK/nCLK input driven by the most common
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
R1
50
R2
50
CML
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Zo = 50 Ohm
HiPerClockS
nCLK
HiPerClockS
CML Built-In Pull-Up
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
A BUILT-IN PULLUP CML DRIVER
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
AN IDT OPEN COLLECTOR CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
R3
84
R4
84
Zo = 50 Ohm
Zo = 50 Ohm
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
nCLK
nCLK
HiPerClockS
HiPerClockS
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
A 3.3V LVDS DRIVER WITH AC COUPLE
2.5V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
Zo = 50 Ohm
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CLK
CLK
R1
100
nCLK
HiPerClockS
nCLK
Zo = 50 Ohm
HiPerClockS
CML Built-In Pull-Up
R1
120
R2
120
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
AN SSTL DRIVER
FIGURE 2F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVERER
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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PRELIMINARY
THERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to
the P.C. board. The expose metal pad is ground pad connected
to ground plane through thermal via. The exposed pad on the
device to the exposed metal pad on the PCB is contacted through
solder as shown in Figure 3 For further information, please refer
to the Application Note on Surface Mount Assembly of Amkor’s
Thermally /Electrically Enhance Leadframe Base Package, Amkor
Technology.
EXPOSED PAD
SOLDER
SOLDER MASK
SIGNAL
TRACE
SIGNAL
TRACE
GROUND PLANE
Expose Metal Pad
(GROUND PAD)
THERMAL VIA
FIGURE 3. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are rec-
ommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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PRELIMINARY
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to V - 2V. For V = 2.5V, the V - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination
is shown in Figure 5C.
CC
CC
CC
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
R1
250
R3
250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
-
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS83S012I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS83S012I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 70mA = 242.6mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30.94mW/Loaded Output pair
MAX
Total Power
(3.465V, with all outputs switching) = 242.6mW + 30.94mW = 273.5mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no
air flow and a multi-layer board, the appropriate value is 34.8°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.274W * 34.8°C/W = 94.5°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 32 LEAD VFQFN, FORCED CONVECTION
JA
θ vs. Air Flow (Linear Feet per Minute)
JA
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8°C/W
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, V = V
= V
– 0.935V
CCO_MAX
OUT
OH_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, V = V
= V
– 1.67V
CCO_MAX
OUT
OL_MAX
)
(V
- V
= 1.67V
CCO_MAX
OL_MAX
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
L
L
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
OH_MAX
CCO _MAX
OH_MAX
CCO
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
) = [(2V - (V
/R ] * (V
- V
) =
L
L
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
CCO
OL_MAX
CCO_MAX
OL_MAX
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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2
2
Pd_in_H = [(V – (V - 2V)] /R = [(V - 1V) - (V - 2V)] /R = (1V) /50Ω = 20.0mW
L
L
OH
CC
CC
CC
ICS853S012I
12:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK/DATA MULTIPLEXER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 32 LEAD VFQFN
JA
θ vs. Air Flow (Linear Feet per Minute)
JA
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8°C/W
TRANSISTOR COUNT
The transistor count for ICS853S012I is: 8,537
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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PRELIMINARY
PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
VHHD-2
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
0.80
0
1.00
0.05
A1
A3
b
--
0.25 Ref.
0.25
0.18
0.30
8
ND
NE
D
8
5.00 BASIC
2.25
D2
E
1.25
1.25
0.30
3.25
3.25
0.50
5.00 BASIC
2.25
E2
e
0.50 BASIC
0.40
L
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS853S012AKI
Marking
TBD
Package
Shipping Packaging
Tray
Temperature
32 Lead VFQFN
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS853S012AKIT
ICS853S012AKILF
ICS853S012AKILFT
TBD
32 Lead VFQFN
1000 Tape & Reel
Tray
TBD
32 Lead "Lead-Free" VFQFN
32 Lead "Lead-Free" VFQFN
TBD
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVPECL CLOCK/DATAMULTIPLEXER
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12:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK/DATA MULTIPLEXER
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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