ICS853S024_技术文档

PRELIMINARY

LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V

LVPECL FANOUT BUFFER

ICS853S024

General Description

Features

The ICS853S024 is a low skew, 1-to-24

• Twenty four LVPECL outputs.

• One differential clock input pair

S

IC

Differential-to-3.3V, 2.5V LVPECL Fanout Buffer and

a member of theHiPerClockS™ family of High

Performance Clock Solutions from IDT. The CLK,

nCLK pair can accept most standard differential

HiPerClockS™

• Differential input clock (CLK, nCLK) can accept the following

signaling levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

• Maximum output frequency: >1.5GHz

input levels. The ICS853S024 is characterized to operate from

either a 3.3V or a 2.5V power supply. Guaranteed output skew

characteristics make the ICS853S024 ideal for those clock

distribution applications demanding well defined performance and

repeatability.

• Translates any single ended input signal to 3.3V/ 2.5V LVPECL

levels with resistor bias on nCLK input

• Output skew: 25ps (typical)

• t_R/ t_F: 180ps (typical)

• Additive phase jitter, RMS: 0.111ps (typical) @ 312.5MHz

• Full 3.3V or 2.5V supply voltage

• 0°C to 70°C ambient operating temperature

• Available in lead-free (RoHS 6) packages.

.

Block Diagram

Pin Assignment

24

Pulldown

Pullup

Q0:Q23

CLK

24

nCLK

nQ0:nQ23

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

V_CC

V_EE

1

2

3

4

5

nCLK

CLK

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

nQ17

Q17

nQ16

Q16

nQ15

Q15

Q0

nQ0

Q1

ICS853S024

64-Lead TQFP, EPad

10mm x 10mm x 1mm

package body

Y Package

nQ1

Q2

6

7

nQ2

Q3

nQ3

8

9

nQ14

Q14

10

Q4 11

Top View

nQ13

Q13

12

13

14

nQ4

Q5

nQ5

V_EE

V_CC

nQ12

Q12

15

16

V_CC

17 18 19 20 21

23 24 25 26 27 28 29 30 31 32

22

The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.

Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

LOW SKEW LVPECL FANOUT BUFFER

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LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER

PRELIMINARY

Table 1. Pin Descriptions

Number

Name

Type

Description

1, 16, 18, 31, 33,

34, 50, 63, 64

V_CC

Power

Power supply pins.

2, 15, 17, 32, 49

3, 4

V_EE

Power

Output

Input

Negative supply pins.

Q0, nQ0

Q1, nQ1

Q2, nQ2

Q3, nQ3

Q4, nQ4

Q5, nQ5

Q6, nQ6

Q7, nQ7

Q8, nQ8

Q9, nQ9

Q10, nQ10

Q11, nQ11

Q12, nQ12

Q13, nQ13

Q14, nQ14

Q15, nQ15

Q16, nQ16

Q17, nQ17

CLK

Differential clock outputs. LVPECL interface levels.

5, 6

7, 8

9, 10

11, 12

13, 14

19, 20

21, 22

23, 24

25, 26

27, 28

29, 30

35, 36

37, 38

39, 40

41, 42

43, 44

45, 46

47

Pulldown Non-inverting differential clock input.

Pullup/

48

nCLK

Input

Inverting differential clock input. V_CC/2 default when left floating.

Pulldown

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

pF

Input Capacitance

Input Pullup Resistor

4

R_PULLUP

50

kΩ

R_PULLDOWNInput Pulldown Resistor

kΩ

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PRELIMINARY

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_CC

Inputs, V_I

4.6V

-0.5V to V_CC+ 0.5V

Outputs, I_O(LVPECL)

Continuous Current

Surge Current

50mA

100mA

Package Thermal Impedance, θ_JA

32.5°C/W (0 mps)

-65°C to 150°C

Storage Temperature, T_STG

DC Electrical Characteristics

Table 3A. LVPECL Power Supply DC Characteristics, V_CC= 3.3V 5% or 2.5V 5%, T_A= 0°C to 70°C

Symbol Parameter

V_CCCore Supply Voltage

I_EEPower Supply Current

Test Conditions

Minimum

Typical

3.3

Maximum

Units

V

3.135

3.465

200

mA

NOTE 1: Output terminated with 50Ω to V_CC/ 2. See Parameter Measurement Information Section.

Table 3B. Differential DC Characteristics, V_CC= 3.3V 5% or 2.5V 5%, T_A= 0°C to 70°C

Symbol Parameter

I_IHInput High Current

Test Conditions

Minimum

Typical

Maximum

150

Units

µA

V

CLK

nCLK

CLK

150

-5

I_IL

Input Low Current

nCLK

-150

0.15

V_PP

Peak-to-Peak Voltage; NOTE 1

1.3

Common Mode Input Voltage;

NOTE 1, 2

V_CMR

V_EE+ 0.5

V_CC– 0.85

V

NOTE 1: V_ILshould not be less than -0.3V.

NOTE 2: Common mode input voltage is defined as V_IH.

Table 3C. LVPECL DC Characteristics, V_CC= 3.3V 5%, T_A= 0°C to 70°C

Symbol Parameter

Test Conditions

Minimum

V_CC– 1.4

V_CC– 2.0

0.6

Typical

Maximum

V_CC– 0.9

V_CC– 1.7

1.0

Units

V_OH

Output High Voltage; NOTE 1

V

V_OL

Output Low Voltage; NOTE 1

V_SWING

Peak-to-Peak Output Voltage Swing

NOTE 1: Outputs terminated with 50Ω to V_CC– 2V.

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LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER

PRELIMINARY

Table 3D. LVPECL DC Characteristics, V_CC= 2.5V 5%, T_A= 0°C to 70°C

Symbol Parameter

Test Conditions

Minimum

V_CC– 1.4

V_CC– 2.0

0.4

Typical

Maximum

Units

V_OH

Output High Voltage; NOTE 1

V_CC– 0.9

V_CC– 1.5

1.0

V

V_OL

Output Low Voltage; NOTE 1

V_SWING

Peak-to-Peak Output Voltage Swing

NOTE 1: Outputs terminated with 50Ω to V_CC– 2V.

AC Electrical Characteristics

Table 4. AC Characteristics, V_CC= 3.3V 5% or 2.5V 5%, T_A= 0°C to 70°C

Parameter Symbol

f_MAXOutput Frequency

t_PD

Test Conditions

Minimum

Typical

Maximum

1.9

Units

GHz

ps

Propagation Delay; NOTE 1

600

156.25 MHz,

Integration Range: 12kHz – 20MHz

0.149

ps

Additive Phase Jitter, RMS;

NOTE 2

312.5 MHz,

Integration Range: 12kHz – 20MHz

tjit(φ)

0.111

0.44

1GHz,

Integration Range: 12kHz – 20MHz

tsk(o)

tsk(pp)

t_R/ t_F

odc

Output Skew; NOTE 3, 4

Part-to-Part Skew; NOTE 4, 5

Output Rise/Fall Time

Output Duty Cycle

25

TBD

180

50

ps

%

20% to 80%

All parameters are measured at f ≤ 1GHz, unless otherwise noted.

Special thermal considerations may be required. See Applications Section.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Measured on Aeroflex PN9000.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Measured at the output differential cross points.

NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions at

the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

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LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER

PRELIMINARY

Parameter Measurement Information

2V

SCOPE

V

CC

Qx

LVPECL

nQx

V_EE

-1.3V 0.165V

-0.5V 0.125V

3.3V LVPECL Output Load AC Test Circuit

2.5V LVPECL Output Load AC Test Circuit

V

CC

nQx

Qx

nCLK

nQy

V_PP

V_CMR

Cross Points

CLK

Qy

tsk(o)

V

EE

Differential Input Level

Output Skew

Part 1

nQx

nCLK

CLK

Qx

nQ0:nQ21

Part 2

nQy

Q0:Q21

Qy

t_PD

tsk(pp)

Part-to-Part Skew

Propagation Delay

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Parameter Measurement Information, continued

nQ0:nQ21

Q0:Q21

80%

t_R

t_PW

V_SWING

20%

t_PERIOD

Clock

20%

Outputs

t_F

t_PW

t_PERIOD

odc =

x 100%

Output Rise/Fall Time

Output Duty Cycle/Pulse Width/Period

Application Information

Wiring the Differential Input to Accept Single Ended Levels

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V_CC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock

swing is only 2.5V and V_CC= 3.3V, V_REF should be 1.25V and

V_CC

R1

1K

Single Ended Clock Input

R2/R1 = 0.609.

CLK

V_REF

nCLK

C1

0.1u

R2

1K

Figure 1. Single-Ended Signal Driving Differential Input

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PRELIMINARY

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both V_SWINGand V_OHmust meet the

V_PPand V_CMRinput requirements. Figures 2A to 2F show interface

examples for the HiPerClockS CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example, in Figure 2A, the input termination applies for IDT

HiPerClockS open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

recommendation.

3.3V

1.8V

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Zo = 50Ω

HiPerClockS

Input

nCLK

LVPECL

HiPerClockS

LVHSTL

R1

50

R2

50

Input

R1

50

R2

50

IDT

HiPerClockS

LVHSTL Driver

R2

50

Figure 2A. HiPerClockS CLK/nCLK Input

Driven by an IDT Open Emitter

HiPerClockS LVHSTL Driver

Figure 2B. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

3.3V

R3

125

R4

125

3.3V

Zo = 50Ω

CLK

R1

100

nCLK

Zo = 50Ω

HiPerClockS

Input

LVPECL

Receiver

LVDS

R1

84

R2

84

Figure 2C. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2D. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVDS Driver

2.5V

3.3V

2.5V

R3

R4

120

Zo = 50Ω

*R3

*R4

33

Zo = 60Ω

CLK

Zo = 50Ω

nCLK

HiPerClockS

Input

SSTL

HCSL

R1

50

R2

50

R1

120

R2

120

*Optional – R3 and R4 can be 0Ω

Figure 2E. HiPerClockS CLK/nCLK Input

Driven by a 3.3V HCSL Driver

Figure 2F. HiPerClockS CLK/nCLK Input

Driven by a 2.5V SSTL Driver

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PRELIMINARY

Recommendations for Unused Input and Output Pins

Inputs:

Outputs:

CLK/nCLK Inputs

LVPECL Outputs

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1kΩ resistor can be tied from CLK to

ground.

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

transmission lines. Matched impedance techniques should be

used to maximize operating frequency and minimize signal

distortion. Figures 3A and 3B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and

clock component process variations.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50Ω

3.3V

Z_o= 50Ω

125Ω

FOUT

FIN

Z

_o= 50Ω

Z_o= 50Ω

FOUT

FIN

50Ω

V_CC- 2V

1

RTT =

Z_o

RTT

((V_OH+ V_OL) / (V_CC– 2)) – 2

84Ω

Figure 3A. 3.3V LVPECL Output Termination

Figure 3B. 3.3V LVPECL Output Termination

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PRELIMINARY

Termination for 2.5V LVPECL Outputs

Figure 4A and Figure 4B show examples of termination for 2.5V

LVPECL driver. These terminations are equivalent to terminating

50Ω to V_CC– 2V. For V_CC= 2.5V, the V_CC– 2V is very close to

ground level. The R3 in Figure 4B can be eliminated and the

termination is shown in Figure 4C.

2.5V

V_CC= 2.5V

2.5V

V_CC= 2.5V

R1

R3

50Ω

250

+

50Ω

+

–

50Ω

–

2.5V LVPECL Driver

R1

50

R2

50

2.5V LVPECL Driver

R2

62.5

R4

62.5

R3

18

Figure 4A. 2.5V LVPECL Driver Termination Example

Figure 4B. 2.5V LVPECL Driver Termination Example

2.5V

V_CC= 2.5V

50Ω

+

50Ω

–

2.5V LVPECL Driver

R1

50

R2

50

Figure 4C. 2.5V LVPECL Driver Termination Example

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PRELIMINARY

EPAD Thermal Release Path

In order to maximize both the removal of heat from the package

and the electrical performance, a land pattern must be

application specific and dependent upon the package power

dissipation as well as electrical conductivity requirements. Thus,

thermal and electrical analysis and/or testing are recommended to

determine the minimum number needed. Maximum thermal and

electrical performance is achieved when an array of vias is

incorporated in the land pattern. It is recommended to use as many

vias connected to ground as possible. It is also recommended that

the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz

copper via barrel plating. This is desirable to avoid any solder

wicking inside the via during the soldering process which may

result in voids in solder between the exposed pad/slug and the

thermal land. Precautions should be taken to eliminate any solder

voids between the exposed heat slug and the land pattern. Note:

These recommendations are to be used as a guideline only. For

further information, refer to the Application Note on the Surface

Mount Assembly of Amkor’s Thermally/Electrically Enhance

Leadfame Base Package, Amkor Technology.

incorporated on the Printed Circuit Board (PCB) within the footprint

of the package corresponding to the exposed metal pad or

exposed heat slug on the package, as shown in Figure 5. The

solderable area on the PCB, as defined by the solder mask, should

be at least the same size/shape as the exposed pad/slug area on

the package to maximize the thermal/electrical performance.

Sufficient clearance should be designed on the PCB between the

outer edges of the land pattern and the inner edges of pad pattern

for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat

transfer and electrical grounding from the package to the board

through a solder joint, thermal vias are necessary to effectively

conduct from the surface of the PCB to the ground plane(s). The

land pattern must be connected to ground through these vias. The

vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are

SOLDER

EXPOSED HEAT SLUG

LAND PATTERN

(GROUND PAD)

PIN PAD

GROUND PLANE

PIN PAD

THERMAL VIA

Figure 5. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)

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PRELIMINARY

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS853S024.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS853S024 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core)_MAX= V_{CC_MAX}* I_{EE_MAX}= 3.465V * 200mA = 693mW

Power (outputs)_MAX= 30mW/Loaded Output pair

If all outputs are loaded, the total power is 24 * 30mW = 720mW

Total Power__MAX(3.465V, with all outputs switching) = 693W + 720mW = 1.413W

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.

The maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj = θ_JA* Pd_total + T_A

Tj = Junction Temperature

θ_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JAmust be used. Assuming 0 air flow

and a multi-layer board, the appropriate value is 32.5°C/W per Table 5 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 1.413 W * 32.5°C/W = 115.9°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type

of board (single layer or multi-layer).

Table 5. Thermal Resistance θ_JAfor 64 Lead TQFP, EPad, Forced Convection

θ_JAby Velocity

Meters per Second

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

32.5°C/W

26.6°C/W

25.1°C/W

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3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 6.

V_CCO

Q1

V_OUT

RL

50Ω

V_CCO- 2V

Figure 6. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage

of V_CC– 2V.

•

For logic high, V_OUT= V_{OH_MAX}= V_{CC_MAX}– 0.9V

(V_{CC_MAX}– V_{OH_MAX}) = 0.9V

For logic low, V_OUT= V_{OL_MAX}= V_{CC_MAX}– 1.7V

(V_{CC_MAX}– V_{OL_MAX}) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(V_{OH_MAX}– (V_{CC_MAX}– 2V))/R_L] * (V_{CC_MAX}– V_{OH_MAX}) = [(2V – (V_{CC_MAX}– V_{OH_MAX}))/R_L] * (V_{CC_MAX}– V_{OH_MAX}) =

[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW

Pd_L = [(V_{OL_MAX}– (V_{CC_MAX}– 2V))/R_L] * (V_{CC_MAX}– V_{OL_MAX}) = [(2V – (V_{CC_MAX}– V_{OL_MAX}))/R_L] * (V_{CC_MAX}– V_{OL_MAX}) =

[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

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Reliability Information

Table 6. θ_JAvs. Air Flow Table for a 64 Lead TQFP, E-Pad

θ_JAvs. Air Flow

Meters per Second

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

32.5°C/W

26.6°C/W

25.1°C/W

Transistor Count

The transistor count for ICS853S024 is: 8336

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Package Outline and Package Dimensions

Package Outline - Y Suffix for 64 Lead TQFP, E-Pad

-HD VERSION

EXPOSED PAD DOWN

Table 7. Package Dimensions for 64 Lead TQFP, E-Pad

JEDEC Variation: ACD

All Dimensions in Millimeters

Symbol

Minimum

Nominal

Maximum

N

64

A

1.20

0.15

1.05

0.27

0.20

A1

A2

0.05

0.95

0.17

0.09

0.10

1.00

0.22

b

c

D & E

D1 & E1

D2 & E2

D3 & E3

e

12.00 Basic

10.00 Basic

7.50 Ref.

5.0

4.5

5.5

0.50 Basic

0.60

L

0.45

0°

0.75

7°

θ

ccc

0.08

Reference Document: JEDEC Publication 95, MS-026

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Ordering Information

Table 7. Ordering Information

Part/Order Number

853S024AYLF

853S024AYLFT

Marking

ICS853S024AYLF

Package

Lead-Free, 64 Lead TQFP, E-Pad

Shipping Packaging

Tray

500 Tape & Reel

Temperature

0°C to +70°C

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for

the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements

are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any

IDT product for use in life support devices or critical medical instruments.

LOW SKEW LVPECL FANOUT BUFFER

15

ICS853S024AY REV. A APRIL 30, 2008

ICS853S024

LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER

PRELIMINARY

Contact Information:

www.IDT.com

Corporate Headquarters

Sales

Technical Support

Integrated Device Technology, Inc.

800-345-7015 (inside USA)

+408-284-8200 (outside USA)

Fax: 408-284-2775

netcom@idt.com

+480-763-2056

6024 Silver Creek Valley Road

San Jose, CA 95138

United States

800-345-7015 (inside USA)

+408-284-8200 (outside USA)

www.IDT.com/go/contactIDT

Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered

trademarks used to identify products or services of their respective owners.

www.IDT.com

Printed in USA


型号：	ICS853S024
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER 低偏移， 1至24差分至3.3V ， 2.5V LVPECL扇出缓冲器
文件：	总16页 (文件大小：720K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS853S024 [IDT]

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