ICS853S012I [IDT]
12:1, Different ial-to-3.3V, 2.5V LVPECL Clock/Data Mult iplexer;
| 型号： | ICS853S012I |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 12:1, Different ial-to-3.3V, 2.5V LVPECL Clock/Data Mult iplexer |
| 文件： | 总20页 (文件大小：495K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12:1, Differential-to-3.3V, 2.5V
LVPECL Clock/Data Multiplexer
ICS853S012I
Datasheet
Description
Features
The ICS853S012I is an 12:1 Differential-to-3.3V or 2.5V LVPECL
Clock/Data Multiplexer which can operate up to 3.2GHz. The
ICS853S012I has twelve differential selectable clock inputs. The
CLK, nCLK input pairs can accept LVPECL, LVDS or CML levels.
• High speed 12:1 differential multiplexer
• One differential 3.3V or 2.5V LVPECL output
• Twelve selectable differential clock or data inputs
• CLKx, nCLKx pairs can accept the following differential input
The fully differential architecture and low propagation delay make
the device ideal for use in clock distribution circuits. The select
pins have internal pull-down resistors.
levels: LVPECL, LVDS, CML
• Maximum output frequency: 3.2GHz
• Translates any single ended input signal to LVPECL levels with
resistor bias on nCLKx input
• Additive phase jitter, RMS: 0.144ps (typical)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.15ns (maximum)
• Full 3.3V or 2.5V operating supply modes
• -40°C to 85°C ambient operating temperature
• Available lead-free (RoHS 6) package
Block Diagram
Pin Assignment
Pulldown
CLK0
Pullup/Pulldown
nCLK0
Pulldown
Pullup/Pulldown
CLK1
nCLK1
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
CLK2
CLK9
24
23
22
21
20
Pulldown
Pullup/Pulldown
CLK2
nCLK2
nCLK2
VCC
Q
nCLK9
SEL0
Q
nQ
SEL1
SEL2
nQ
VEE
SEL3
CLK8
nCLK8
19
18
17
CLK3
nCLK3
9
10 11 12 13 14 15 16
Pulldown
Pullup/Pulldown
CLK11
nCLK11
ICS853S012I
SEL[3:0]
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
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ICS853S012I Datasheet
Table 1. Pin Descriptions
Number
Name
Type
Pulldown
Description
1
CLK2
Input
Input
Non-inverting differential clock input.
Pullup/
Pulldown
2
nCLK2
VCC
Inverting differential clock input. VCC/2 default when left floating.
3
4, 5
6
Power
Output
Power
Input
Positive supply pin.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Q, nQ
VEE
7
CLK3
Pulldown
Non-inverting differential clock input.
Pullup/
Pulldown
8
nCLK3
Input
Inverting differential clock input. VCC/2 default when left floating.
Pullup/
Pulldown
9
nCLK4
CLK4
Input
Input
Input
Inverting differential clock input. VCC/2 default when left floating.
Inverting differential clock input.
10
11
Pulldown
Pullup/
Pulldown
nCLK5
Inverting differential clock input. VCC/2 default when left floating.
12
13
CLK5
CLK6
Input
Input
Pulldown
Pulldown
Inverting differential clock input.
Non-inverting differential clock input.
Pullup/
Pulldown
14
15
16
nCLK6
CLK7
Input
Input
Input
Inverting differential clock input. VCC/2 default when left floating.
Non-inverting differential clock input.
Pulldown
Pullup/
Pulldown
nCLK7
Inverting differential clock input. VCC/2 default when left floating.
Pullup/
Pulldown
17
18
nCLK8
CLK8
Input
Input
Input
Inverting differential clock input. VCC/2 default when left floating.
Inverting differential clock input.
Pulldown
19, 20,
21, 22
SEL3, SEL2,
SEL1, SEL0
Pulldown
Clock select input pins. LVCMOS/LVTTL interface levels.
Pullup/
Pulldown
23
24
25
26
27
nCLK9
CLK9
Input
Input
Input
Input
Input
Inverting differential clock input. VCC/2 default when left floating.
Inverting differential clock input.
Pulldown
Pullup/
Pulldown
nCLK10
CLK10
nCLK11
Inverting differential clock input. VCC/2 default when left floating.
Inverting differential clock input.
Pulldown
Pullup/
Pulldown
Inverting differential clock input. VCC/2 default when left floating.
28
29
CLK11
CLK0
Input
Input
Pulldown
Pulldown
Inverting differential clock input.
Inverting differential clock input.
Pullup/
Pulldown
30
31
32
nCLK0
CLK1
Input
Input
Input
Inverting differential clock input. VCC/2 default when left floating.
Inverting differential clock input.
Pulldown
Pullup/
Pulldown
nCLK1
Inverting differential clock input. VCC/2 default when left floating.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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ICS853S012I Datasheet
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
k
RPULLDOWN Input Pulldown Resistor
50
50
2
RPULLUP
CIN
Input Pullup Resistor
Input Capacitance
k
SEL[3:0]
pF
Function Table
Table 3. Control Input Function Table
Inputs
Outputs
SEL3
SEL2
SEL1
SEL0
Q
nQ
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
L
nCLK0 (default)
nCLK1
nCLK2
nCLK3
nCLK4
nCLK5
nCLK6
nCLK7
nCLK8
nCLK9
nCLK10
nCLK11
H
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ICS853S012I Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
39.5C/W (1 mps)
-65C to 150C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%; VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
VCC Power Supply Voltage
IEE Power Supply Current
Test Conditions
Minimum
Typical
Maximum
3.465
70
Units
V
3.135
3.3
mA
Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%; VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
VCC Power Supply Voltage
IEE Power Supply Current
Test Conditions
Minimum
Typical
Maximum
2.625
67
Units
V
2.375
2.5
mA
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%; VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
CC = 3.3V
VCC = 2.5V
Minimum
2.2
Typical
Maximum
VCC + 0.3
VCC + 0.3
0.8
Units
V
V
V
V
V
VIH
VIL
Input High Voltage
1.7
V
CC = 3.3V
CC = 2.5V
-0.3
Input Low Voltage
Input
V
-0.3
0.7
IIH
IIL
SEL[3:0]
V
CC = VIN = 3.465V or 2.625V
150
μA
μA
High Current
Input
SEL[3:0]
V
CC = 3.465V or 2.625V, VIN = 0V
-10
Low Current
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ICS853S012I Datasheet
Table 4D. Differential DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%; VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CLK[0:11],
nCLK[0:11]
VCC = VIN = 3.465 or
2.625V
IIH Input High Current
150
μA
VCC = 3.465 or 2.625V,
CLK[0:11]
-10
μA
μA
VIN = 0V
IIL
Input Low Current
VCC = 3.465 or 2.625V,
nCLK[0:11]
-150
VIN = 0V
VPP
Peak-to-Peak Voltage
0.15
1.2
1.5
V
V
VCMR
Common Mode Range; NOTE 1
VCC
NOTE 1: Common mode input voltage is defined as VIH.
Table 4E. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VCC – 1.125
VCC – 1.895
0.6
Typical
Maximum
VCC – 0.935
VCC – 1.670
1.0
Units
VOH
Output High Voltage; NOTE 1
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs termination with 50 to VCC – 2V.
Table 4F. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VCC – 1.125
VCC – 1.895
0.6
Typical
Maximum
VCC – 0.835
VCC – 1.670
1.0
Units
VOH
Output High Voltage; NOTE 1
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs termination with 50 to VCC – 2V.
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ICS853S012I Datasheet
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%; VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
3.2
GHz
fOUT = 155.52MHz, V = 3.3V
Integration Range:
0.144
0.164
ps
ps
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section
12kHz – 20MHz
tjit
f
OUT = 155.52MHz, V = 2.5V
Integration Range:
12kHz – 20MHz
Propagation Delay;
NOTE 1
tPD
CLKx, nCLKx to Q, nQ
425
75
875
250
ps
ps
Part-to-Part Skew;
NOTE 2, 3
tsk(pp)
tsk(i)
Input Skew
60
ps
ps
tR / tF
Output Rise/ Fall Time
20% to 80%
225
fOUT = 155.52MHz,
Input Peak-to-Peak = 800mV
MUXISOLATION
Mux Isolation; NOTE 4
75
dB
NOTE: All parameters characterized up to 1GHz unless noted otherwise.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same
temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential
cross points.
NOTE 3: This parameter is defined in accordance to JEDEC Standard 65.
NOTE 4: Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.
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ICS853S012I Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value
of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental.
When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the
fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.144ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment.
Measured using a Rohde & Schwarz SMA100 as the input source.
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ICS853S012I Datasheet
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
2.5V LVPECL Output Load AC Test Circuit
2V
2V
SCOPE
SCOPE
VCC
Qx
Qx
VCC
nQx
nQx
VEE
VEE
-0.5V±0.125V
-1.3V±0.165V
Differential Input Level
Part-to-Part Skew
V
CC
Part 1
nQx
nCLK[0:11]
Qx
VPP
VCMR
Cross Points
Part 2
CLK[0:11]
nQy
Qy
V
EE
tsk(pp)
Output Rise/Fall Time
Propagation Delay
nCLK[0:11]
CLK[0:11]
nQ
nQ
Q
Q
tPD
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ICS853S012I Datasheet
MUX Isolation
Input Skew
Spectrum of Output Signal Q
nCLKx
MUX selects active
input clock signal
A0
CLKx
nCLKy
CLKy
MUX_ISOLATION = A0 – A1
MUX selects other input
A1
nQ
Q
tPD2
tPD1
ƒ
Frequency
(fundamental)
tsk(i)
tsk(i) = |tPD1 - tPD2
|
x, y = 0 to 11
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission
line impedance.
For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and
weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even
though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet
specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be
larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components
might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications
are characterized and guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
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ICS853S012I Datasheet
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, CML and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figures 2A to 2E show interface examples for the IN/nIN input with built-in 50 terminations driven by the most common
driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
Figure 2A. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2C.CLK/nCLK Input Driven by a
3.3V LVDS Driver
Figure 2D. CLK/nCLK Input Driven by a
Built-In Pullup CML Driver
Figure 2E. CLK/nCLK Input Driven by an
IDT Open Collector CML Driver
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ICS853S012I Datasheet
2.5V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, CML and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figures 3A to 3E show interface examples for the IN/nIN input with built-in 50 terminations driven by the most common
driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
Figure 3A.CLK/nCLK Input Driven by a
2.5V LVPECL Driver
Figure 3B.CLK/nCLK Input Driven by a
2.5V LVPECL Driver
Figure 3C.CLK/nCLK Input Driven by a
2.5V LVDS Driver
Figure 3D.CLK/nCLK Input Driven by a
Built-In Pullup CML Driver
Figure 3E.CLK/nCLK Input Driven by an
IDT Open Collector CML Driver
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ICS853S012I Datasheet
Recommendations for Unused Output Pins
Inputs
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k
resistor can be used.
Outputs
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component
process variations.
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
3.3V
R3
R4
125
125
3.3V
3.3V
Zo = 50
Zo = 50
+
_
Input
R1
84
R2
84
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ICS853S012I Datasheet
Termination for 2.5V LVPECL Outputs
Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to
CC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown
V
in Figure 5C.
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V
2.5V
VCC = 2.5V
2.5V
VCC = 2.5V
R1
R3
250Ω
250Ω
50Ω
50Ω
50Ω
+
+
–
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
2.5V LVPECL Driver
R2
R4
62.5Ω
62.5Ω
R3
18Ω
Figure 5C. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
R2
50Ω
50Ω
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ICS853S012I Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed
on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis
and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is
also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug
and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern.
Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology.
SOLDER
SOLDER
PIN
EXPOSED HEAT SLUG
PIN
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
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ICS853S012I Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853S031I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853S031I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
ꢀ
ꢀ
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 70mA = 242.55mW
Power (outputs)MAX = 31.12mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 242.55mW + 31.12mW = 273.67mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the
bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JAmust be used. Assuming a moderate
air flow of 1 meter per second and a multi-layer board, the appropriate value is 39.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.274W * 39.5°C/W = 95.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
39.5°C/W
34.5°C/W
31.0°C/W
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ICS853S012I Datasheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
VCC - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage
of VCC – 2V.
ꢀ
ꢀ
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.935V
(VCC_MAX – VOH_MAX) = 0.935V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.67V
(VCC_MAX – VOL_MAX) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.67V)/50] * 1.67V = 11.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 31.12mW
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ICS853S012I Datasheet
Reliability Information
Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
39.5°C/W
34.5°C/W
31.0°C/W
Transistor Count
The transistor count for ICS853S031I is: 8264
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ICS853S012I Datasheet
Package Outline Drawings – Page 1
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ICS853S012I Datasheet
Package Outline Drawings – Page 2
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ICS853S012I Datasheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
853S012AKILF
853S012AKILFT
Marking
ICS3S012AIL
ICS3S012AIL
Package
Lead-Free, 32 Lead VFQFN
Lead-Free, 32 Lead VFQFN
Shipping Packaging
Tray
Temperature
-40C to 85C
-40C to 85C
Tape & Reel
Revision History
Date
Description of Change
Updated the electrical characteristics for tPD in Table 5.
Updated the package outline drawings; however, no mechanical changes.
August 23, 2017
Figures 2E, 3E corrected misspelling on Driver
September 28, 2012
Removed quantity from Tape and Reel
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