ICS8432BY-111T [IDT]
PLL Frequency Synthesizer, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32;
| 型号： | ICS8432BY-111T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Frequency Synthesizer, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32 |
| 文件： | 总9页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8432-111
Integrated
Circuit
Systems, Incꢀ
700MHZ/350MHZ, LOW PHASE NOISE,
LVPECLFREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8432-111 is a general purpose, dual output • Fully integrated PLL
,&6
high frequency synthesizer and a member of the
• Accepts any differential input signal (PECL, HSTL, LVDS,
SSTL, etc.)
HiPerClockS™
HiPerClockS™ family of High Performance Clocks
Solutions from ICS. The VCO operates at a fre-
quency range of 250MHz to 700MHz. The VCO
• Accepts any single-ended input signal to LVCMOS with resistor
frequency is programmed in steps equal to the value of the
input differential or single ended reference frequency. Output
frequencies up to 700MHz for FOUT and 350MHz for FOUT/2
can be programmed using the serial or parallel interfaces to
the configuration logic. The low phase noise characteristics and
the multiple frequency outputs of the ICS8432-111 makes it
an ideal clock source for Fiber Channel 1 and 2, and Infiniband
applications.
bias on nCLK input
• 14MHz to 25MHz differential input or reference input frequency
• FOUT and FOUT/2 differential 3.3V LVPECL outputs
• FOUT frequency up to 700MHz
• FOUT/2 frequency up to 350MHz
• Low phase noise
• Parallel interface for programming counter and VCO
frequency multiplier and dividers
• Serial 3 wire interface
• Selectable differential input interface and LVCMOS
reference input
• LVCMOS control inputs
• 3.3V supply voltage
• 32 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.8mm package lead pitch
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
CLK_SEL
REF_CLK
0
1
32 31 30 29 28 27 26 25
CLK
nCLK
M5
M6
M7
M8
N0
N1
nc
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK
REF_CLK
CLK_SEL
VDDA
ICS8432-111
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
0
1
VEE
VCO
FOUT
÷ N
9
10 11 12 13 14 15 16
nFOUT
FOUT/2
nFOUT/2
÷ M
÷ 2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
Y Package
Top View
M0:M8
N0:N1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8432-111
www.icst.com/products/hiperclocks.html
REV. B APRIL 2, 2001
1
PRELIMINARY
ICS8432-111
Integrated
Circuit
Systems, Incꢀ
700MHZ/350MHZ, LOW PHASE NOISE,
LVPECLFREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz clock input. Valid PLL loop divider values for
different input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1 and NOTE 2.
The ICS8432-111 features a fully integrated PLL and therefore requires no external component for setting the loop bandwidth.
A differential clock input is used as the input to the ICS8432-111. This input is fed into the phase detector. A 25MHz clock input
provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz.
The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter divider force the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock.
The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides
a 50% output duty cycle.
The programmable features of the ICS8432-111 support two input modes and programmable PLL loop divider and output
divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel
mode the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the ripple
counter. On the LOW-to-HIGH transition of the nP_LOAD input the data is latched and the ripple counter remains loaded until
the next LOW transition on nP_LOAD or until a serial event occurs. As a result the M and N bits can be hardwired to set the
ripple counter to a specific default state that will automatically occur during power-up. The TEST output is LOW when operat-
ing in the parallel input mode. The relationship between the VCO frequency, the input frequency and the loop divider is defined
as follows:
fVCO = fIN x M
The M count and the required values of M0 through M8 are shown in Table 4B, Programmable VCO Frequency Function.
Valid M values for which the PLL will achieve lock are defined as 10 ≤ M ≤ 28. The frequency out is defined as follows:
fOUT = fVCO = fIN x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the ripple counter when S_LOAD
transitions from LOW-to-HIGH. The ripple counter divide values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH data at the S_DATA input is passed directly to the ripple counter on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the
state of the TEST output as follows:
T1 T0
TEST Output
0
0
1
1
0
1
0
1
LOW
S_Data
Output of M divider
CMOS Fout
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_DATA
S_CLOCK
S_LOAD
M0:M8, N0:N2
nP_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
8432-111
www.icst.com/products/hiperclocks.html
REV. B APRIL 2, 2001
2
PRELIMINARY
ICS8432-111
Integrated
Circuit
Systems, Incꢀ
700MHZ/350MHZ, LOW PHASE NOISE,
LVPECLFREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
1
M5
Input
Input
M counter/divider inputs. Data latched on LOW-to-HIGH transistion
of nP_LOAD input. LVCMOS / LVTTL interface levels.
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Pulldown
Pulldown
Determines output divider value as defined in Table 3C Function
Table. LVCMOS / LVTTL interface levels.
5, 6
N0, N1
Input
7
nc
Unused
Power
Unused pin.
8, 16
VEE
Power supply ground pin. Connect to ground.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS interface levels.
9
TEST
VDD
Output
Power
10
Core power supply pin.
Half frequency differential output for the synthesizer.
3.3V LVPECL interface levels.
11, 12
13
FOUT/2, nFOUT/2 Output
VDDO
Power
Output
Output power supply connection. Connect to 3.3V.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
14, 15
FOUT, nFOUT
Resets the reference frequency and output dividers.
LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLK.
Shift register serial input. Data sampled on the rising edge of
S_CLK.
Controls transition of data from shift register into the ripple counter.
LVCMOS / LVTTL interface levels.
17
18
19
MR
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown
S_CLOCK
S_DATA
20
21
S_LOAD
VDDA
Input
Power
Analog power supply pin. Connect to 3.3V.
Selects between differential clock input or reference input as the
PLL reference source. LVCMOS / LVTTL interface levels. Selects
CLK, nCLK inputs when HIGH. Selects REF_CLK when LOW.
22
CLK_SEL
Input
Pullup
23
24
25
REF_CLK
CLK
Input
Input
Input
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
Pulldown Non-inverting differential clock input. Accepts any differential levels.
nCLK
Pullup
Inverting differential clock input. Accepts any differential levels.
Parallel load input. Determines when data present at M8:M0 is
26
27
nP_LOAD
VCO_SEL
Input
Input
Pulldown loaded into ripple counter, and when data present at N1:N0 sets
the output divide value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS / LVTTL interface levels.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions Minimum Typical Maximum Units
REF_CLK,
CLK, nCLK
M0:M8, S_LOAD,
N0:N1, S_DATA,
VCO_SEL, MR,
pF
Input Capacitance
pF
CLK_SEL,
S_CLOCK,
nP_LOAD
RPULLUP
Input Pullup Resistor
51
51
KΩ
KΩ
RPULLDOWN Input Pulldown Resistor
8432-111
www.icst.com/products/hiperclocks.html
REV. B APRIL 2, 2001
3
PRELIMINARY
ICS8432-111
Integrated
Circuit
Systems, Incꢀ
700MHZ/350MHZ, LOW PHASE NOISE,
LVPECLFREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODES FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
L
X
L
X
X
X
X
X
X
X
X
Reset. M and N counters reset.
Data on M and N inputs passed directly to ripple
counter. TEST output forced LOW.
Data is latched into input registers and remains
loaded until next LOW transition or until a serial
event occurs.
Data Data
L
↑
Data Data
X
X
X
Serial input mode. Shift register is loaded with
data on S_DATA on each rising edge of
S_CLOCK.
Contents of the shift register are passed to the
ripple counter.
L
L
H
H
X
X
X
X
L
↑
Data
Data
↑
L
L
L
H
H
X
X
X
X
↓
L
Data
X
Ripple counter divide values are latched.
L
X
Parallel or serial input do not affect shift registers.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
0
8
M3
1
4
M2
0
2
M1
1
1
M0
0
VCO Frequency
(MHz)
M Count
250
275
300
325
•
10
11
12
13
•
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
675
700
26
27
28
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
1
0
0
NOTE 1: These M count values and the resulting frequency correspond to differential input or reference frequency of
25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Output Frequency
(MHz)
Inputs
N Divider
Value
FOUT
FOUT/2
N1
0
N0
0
Minimum
250
Maximum
700
Minimum
125
Maximum
350
1
2
4
8
0
1
125
350
62.5
175
1
0
62.5
175
31.25
15.625
87.5
1
1
31.25
87.5
43.75
8432-111
www.icst.com/products/hiperclocks.html
REV. B APRIL 2, 2001
4
PRELIMINARY
ICS8432-111
Integrated
Circuit
Systems, Incꢀ
700MHZ/350MHZ, LOW PHASE NOISE,
LVPECLFREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Inputs
4.6V
-0.5V to VDD+0.5 V
-0.5V to VDD+0.5V
Outputs
Ambient Operating Temperature 0°C to 70°C
Storage Temperature -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any conditions beyond those listed in the DC Character-
istics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD, VDDA, VDDO Power Supply Voltage
3.135
3.3
3.465
110
V
IEE
Core Power Supply Current
Analog Power Supply Current
mA
mA
IDDA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK
VIN = 3.465V
VIN = 3.465V
VIN = 0V
150
5
µA
µA
µA
µA
IIH
IIL
Input High Current
nCLK
CLK
-5
Input Low Current
nCLK
VIN = 0V
-150
VPP
Peak-to-Peak Input Voltage
Common Mode Input Voltage
VCMR
8432-111
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REV. B APRIL 2, 2001
5
PRELIMINARY
ICS8432-111
Integrated
Circuit
Systems, Incꢀ
700MHZ/350MHZ, LOW PHASE NOISE,
LVPECLFREQUENCY SYNTHESIZER
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
VCO_SEL, CLK_SEL, S_LOAD,
S_DATA, S_CLOCK, nP_LOAD,
N0:N1, M0:M8, MR
VDDI = 3.465V
VDDI = 3.465V
VDDI = 3.135V
VDDI = 3.135V
2
3.765
3.765
0.8
V
V
Input
VIH
High Voltage
REF_CLK
1.7
-0.3
VCO_SEL, CLK_SEL, S_LOAD,
S_DATA, S_CLOCK, nP_LOAD,
N0:N1, M0:M8, MR
V
Input
VIL
Low Voltage
REF_CLK
1.3
V
M0-M4, M6-M8, N0, N1,
S_CLOCK, S_DATA, S_LOAD,
REF_CLK, nP_LOAD, MR
VDDx = VIN =
3.465V
150
µA
Input
IIH
High Current
VDDx = VIN =
3.465V
M5, CLK_SEL, VCO_SEL
5
µA
µA
M0-M4, M6-M8, N0, N1,
S_CLOCK, S_DATA, S_LOAD,
REF_CLK, nP_LOAD, MR
VDDx = 3.465V,
VIN = 0V
-5
Input
IIL
Low Current
VDDx = 3.465V,
VIN = 0V
VDDx = 3.135V,
IOH = -36mA
VDDx = 3.135V,
IOL = 36mA
M5, CLK_SEL, VCO_SEL
-150
2.6
µA
V
Output
VOH
TEST
TEST
High Voltage
Output
Low Voltage
VOL
0.5
V
TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT,
Output High Voltage;
NOTE 1, 2
nFOUT,
FOUT/2,
nFOUT/2
FOUT,
nFOUT,
FOUT/2,
nFOUT/2
FOUT,
VOH
VDDx = 3.3V
2.1
V
V
V
Output Low Voltage;
NOTE 1, 2
VOL
VDDx = 3.3V
1.6
Peak-to-Peak
Output Voltage Swing FOUT/2,
nFOUT/2
nFOUT,
VSWING
3.135V ≤ VDDx ≤ 3.465V
0.6
0.85
NOTE 1: FOUT, nFOUT, FOUT/2, nFOUT/2 outputs terminated with 50 Ω to VDDO - 2V.
NOTE 2: These levels are specified for VDDO = 3.3V. Output levels will vary 1:1 with VDDO.
8432-111
www.icst.com/products/hiperclocks.html
REV. B APRIL 2, 2001
6
PRELIMINARY
ICS8432-111
Integrated
Circuit
Systems, Incꢀ
700MHZ/350MHZ, LOW PHASE NOISE,
LVPECLFREQUENCY SYNTHESIZER
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
REF_CLK;
NOTE 1
CLK, nCLK;
NOTE 1
14
14
25
25
MHz
MHz
Maximum Input
Frequency
fIN
S_CLOCK
REF_CLK
CLK, nCLK
REF_CLK
CLK, nCLK
REF_CLK
CLK, nCLK
TBD
TBD
MHz
ns
Measured at 20% to 80% points
Measured at 20% to 80% point
tR
Input Rise Time
Input Fall Time
TBD
TBD
ns
%
tF
TBD
Input Reference
Duty Cycle
tDC
NOTE 1: For the differential input and reference frequency range the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 14MHz valid values of M are 18 ≤ M ≤ 50. Using the
maximum frequency of 25MHz valid values of M are 10 ≤ M ≤ 28.
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
Units
MHz
FOUT
Output Frequency
3.135 ≤ VDDx ≤ 3.465V
125MHZ, 1KHz offset
125MHZ, 10KHz offset
125MHZ, 100KHz offset
31.25
700
dBc/Hz
dBc/Hz
dBc/Hz
ps
ØNOISE Single Side Band Phase Noise
tsk(o)
tDC
Output Skew
Output Duty Cycle
47
53
%
FOUT, nFOUT
FOUT/2, nFOUT/2
FOUT, nFOUT
tR
tF
Output Rise Time
Output Fall Time
20% to 80%
20% to 80%
300
800
ps
300
TBD
TBD
800
ps
ns
ns
FOUT/2, nFOUT/2
M, N to nP_LOAD
S_DATA to
S_CLOCK
S_CLOCK to
S_LOAD
tS
tH
Setup Time
Hold Time
TBD
TBD
TBD
ns
ns
ns
M, N to nP_LOAD
S_DATA to
S_CLOCK
S_CLOCK to
S_LOAD
TBD
ns
tLOCK
tPW
PLL Lock Time
Pulse Width
TBD
TBD
TBD
ms
ns
ns
nP_LOAD
S_LOAD
8432-111
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REV. B APRIL 2, 2001
7
PRELIMINARY
ICS8432-111
Integrated
Circuit
Systems, Incꢀ
700MHZ/350MHZ, LOW PHASE NOISE,
LVPECLFREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX
D
D2
θ
32
25
24
1
2
3
L
E
E1
E2
N
8
17
16
9
e
D1
A
C
A2
SEATING
PLANE
-C-
ccc
b
A1
c
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
D
9.00 BASIC
7.00 BASIC
5.60
D1
D2
E
9.00 BASIC
7.00 BASIC
5.60
E1
E2
e
0.80 BASIC
0.60
L
0.45
0.75
0°
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
8432-111
www.icst.com/products/hiperclocks.html
REV. B APRIL 2, 2001
8
PRELIMINARY
ICS8432-111
Integrated
Circuit
Systems, Incꢀ
700MHZ/350MHZ, LOW PHASE NOISE,
LVPECLFREQUENCY SYNTHESIZER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS8432BY-111
Marking
Package
32 Lead LQFP
Count
250 per tray
2000
Temperature
0°C to 70°C
0°C to 70°C
ICS8432BY-111
ICS8432BY-111
ICS8432BY-111T
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8432-111
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REV. B APRIL 2, 2001
9
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